diff options
| author | Zheng Bao <fishbaozi@gmail.com> | 2022-02-11 11:53:32 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-12 17:07:09 +0000 |
| commit | c5b912f788765560c1db08f3341826b9c548b865 (patch) | |
| tree | 4a825193a60a1bb4e7012918bf772649abd29593 /src/soc/amd/cezanne/Kconfig | |
| parent | 514965a9ce2ea698e6a67d3b7dd38e98381e3699 (diff) | |
soc/amd/cezanne: Allow to specify SPL table path in Kconfig
BUG=b:216096562
Change-Id: I4a5ee335ea8808b595dc65ebafd15baedfbdd06e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 40ba4c1024..c0c500d3fa 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -377,6 +377,20 @@ config PSP_WHITELIST_FILE depends on HAVE_PSP_WHITELIST_FILE default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" +config HAVE_SPL_FILE + bool "Have a mainboard specific SPL table file" + default n + help + Have a mainboard specific SPL table file, which is created by AMD + and put to 3rdparty/blobs. + + If unsure, answer 'n' + +config SPL_TABLE_FILE + string "SPL table file" + depends on HAVE_SPL_FILE + default "3rdparty/amd_blobs/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin" + config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" default "28 6" |