From c5b912f788765560c1db08f3341826b9c548b865 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Fri, 11 Feb 2022 11:53:32 +0800 Subject: soc/amd/cezanne: Allow to specify SPL table path in Kconfig BUG=b:216096562 Change-Id: I4a5ee335ea8808b595dc65ebafd15baedfbdd06e Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/c/coreboot/+/61837 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/Kconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/soc/amd/cezanne/Kconfig') diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 40ba4c1024..c0c500d3fa 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -377,6 +377,20 @@ config PSP_WHITELIST_FILE depends on HAVE_PSP_WHITELIST_FILE default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" +config HAVE_SPL_FILE + bool "Have a mainboard specific SPL table file" + default n + help + Have a mainboard specific SPL table file, which is created by AMD + and put to 3rdparty/blobs. + + If unsure, answer 'n' + +config SPL_TABLE_FILE + string "SPL table file" + depends on HAVE_SPL_FILE + default "3rdparty/amd_blobs/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin" + config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" default "28 6" -- cgit v1.2.3