diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2024-10-04 13:20:48 +0100 |
|---|---|---|
| committer | Sean Rhodes <sean@starlabs.systems> | 2024-10-11 11:27:42 +0000 |
| commit | 5072fb19644cfaaa4d39144b2e5ca7b7c899c0f2 (patch) | |
| tree | 1852084b9dfdefc2138b9bfbca8e72f511ea9691 /src/mainboard/starlabs/starbook/variants/tgl/devtree.c | |
| parent | 9820363f5fbb6166d5d84543eb3038b643301168 (diff) | |
mb/starlabs/*: Rework the performance profiles
Rather than hardcoded values, simply change these to -25% of the
defaults for Power Saving, and +25% for Performance.
Change-Id: I16aeb4d5dc25a3f240a775509276c9d3189e9699
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84661
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/starlabs/starbook/variants/tgl/devtree.c')
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/tgl/devtree.c | 22 |
1 files changed, 10 insertions, 12 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c index 4013d7758f..b6422f53a8 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c @@ -23,32 +23,30 @@ void devtree_update(void) struct device *tbt_pci_dev = pcidev_on_root(0x07, 0); struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2); + uint8_t performance_scale = 100; /* Update PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: - soc_conf_2core->tdp_pl1_override = 15; - soc_conf_4core->tdp_pl1_override = 15; - soc_conf_2core->tdp_pl2_override = 15; - soc_conf_4core->tdp_pl2_override = 15; + performance_scale -= 25; cfg->tcc_offset = 30; break; case PP_BALANCED: - soc_conf_2core->tdp_pl1_override = 15; - soc_conf_4core->tdp_pl1_override = 15; - soc_conf_2core->tdp_pl2_override = 25; - soc_conf_4core->tdp_pl2_override = 25; + /* Use the Intel defaults */ cfg->tcc_offset = 25; break; case PP_PERFORMANCE: - soc_conf_2core->tdp_pl1_override = 28; - soc_conf_4core->tdp_pl1_override = 28; - soc_conf_2core->tdp_pl2_override = 40; - soc_conf_4core->tdp_pl2_override = 40; + performance_scale += 25; cfg->tcc_offset = 20; break; } + soc_conf_2core->tdp_pl1_override = (soc_conf_2core->tdp_pl1_override * performance_scale) / 100; + soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100; + + soc_conf_2core->tdp_pl2_override = (soc_conf_2core->tdp_pl1_override * performance_scale) / 100; + soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100; + /* Set PL4 to 1.0C */ soc_conf_2core->tdp_pl4 = 65; soc_conf_4core->tdp_pl4 = 65; |