mb/starlabs/*: Rework the performance profiles

Rather than hardcoded values, simply change these to -25% of the
defaults for Power Saving, and +25% for Performance.

Change-Id: I16aeb4d5dc25a3f240a775509276c9d3189e9699
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84661
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 83 insertions, 78 deletions

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
index 925d9f0082..ae87d6a5db 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
@@ -21,25 +21,27 @@ void devtree_update(void)
 
 	struct device *nic_dev = pcidev_on_root(0x14, 3);
 
+	uint8_t performance_scale = 100;
+
 	/* Update PL1 & PL2 based on CMOS settings */
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
-		soc_conf_4core->tdp_pl1_override	= 6;
-		soc_conf_4core->tdp_pl2_override	= 10;
+		performance_scale -= 25;
 		common_config->pch_thermal_trip		= 30;
 		break;
 	case PP_BALANCED:
-		soc_conf_4core->tdp_pl1_override	= 10;
-		soc_conf_4core->tdp_pl2_override	= 25;
+		/* Use the Intel defaults */
 		common_config->pch_thermal_trip		= 25;
 		break;
 	case PP_PERFORMANCE:
-		soc_conf_4core->tdp_pl1_override	= 20;
-		soc_conf_4core->tdp_pl2_override	= 35;
+		performance_scale += 25;
 		common_config->pch_thermal_trip		= 20;
 		break;
 	}
 
+	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
+
 	/* Set PL4 to 1.0C */
 	soc_conf_4core->tdp_pl4				= 36;
 
diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c
index 82517df36e..2e192e3548 100644
--- a/src/mainboard/starlabs/lite/devtree.c
+++ b/src/mainboard/starlabs/lite/devtree.c
@@ -25,25 +25,27 @@ void devtree_update(void)
 
 	struct device *nic_dev = pcidev_on_root(0x0c, 0);
 
+	uint8_t performance_scale = 100;
+
 	/* Update PL1 & PL2 based on CMOS settings */
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
-		soc_conf->tdp_pl1_override	= 6;
-		soc_conf->tdp_pl2_override	= 10;
+		performance_scale -= 25;
 		cfg->tcc_offset			= 15;
 		break;
 	case PP_BALANCED:
-		soc_conf->tdp_pl1_override	= 10;
-		soc_conf->tdp_pl2_override	= 15;
+		/* Use the Intel defaults */
 		cfg->tcc_offset			= 10;
 		break;
 	case PP_PERFORMANCE:
-		soc_conf->tdp_pl1_override	= 10;
-		soc_conf->tdp_pl2_override	= 20;
+		performance_scale += 25;
 		cfg->tcc_offset			= 5;
 		break;
 	}
 
+	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100;
+	soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
+
 	/* Set PL4 to 1.0C */
 	soc_conf->tdp_pl4			= 31;
 
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
index b99e432dd6..e7fc786481 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
@@ -22,31 +22,30 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_12core =
 		&cfg->power_limits_config[ADL_P_682_28W_CORE];
 
+	uint8_t performance_scale = 100;
+
 	/* Update PL1 & PL2 based on CMOS settings */
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
-		soc_conf_10core->tdp_pl1_override	= 15;
-		soc_conf_12core->tdp_pl1_override	= 15;
-		soc_conf_10core->tdp_pl2_override	= 15;
-		soc_conf_12core->tdp_pl2_override	= 15;
+		performance_scale -= 25;
 		common_config->pch_thermal_trip		= 20;
 		break;
 	case PP_BALANCED:
-		soc_conf_10core->tdp_pl1_override	= 15;
-		soc_conf_12core->tdp_pl1_override	= 15;
-		soc_conf_10core->tdp_pl2_override	= 25;
-		soc_conf_12core->tdp_pl2_override	= 25;
+		/* Use the Intel defaults */
 		common_config->pch_thermal_trip		= 15;
 		break;
 	case PP_PERFORMANCE:
-		soc_conf_10core->tdp_pl1_override	= 28;
-		soc_conf_12core->tdp_pl1_override	= 28;
-		soc_conf_10core->tdp_pl2_override	= 40;
-		soc_conf_12core->tdp_pl2_override	= 40;
+		performance_scale += 25;
 		common_config->pch_thermal_trip		= 10;
 		break;
 	}
 
+	soc_conf_10core->tdp_pl1_override = (soc_conf_10core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_12core->tdp_pl1_override = (soc_conf_12core->tdp_pl2_override * performance_scale) / 100;
+
+	soc_conf_10core->tdp_pl2_override = (soc_conf_10core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_12core->tdp_pl2_override = (soc_conf_12core->tdp_pl2_override * performance_scale) / 100;
+
 	/* Set PL4 to 1.0C */
 	soc_conf_10core->tdp_pl4			= 65;
 	soc_conf_12core->tdp_pl4			= 65;
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
index a38fcd47a5..1496754e8b 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
@@ -17,25 +17,27 @@ void devtree_update(void)
 
 	struct device *nic_dev = pcidev_on_root(0x14, 3);
 
+	uint8_t performance_scale = 100;
+
 	/* Update PL1 & PL2 based on CMOS settings */
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
-		soc_conf->tdp_pl1_override	= 15;
-		soc_conf->tdp_pl2_override	= 15;
+		performance_scale -= 25;
 		cfg->tcc_offset			= 20;
 		break;
 	case PP_BALANCED:
-		soc_conf->tdp_pl1_override	= 17;
-		soc_conf->tdp_pl2_override	= 20;
+		/* Use the Intel defaults */
 		cfg->tcc_offset			= 15;
 		break;
 	case PP_PERFORMANCE:
-		soc_conf->tdp_pl1_override	= 20;
-		soc_conf->tdp_pl2_override	= 25;
+		performance_scale += 25;
 		cfg->tcc_offset			= 10;
 		break;
 	}
 
+	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100;
+	soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
+
 	/* Set PL4 to 1.0C */
 	soc_conf->tdp_pl4			= 45;
 
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
index 26adaf2adb..a5b13b8841 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
@@ -17,25 +17,27 @@ void devtree_update(void)
 
 	struct device *nic_dev = pcidev_on_root(0x1c, 5);
 
+	uint8_t performance_scale = 100;
+
 	/* Update PL1 & PL2 based on CMOS settings */
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
-		soc_conf->tdp_pl1_override	= 15;
-		soc_conf->tdp_pl2_override	= 15;
+		performance_scale -= 25;
 		cfg->tcc_offset			= 20;
 		break;
 	case PP_BALANCED:
-		soc_conf->tdp_pl1_override	= 17;
-		soc_conf->tdp_pl2_override	= 20;
+		/* Use the Intel defaults */
 		cfg->tcc_offset			= 15;
 		break;
 	case PP_PERFORMANCE:
-		soc_conf->tdp_pl1_override	= 20;
-		soc_conf->tdp_pl2_override	= 25;
+		performance_scale += 25;
 		cfg->tcc_offset			= 10;
 		break;
 	}
 
+	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100;
+	soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
+
 	/* Set PL4 to 1.0C */
 	soc_conf->tdp_pl4			= 45;
 
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
index 3b47058a27..5eea89ffe9 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
@@ -25,31 +25,30 @@ void devtree_update(void)
 	struct device *tbt_pci_dev = pcidev_on_root(0x07, 0);
 	struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
 
+	uint8_t performance_scale = 100;
+
 	/* Update PL1 & PL2 based on CMOS settings */
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
-		soc_conf_6core->tdp_pl1_override	= 15;
-		soc_conf_12core->tdp_pl1_override	= 15;
-		soc_conf_6core->tdp_pl2_override	= 15;
-		soc_conf_12core->tdp_pl2_override	= 15;
+		performance_scale -= 25;
 		common_config->pch_thermal_trip		= 30;
 		break;
 	case PP_BALANCED:
-		soc_conf_6core->tdp_pl1_override	= 15;
-		soc_conf_12core->tdp_pl1_override	= 15;
-		soc_conf_6core->tdp_pl2_override	= 20;
-		soc_conf_12core->tdp_pl2_override	= 25;
+		/* Use the Intel defaults */
 		common_config->pch_thermal_trip		= 25;
 		break;
 	case PP_PERFORMANCE:
-		soc_conf_6core->tdp_pl1_override	= 15;
-		soc_conf_12core->tdp_pl1_override	= 28;
-		soc_conf_6core->tdp_pl2_override	= 25;
-		soc_conf_12core->tdp_pl2_override	= 40;
+		performance_scale += 25;
 		common_config->pch_thermal_trip		= 20;
 		break;
 	}
 
+	soc_conf_6core->tdp_pl1_override = (soc_conf_6core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_6core->tdp_pl2_override = (soc_conf_6core->tdp_pl2_override * performance_scale) / 100;
+
+	soc_conf_12core->tdp_pl1_override = (soc_conf_12core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_12core->tdp_pl2_override = (soc_conf_12core->tdp_pl2_override * performance_scale) / 100;
+
 	/* Set PL4 to 1.0C */
 	soc_conf_6core->tdp_pl4				= 65;
 	soc_conf_12core->tdp_pl4			= 65;
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
index 4013d7758f..b6422f53a8 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
@@ -23,32 +23,30 @@ void devtree_update(void)
 	struct device *tbt_pci_dev = pcidev_on_root(0x07, 0);
 	struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
 
+	uint8_t performance_scale = 100;
 
 	/* Update PL1 & PL2 based on CMOS settings */
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
-		soc_conf_2core->tdp_pl1_override	= 15;
-		soc_conf_4core->tdp_pl1_override	= 15;
-		soc_conf_2core->tdp_pl2_override	= 15;
-		soc_conf_4core->tdp_pl2_override	= 15;
+		performance_scale -= 25;
 		cfg->tcc_offset				= 30;
 		break;
 	case PP_BALANCED:
-		soc_conf_2core->tdp_pl1_override	= 15;
-		soc_conf_4core->tdp_pl1_override	= 15;
-		soc_conf_2core->tdp_pl2_override	= 25;
-		soc_conf_4core->tdp_pl2_override	= 25;
+		/* Use the Intel defaults */
 		cfg->tcc_offset				= 25;
 		break;
 	case PP_PERFORMANCE:
-		soc_conf_2core->tdp_pl1_override	= 28;
-		soc_conf_4core->tdp_pl1_override	= 28;
-		soc_conf_2core->tdp_pl2_override	= 40;
-		soc_conf_4core->tdp_pl2_override	= 40;
+		performance_scale += 25;
 		cfg->tcc_offset				= 20;
 		break;
 	}
 
+	soc_conf_2core->tdp_pl1_override = (soc_conf_2core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
+
+	soc_conf_2core->tdp_pl2_override = (soc_conf_2core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
+
 	/* Set PL4 to 1.0C */
 	soc_conf_2core->tdp_pl4				= 65;
 	soc_conf_4core->tdp_pl4				= 65;
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
index ec72aa68c7..5d2b8f6973 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
@@ -25,31 +25,30 @@ void devtree_update(void)
 	struct device *tbt_pci_dev_1 = pcidev_on_root(0x07, 0);
 	struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
 
+	uint8_t performance_scale = 100;
+
 	/* Update PL1 & PL2 based on CMOS settings */
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
-		soc_conf_6core->tdp_pl1_override	= 15;
-		soc_conf_14core->tdp_pl1_override	= 15;
-		soc_conf_6core->tdp_pl2_override	= 15;
-		soc_conf_14core->tdp_pl2_override	= 15;
+		performance_scale -= 25;
 		common_config->pch_thermal_trip		= 30;
 		break;
 	case PP_BALANCED:
-		soc_conf_6core->tdp_pl1_override	= 15;
-		soc_conf_14core->tdp_pl1_override	= 15;
-		soc_conf_6core->tdp_pl2_override	= 20;
-		soc_conf_14core->tdp_pl2_override	= 25;
+		/* Use the Intel defaults */
 		common_config->pch_thermal_trip		= 25;
 		break;
 	case PP_PERFORMANCE:
-		soc_conf_6core->tdp_pl1_override	= 15;
-		soc_conf_14core->tdp_pl1_override	= 28;
-		soc_conf_6core->tdp_pl2_override	= 25;
-		soc_conf_14core->tdp_pl2_override	= 40;
+		performance_scale += 25;
 		common_config->pch_thermal_trip		= 20;
 		break;
 	}
 
+	soc_conf_6core->tdp_pl1_override = (soc_conf_6core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_6core->tdp_pl2_override = (soc_conf_6core->tdp_pl2_override * performance_scale) / 100;
+
+	soc_conf_14core->tdp_pl1_override = (soc_conf_14core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_14core->tdp_pl2_override = (soc_conf_14core->tdp_pl2_override * performance_scale) / 100;
+
 	/* Set PL4 to 1.0C */
 	soc_conf_6core->tdp_pl4				= 65;
 	soc_conf_14core->tdp_pl4			= 65;
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
index 075cc70e47..8c35c5ce24 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
@@ -23,25 +23,27 @@ void devtree_update(void)
 	struct device *touchscreen_dev = pcidev_on_root(0x15, 2);
 	struct device *accelerometer_dev = pcidev_on_root(0x15, 0);
 
+	uint8_t performance_scale = 100;
+
 	/* Update PL1 & PL2 based on CMOS settings */
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
-		soc_conf_4core->tdp_pl1_override	= 6;
-		soc_conf_4core->tdp_pl2_override	= 10;
+		performance_scale -= 25;
 		common_config->pch_thermal_trip		= 30;
 		break;
 	case PP_BALANCED:
-		soc_conf_4core->tdp_pl1_override	= 10;
-		soc_conf_4core->tdp_pl2_override	= 25;
+		/* Use the Intel defaults */
 		common_config->pch_thermal_trip		= 25;
 		break;
 	case PP_PERFORMANCE:
-		soc_conf_4core->tdp_pl1_override	= 20;
-		soc_conf_4core->tdp_pl2_override	= 35;
+		performance_scale += 25;
 		common_config->pch_thermal_trip		= 20;
 		break;
 	}
 
+	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
+
 	/* Set PL4 to 1.0C */
 	soc_conf_4core->tdp_pl4				= 37;