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authorElyes Haouas <ehaouas@noos.fr>2024-08-31 10:57:18 +0200
committerElyes Haouas <ehaouas@noos.fr>2024-09-01 04:58:51 +0000
commitb1ae6ca7ef8b848e53577cb9da46c19d2d5886a8 (patch)
tree8900b50b15d8934d7a1d8efc711ca8e7498ffe0d /src/mainboard/intel/coffeelake_rvp/variants
parentf3d54feef4c700991dd11b012f810162c5b6b06a (diff)
tree: Use boolean for s0ix_enable
Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/coffeelake_rvp/variants')
-rw-r--r--src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb2
-rw-r--r--src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
index bee71aa615..012afc41f8 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
@@ -40,7 +40,7 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[5]" = "5"
# Disable S0ix
- register "s0ix_enable" = "0"
+ register "s0ix_enable" = "false"
device domain 0 on
device pci 00.0 on end # Host Bridge
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
index 0ba9e83469..e49c102708 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
@@ -38,7 +38,7 @@ chip soc/intel/cannonlake
register "sdcard_cd_gpio" = "GPP_G5"
# Enable S0ix
- register "s0ix_enable" = "1"
+ register "s0ix_enable" = "true"
# Intel Common SoC Config
#+-------------------+---------------------------+