From b1ae6ca7ef8b848e53577cb9da46c19d2d5886a8 Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Sat, 31 Aug 2024 10:57:18 +0200 Subject: tree: Use boolean for s0ix_enable Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb | 2 +- src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/intel/coffeelake_rvp/variants') diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index bee71aa615..012afc41f8 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -40,7 +40,7 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[5]" = "5" # Disable S0ix - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index 0ba9e83469..e49c102708 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -38,7 +38,7 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "GPP_G5" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ -- cgit v1.2.3