diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-08-31 10:57:18 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-09-01 04:58:51 +0000 |
| commit | b1ae6ca7ef8b848e53577cb9da46c19d2d5886a8 (patch) | |
| tree | 8900b50b15d8934d7a1d8efc711ca8e7498ffe0d /src/mainboard/intel | |
| parent | f3d54feef4c700991dd11b012f810162c5b6b06a (diff) | |
tree: Use boolean for s0ix_enable
Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel')
10 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 68c0754bd6..95b006e2f6 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -132,7 +132,7 @@ chip soc/intel/alderlake # TCSS USB3 register "tcss_aux_ori" = "0" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "dptf_enable" = "1" register "serial_io_i2c_mode" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index ec6089452f..0b3a3efea0 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -95,7 +95,7 @@ chip soc/intel/alderlake # TCSS USB3 register "tcss_aux_ori" = "0" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index 6776284fe0..c01613c296 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -70,7 +70,7 @@ chip soc/intel/alderlake register "tcss_aux_ori" = "4" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index bee71aa615..012afc41f8 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -40,7 +40,7 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[5]" = "5" # Disable S0ix - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index 0ba9e83469..e49c102708 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -38,7 +38,7 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "GPP_G5" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 59d69dc28f..1495366a88 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -150,7 +150,7 @@ chip soc/intel/jasperlake }" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # GPIO for SD card detect register "sdcard_cd_gpio" = "VGPIO_39" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 010cae2b00..e97d19e0de 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -50,7 +50,7 @@ chip soc/intel/meteorlake register "cnvi_bt_core" = "true" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index fb55da4362..b864da6c05 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -19,7 +19,7 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port A0 register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Type-A Port A1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b82f583c76..69ec54636c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -68,7 +68,7 @@ chip soc/intel/tigerlake register "TcssAuxOri" = "0" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 51895b2c9d..fbb8418ff9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -75,7 +75,7 @@ chip soc/intel/tigerlake register "TcssAuxOri" = "0" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" |