diff options
| author | Nico Huber <nico.huber@secunet.com> | 2019-10-02 16:02:06 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-08-23 09:57:02 +0000 |
| commit | 119ace0908b66b718c4b581423309648b10e4bf7 (patch) | |
| tree | b9ed4510a9081065c35af99a06446a74b3db82c1 /src/mainboard/google/hatch/variants/noibat | |
| parent | 2b9035ed6e51fe835b85dd626e655e1d3901e7ea (diff) | |
soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.
Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/google/hatch/variants/noibat')
| -rw-r--r-- | src/mainboard/google/hatch/variants/noibat/overridetree.cb | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb index 2de90ec8e2..c73798a9a8 100644 --- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb +++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb @@ -309,8 +309,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end |