soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.

Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

10 files changed, 46 insertions, 11 deletions

diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 4011693d34..851248d77d 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -444,12 +444,14 @@ chip soc/intel/cannonlake
 		device pci 1c.7 off end # PCI Express Port 8
 		device pci 1d.0 on
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
+			register "PcieRpSlotImplemented[8]" = "1"
 		end # PCI Express Port 9
 		device pci 1d.1 off  end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off  end # PCI Express Port 12
 		device pci 1d.4 on
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[12]" = "1"
 		end # PCI Express Port 13 (x4)
 		device pci 1e.0 on end # UART #0
 		device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index a12b71cfbd..f13fcf8f9a 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -329,7 +329,9 @@ chip soc/intel/cannonlake
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9 (X4 NVME)
+		device pci 1d.0 on	# PCI Express Port 9 (X4 NVME)
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
@@ -339,6 +341,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_01"
 				device pci 00.0 on  end
 			end
+			register "PcieRpSlotImplemented[13]" = "1"
 		end # PCI Express Port 14 (x4)
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
index 7f75c78e26..10da16163d 100644
--- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
@@ -394,8 +394,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
index c1c44a69e9..61c7f0f242 100644
--- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
@@ -401,8 +401,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
index 67e62e7d08..dbf1851f32 100644
--- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
@@ -394,8 +394,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
index 2de90ec8e2..c73798a9a8 100644
--- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
@@ -309,8 +309,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index 7ead982c08..a5aa702890 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -333,8 +333,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
index d7b2298a06..3d5da00040 100644
--- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
@@ -328,8 +328,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index bacc6dceb7..760e35146e 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -377,8 +377,11 @@ chip soc/intel/cannonlake
 		device pci 1d.0 off end # PCI Express Port 9
 		device pci 1d.1 on
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
+			register "PcieRpSlotImplemented[9]" = "1"
 		end # PCI Express Port 10
-		device pci 1d.2 on  end # PCI Express Port 11
+		device pci 1d.2 on	# PCI Express Port 11
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1d.4 on
 			chip drivers/generic/bayhub
@@ -386,6 +389,7 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[12]" = "1"
 		end # PCI Express Port 13 (x4)
 		device pci 1e.0 off end # UART #0
 		device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index e79a8a5aeb..78f024cbf4 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -385,22 +385,29 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 off end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 (USB)
+		device pci 1c.0 on	# PCI Express Port 1 (USB)
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
 		device pci 1c.1 off end # PCI Express Port 2 (USB)
 		device pci 1c.2 off end # PCI Express Port 3 (USB)
 		device pci 1c.3 off end # PCI Express Port 4 (USB)
 		device pci 1c.4 off end # PCI Express Port 5 (USB)
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 on  end # PCI Express Port 8
+		device pci 1c.7 on	# PCI Express Port 8
+			register "PcieRpSlotImplemented[7]" = "1"
+		end
 		device pci 1d.0 on
 			chip drivers/generic/bayhub
 				register "power_saving" = "1"
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
+			register "PcieRpSlotImplemented[8]" = "1"
 		end # PCI Express Port 9
-		device pci 1d.1 on  end # PCI Express Port 10
+		device pci 1d.1 on	# PCI Express Port 10
+			register "PcieRpSlotImplemented[9]" = "1"
+		end
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1d.4 on
@@ -409,6 +416,7 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[12]" = "1"
 		end # PCI Express Port 13 (x4)
 		device pci 1e.0 off end # UART #0
 		device pci 1e.1 off end # UART #1