soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.

Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

23 files changed, 171 insertions, 50 deletions

diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 4011693d34..851248d77d 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -444,12 +444,14 @@ chip soc/intel/cannonlake
 		device pci 1c.7 off end # PCI Express Port 8
 		device pci 1d.0 on
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
+			register "PcieRpSlotImplemented[8]" = "1"
 		end # PCI Express Port 9
 		device pci 1d.1 off  end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off  end # PCI Express Port 12
 		device pci 1d.4 on
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[12]" = "1"
 		end # PCI Express Port 13 (x4)
 		device pci 1e.0 on end # UART #0
 		device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index a12b71cfbd..f13fcf8f9a 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -329,7 +329,9 @@ chip soc/intel/cannonlake
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9 (X4 NVME)
+		device pci 1d.0 on	# PCI Express Port 9 (X4 NVME)
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
@@ -339,6 +341,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_01"
 				device pci 00.0 on  end
 			end
+			register "PcieRpSlotImplemented[13]" = "1"
 		end # PCI Express Port 14 (x4)
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
index 7f75c78e26..10da16163d 100644
--- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
@@ -394,8 +394,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
index c1c44a69e9..61c7f0f242 100644
--- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
@@ -401,8 +401,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
index 67e62e7d08..dbf1851f32 100644
--- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
@@ -394,8 +394,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
index 2de90ec8e2..c73798a9a8 100644
--- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
@@ -309,8 +309,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index 7ead982c08..a5aa702890 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -333,8 +333,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
index d7b2298a06..3d5da00040 100644
--- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
@@ -328,8 +328,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index bacc6dceb7..760e35146e 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -377,8 +377,11 @@ chip soc/intel/cannonlake
 		device pci 1d.0 off end # PCI Express Port 9
 		device pci 1d.1 on
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
+			register "PcieRpSlotImplemented[9]" = "1"
 		end # PCI Express Port 10
-		device pci 1d.2 on  end # PCI Express Port 11
+		device pci 1d.2 on	# PCI Express Port 11
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1d.4 on
 			chip drivers/generic/bayhub
@@ -386,6 +389,7 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[12]" = "1"
 		end # PCI Express Port 13 (x4)
 		device pci 1e.0 off end # UART #0
 		device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index e79a8a5aeb..78f024cbf4 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -385,22 +385,29 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 off end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 (USB)
+		device pci 1c.0 on	# PCI Express Port 1 (USB)
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
 		device pci 1c.1 off end # PCI Express Port 2 (USB)
 		device pci 1c.2 off end # PCI Express Port 3 (USB)
 		device pci 1c.3 off end # PCI Express Port 4 (USB)
 		device pci 1c.4 off end # PCI Express Port 5 (USB)
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 on  end # PCI Express Port 8
+		device pci 1c.7 on	# PCI Express Port 8
+			register "PcieRpSlotImplemented[7]" = "1"
+		end
 		device pci 1d.0 on
 			chip drivers/generic/bayhub
 				register "power_saving" = "1"
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
+			register "PcieRpSlotImplemented[8]" = "1"
 		end # PCI Express Port 9
-		device pci 1d.1 on  end # PCI Express Port 10
+		device pci 1d.1 on	# PCI Express Port 10
+			register "PcieRpSlotImplemented[9]" = "1"
+		end
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1d.4 on
@@ -409,6 +416,7 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[12]" = "1"
 		end # PCI Express Port 13 (x4)
 		device pci 1e.0 off end # UART #0
 		device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index e5f867cbdc..f24e191256 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -124,12 +124,18 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 53c677b64e..6f282f05a4 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -140,12 +140,18 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
index 989b5cd4ea..a1455848e9 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
@@ -99,12 +99,18 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5 (Not available on PCH-H)
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
 		device pci 1d.4 off end # PCI Express Port 13
 		device pci 1d.5 off end # PCI Express Port 14
 		device pci 1d.6 off end # PCI Express Port 15
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
index a63d4c0364..a876994bfa 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
@@ -107,12 +107,18 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5 (Not available on PCH-H)
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1
-		device pci 1c.4 on  end # PCI Express Port 5
+		device pci 1c.0 on	# PCI Express Port 1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9 x4 SLOT 1
+		device pci 1d.0 on	# PCI Express Port 9 x4 SLOT 1
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
@@ -120,11 +126,21 @@ chip soc/intel/cannonlake
 		device pci 1d.5 off end # PCI Express Port 14
 		device pci 1d.6 off end # PCI Express Port 15
 		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1b.0 on  end # PCI Express Port 17
-		device pci 1b.1 on  end # PCI Express Port 18
-		device pci 1b.2 on  end # PCI Express Port 19
-		device pci 1b.3 on  end # PCI Express Port 20
-		device pci 1b.4 on  end # PCI Express Port 21 X4 SLOT 2
+		device pci 1b.0 on	# PCI Express Port 17
+			register "PcieRpSlotImplemented[16]" = "1"
+		end
+		device pci 1b.1 on	# PCI Express Port 18
+			register "PcieRpSlotImplemented[17]" = "1"
+		end
+		device pci 1b.2 on	# PCI Express Port 19
+			register "PcieRpSlotImplemented[18]" = "1"
+		end
+		device pci 1b.3 on	# PCI Express Port 20
+			register "PcieRpSlotImplemented[19]" = "1"
+		end
+		device pci 1b.4 on	# PCI Express Port 21 X4 SLOT 2
+			register "PcieRpSlotImplemented[20]" = "1"
+		end
 		device pci 1e.1 off end # UART #1
 		device pci 1f.6 on  end # GbE
 	end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
index c5c291df9f..f48c9b49a8 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
@@ -84,12 +84,18 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
index a8f6766340..28b33cf5f4 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
@@ -94,12 +94,18 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
index 1e388240a6..89d60366a7 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
@@ -78,12 +78,18 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb
index a89ba1b755..cae3d4c070 100644
--- a/src/mainboard/prodrive/hermes/devicetree.cb
+++ b/src/mainboard/prodrive/hermes/devicetree.cb
@@ -35,6 +35,7 @@ chip soc/intel/cannonlake
 			device pci 00.0 on      # Aspeed PCI Bridge
 				device pci 00.0 on end  # Aspeed 2500 VGA
 			end
+			register "PcieRpSlotImplemented[14]" = "1"
 		end
 		device pci 1f.0 on	# LPC Interface
 			chip drivers/pc80/tpm
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
index 8098c56981..7759b57f27 100644
--- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
@@ -183,20 +183,35 @@ chip soc/intel/cannonlake
 		end
 		device pci 1b.4 on	# PCIe root port 21 (Slot 1)
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[20]" = "1"
 		end
 		device pci 1c.0 on	# PCIe root port 1 (Slot 3)
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[0]" = "1"
+		end
+		device pci 1c.4 on	# PCIe root port 5 (PHY 3)
+			register "PcieRpSlotImplemented[4]" = "1"
+		end
+		device pci 1c.5 on	# PCIe root port 6 (PHY 4)
+			register "PcieRpSlotImplemented[5]" = "1"
+		end
+		device pci 1c.6 on	# PCIe root port 7 (PHY 2)
+			register "PcieRpSlotImplemented[6]" = "1"
+		end
+		device pci 1c.7 on	# PCIe root port 8 (PHY 1)
+			register "PcieRpSlotImplemented[7]" = "1"
 		end
-		device pci 1c.4 on end # PCIe root port 5 (PHY 3)
-		device pci 1c.5 on end # PCIe root port 6 (PHY 4)
-		device pci 1c.6 on end # PCIe root port 7 (PHY 2)
-		device pci 1c.7 on end # PCIe root port 8 (PHY 1)
 
 		device pci 1d.0 on	# PCIe root port 9 (M2 M)
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
+		device pci 1d.5 on	# PCIe root port 14 (PHY 0)
+			register "PcieRpSlotImplemented[13]" = "1"
+		end
+		device pci 1d.6 on	# PCIe root port 15 (BMC)
+			register "PcieRpSlotImplemented[14]" = "1"
 		end
-		device pci 1d.5 on end # PCIe root port 14 (PHY 0)
-		device pci 1d.6 on end # PCIe root port 15 (BMC)
 
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 on  end # UART #1
diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb
index c122bb8982..fc3f418c6f 100644
--- a/src/mainboard/purism/librem_whl/devicetree.cb
+++ b/src/mainboard/purism/librem_whl/devicetree.cb
@@ -293,12 +293,18 @@ chip soc/intel/cannonlake
 		device pci 1c.4 off end # PCI Express Port 5
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 on  end # PCI Express Port 8  (WLAN)
+		device pci 1c.7 on	# PCI Express Port 8  (WLAN)
+			register "PcieRpSlotImplemented[7]" = "1"
+		end
 		device pci 1d.0 off end # PCI Express Port 9
-		device pci 1d.1 on  end # PCI Express Port 10 (LAN)
+		device pci 1d.1 on	# PCI Express Port 10 (LAN)
+			register "PcieRpSlotImplemented[9]" = "1"
+		end
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 on  end # PCI Express Port 13 (NVMe)
+		device pci 1d.4 on	# PCI Express Port 13 (NVMe)
+			register "PcieRpSlotImplemented[12]" = "1"
+		end
 		device pci 1d.5 off end # PCI Express Port 14
 		device pci 1d.6 off end # PCI Express Port 15
 		device pci 1d.7 off end # PCI Express Port 16
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb
index 9cdeeabc28..659ca89475 100644
--- a/src/mainboard/system76/lemp9/devicetree.cb
+++ b/src/mainboard/system76/lemp9/devicetree.cb
@@ -215,14 +215,22 @@ chip soc/intel/cannonlake
 		device pci 1c.2 off end # PCI Express Port 3
 		device pci 1c.3 off end # PCI Express Port 4
 		device pci 1c.4 off end # PCI Express Port 5
-		device pci 1c.5 on  end # PCI Express Port 6
+		device pci 1c.5 on	# PCI Express Port 6
+			register "PcieRpSlotImplemented[5]" = "1"
+		end
 		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 on  end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1c.7 on	# PCI Express Port 8
+			register "PcieRpSlotImplemented[7]" = "1"
+		end
+		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 on  end # PCI Express Port 13
+		device pci 1d.4 on	# PCI Express Port 13
+			register "PcieRpSlotImplemented[12]" = "1"
+		end
 		device pci 1d.5 off end # PCI Express Port 14
 		device pci 1d.6 off end # PCI Express Port 15
 		device pci 1d.7 off end # PCI Express Port 16
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2923efc555..e5ceac9312 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -185,6 +185,8 @@ struct soc_intel_cannonlake_config {
 	uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
 	/* PCIe LTR(Latency Tolerance Reporting) mechanism */
 	uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
+	/* Implemented as slot or built-in? */
+	uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
 	/* Enable/Disable HotPlug support for Root Port */
 	uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
 
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 0779ce2e44..51ed2a8b57 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -479,6 +479,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
 	       sizeof(config->PcieRpLtrEnable));
+	memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented,
+	       sizeof(config->PcieRpSlotImplemented));
 	memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
 	       sizeof(params->PcieRpHotPlug));