diff options
| author | Chia-Ling Hou <chia-ling.hou@intel.com> | 2023-06-07 16:53:00 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-23 15:22:45 +0000 |
| commit | b5a032859aec1449b46eed60a6c6aeb9147e45a7 (patch) | |
| tree | 1fe057507bc9193485619a060990ebddc5ba8f9c /src/mainboard/google/dedede/variants/dibbi | |
| parent | 3dedfcbbd472fe569e06e8454db77fa8915a0a2f (diff) | |
soc/intel/jasperlake: Add per-SKU power limits
Add JSL SKUs ID and add PLx from JSL PDG in project devicetree.
BUG=b:281479111
TEST=emerge-dedede coreboot and read correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Super Ni <super.ni@intel.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/dibbi')
| -rw-r--r-- | src/mainboard/google/dedede/variants/dibbi/overridetree.cb | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb index e3df1f2d17..6cda5862af 100644 --- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb @@ -25,6 +25,19 @@ chip soc/intel/jasperlake }, }" + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + # Enable Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 register "PcieRpEnable[2]" = "1" |