soc/intel/jasperlake: Add per-SKU power limits

Add JSL SKUs ID and add PLx from JSL PDG in project devicetree.

BUG=b:281479111
TEST=emerge-dedede coreboot and read correct value on dibbi

Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Super Ni <super.ni@intel.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>

14 files changed, 112 insertions, 37 deletions

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 30a971c326..9f747d9b97 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -166,11 +166,37 @@ chip soc/intel/jasperlake
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
-	register "power_limits_config" = "{
+	# Power limit config
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
 		.tdp_pl1_override = 6,
 		.tdp_pl2_override = 20,
 	}"
 
+	register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+	}"
+
+	register "power_limits_config[JSL_N4505_10W_CORE]" = "{
+		.tdp_pl1_override = 10,
+		.tdp_pl2_override = 25,
+	}"
+
+	register "power_limits_config[JSL_N5105_10W_CORE]" = "{
+		.tdp_pl1_override = 10,
+		.tdp_pl2_override = 25,
+	}"
+
+	register "power_limits_config[JSL_N6005_10W_CORE]" = "{
+		.tdp_pl1_override = 10,
+		.tdp_pl2_override = 25,
+	}"
+
 	register "tcc_offset" = "10"     # TCC of 90C
 
 	# VR config settings
diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
index 518b962fd0..a507dd1461 100644
--- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
@@ -59,11 +59,6 @@ chip soc/intel/jasperlake
 		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 	}"
 
-	register "power_limits_config" = "{
-			.tdp_pl1_override = 6,
-			.tdp_pl2_override = 20,
-	}"
-
 	register "tcc_offset" = "10"    # TCC of 95C
 
 	# Enable Acoustic noise mitigation and set slew rate to 1/8
diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
index e3df1f2d17..6cda5862af 100644
--- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
@@ -25,6 +25,19 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	# Power limit config
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+		.tdp_pl4 = 60,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+		.tdp_pl4 = 60,
+	}"
+
 	# Enable Root Port 3 (index 2) for LAN
 	# External PCIe port 7 is mapped to PCIe Root Port 3
 	register "PcieRpEnable[2]" = "1"
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index 2eb9d814b9..e90d97ed71 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -64,11 +64,6 @@ chip soc/intel/jasperlake
 		},
 	}"
 
-	register "power_limits_config" = "{
-		.tdp_pl1_override = 6,
-		.tdp_pl2_override = 20,
-	}"
-
 	register "tcc_offset" = "20"	# TCC of 85C
 
 	# Enable Acoustic noise mitigation and set slew rate to 1/4
diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
index cffcc9a837..704e4587b8 100644
--- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
@@ -35,11 +35,6 @@ chip soc/intel/jasperlake
 		},
 	}"
 
-	register "power_limits_config" = "{
-		.tdp_pl1_override = 6,
-		.tdp_pl2_override = 20,
-	}"
-
 	register "tcc_offset" = "20"	# TCC of 85C
 
 	register "SerialIoGSpiMode[PchSerialIoIndexGSPI0]" = "PchSerialIoDisabled" # Disable GSPI0
diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
index 1ce3a8fe67..5e39c884e4 100644
--- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
@@ -65,11 +65,6 @@ chip soc/intel/jasperlake
 		},
 	}"
 
-	register "power_limits_config" = "{
-		.tdp_pl1_override = 6,
-		.tdp_pl2_override = 20,
-	}"
-
 	register "tcc_offset" = "20"	# TCC of 85C
 
 	device domain 0 on
diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
index fe3c407d0e..7b849b2509 100644
--- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
@@ -56,7 +56,18 @@ chip soc/intel/jasperlake
 		},
 	}"
 
-	register "power_limits_config" = "{
+	# Power limit config
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+		.tdp_pl1_override = 7,
+		.tdp_pl2_override = 12,
+	}"
+
+	register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+		.tdp_pl1_override = 7,
+		.tdp_pl2_override = 12,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
 		.tdp_pl1_override = 7,
 		.tdp_pl2_override = 12,
 	}"
diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb
index b67bd97da7..c56840823d 100644
--- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb
@@ -72,7 +72,18 @@ chip soc/intel/jasperlake
 		},
 	}"
 
-	register "power_limits_config" = "{
+	# Power limit config
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 15,
+	}"
+
+	register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 15,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
 		.tdp_pl1_override = 6,
 		.tdp_pl2_override = 15,
 	}"
diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
index 2260652d22..437c60a5cd 100644
--- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
@@ -54,11 +54,6 @@ chip soc/intel/jasperlake
 		},
 	}"
 
-	register "power_limits_config" = "{
-			.tdp_pl1_override = 6,
-			.tdp_pl2_override = 20,
-	}"
-
 	register "tcc_offset" = "10"    # TCC of 95C
 
 	# Enable Acoustic noise mitigation and set slew rate to 1/8
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index bb5bf24419..cde69ed9aa 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -95,7 +95,18 @@ chip soc/intel/jasperlake
 		},
 	}"
 
-	register "power_limits_config" = "{
+	# Power limit config
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+		.tdp_pl1_override = 7,
+		.tdp_pl2_override = 12,
+	}"
+
+	register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+		.tdp_pl1_override = 7,
+		.tdp_pl2_override = 12,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
 		.tdp_pl1_override = 7,
 		.tdp_pl2_override = 12,
 	}"
diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
index 75618f4505..e01dee93e8 100644
--- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
@@ -64,7 +64,18 @@ chip soc/intel/jasperlake
 		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 	}"
 
-	register "power_limits_config" = "{
+	# Power limit config
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 12,
+	}"
+
+	register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 12,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
 		.tdp_pl1_override = 6,
 		.tdp_pl2_override = 12,
 	}"
diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
index 43a68dbb16..5e4de2ac2a 100644
--- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
@@ -87,11 +87,6 @@ chip soc/intel/jasperlake
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # Camera
 
-	register "power_limits_config" = "{
-			.tdp_pl1_override = 6,
-			.tdp_pl2_override = 20,
-	}"
-
 	register "tcc_offset" = "10"    # TCC of 95C
 
 	register "xhci_lfps_sampling_offtime_ms" = "0"
diff --git a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
index b454e3d2cd..0935457092 100644
--- a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
@@ -40,7 +40,18 @@ chip soc/intel/jasperlake
 
 	register "disable_external_bypass_vr" = "1"    # Does not support external vnn power rail
 
-	register "power_limits_config" = "{
+	# Power limit config
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+		.tdp_pl1_override = 7,
+		.tdp_pl2_override = 25,
+	}"
+
+	register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+		.tdp_pl1_override = 7,
+		.tdp_pl2_override = 25,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
 		.tdp_pl1_override = 7,
 		.tdp_pl2_override = 25,
 	}"
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 3b1f007f16..1aa2e711a9 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -84,7 +84,18 @@ chip soc/intel/jasperlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	register "power_limits_config" = "{
+	# Power limit config
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+		.tdp_pl1_override = 7,
+		.tdp_pl2_override = 20,
+	}"
+
+	register "power_limits_config[JSL_N6000_6W_CORE]" = "{
+		.tdp_pl1_override = 7,
+		.tdp_pl2_override = 20,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
 		.tdp_pl1_override = 7,
 		.tdp_pl2_override = 20,
 	}"