From b5a032859aec1449b46eed60a6c6aeb9147e45a7 Mon Sep 17 00:00:00 2001 From: Chia-Ling Hou Date: Wed, 7 Jun 2023 16:53:00 +0800 Subject: soc/intel/jasperlake: Add per-SKU power limits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add JSL SKUs ID and add PLx from JSL PDG in project devicetree. BUG=b:281479111 TEST=emerge-dedede coreboot and read correct value on dibbi Signed-off-by: Chia-Ling Hou Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679 Reviewed-by: Super Ni Reviewed-by: Super Ni Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar --- src/mainboard/google/dedede/variants/dibbi/overridetree.cb | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/mainboard/google/dedede/variants/dibbi') diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb index e3df1f2d17..6cda5862af 100644 --- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb @@ -25,6 +25,19 @@ chip soc/intel/jasperlake }, }" + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + # Enable Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 register "PcieRpEnable[2]" = "1" -- cgit v1.2.3