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authorNico Huber <nico.huber@secunet.com>2019-10-02 16:02:06 +0200
committerNico Huber <nico.h@gmx.de>2020-08-23 09:57:02 +0000
commit119ace0908b66b718c4b581423309648b10e4bf7 (patch)
treeb9ed4510a9081065c35af99a06446a74b3db82c1 /src/mainboard/google/cyan/spd/spd.c
parent2b9035ed6e51fe835b85dd626e655e1d3901e7ea (diff)
soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/google/cyan/spd/spd.c')
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