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authorEric Lai <eric_lai@quanta.corp-partner.google.com>2022-03-14 15:08:27 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-03-17 16:00:38 +0000
commitaf92d07503600695df44f59aa7c8f9c19b4e462d (patch)
treea125ec51ee5f46c1ec7de8f9f3478ffddfc3c82c /src/mainboard/google/brya/variants/baseboard/nissa
parent275478711009ffed866fbc0f30ff2130447913f4 (diff)
mb/google/brya: Remove mainboard.asl
Use C code to generate MS0X entry and provide variant hook. BUG=b:207144468 TEST=check SSDT table has the same entry. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x148) } Else { \_SB.PCI0.STXS (0x148) } } } Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard/nissa')
-rw-r--r--src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
index 068aaa4835..51e4b207f9 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
@@ -16,5 +16,7 @@
#define GPIO_EC_IN_RW GPP_F18
/* GPIO IRQ for tight timestamps */
#define EC_SYNC_IRQ GPD2_IRQ
+/* GPP_H18 used as dummy here since nissa not selected HAVE_SLP_S0_GATE */
+#define GPIO_SLP_S0_GATE GPP_H18
#endif /* __BASEBOARD_GPIO_H__ */