mb/google/brya: Remove mainboard.asl

Use C code to generate MS0X entry and provide variant hook.

BUG=b:207144468
TEST=check SSDT table has the same entry.
    Scope (\_SB)
    {
        Method (MS0X, 1, Serialized)
        {
            If ((Arg0 == One))
            {
                \_SB.PCI0.CTXS (0x148)
            }
            Else
            {
                \_SB.PCI0.STXS (0x148)
            }
        }
    }

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

2 files changed, 9 insertions, 0 deletions

diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
index 7c1ce21f6c..9accc08f9d 100644
--- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
@@ -25,6 +25,13 @@ bool variant_is_half_populated(void);
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config);
 void variant_fill_ssdt(const struct device *dev);
 
+enum s0ix_entry {
+	S0IX_EXIT,
+	S0IX_ENTRY,
+};
+
+void variant_generate_s0ix_hook(enum s0ix_entry);
+
 /* Modify devictree settings during ramstage */
 void variant_devtree_update(void);
 
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
index 068aaa4835..51e4b207f9 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
@@ -16,5 +16,7 @@
 #define GPIO_EC_IN_RW		GPP_F18
 /* GPIO IRQ for tight timestamps */
 #define EC_SYNC_IRQ		GPD2_IRQ
+/* GPP_H18 used as dummy here since nissa not selected HAVE_SLP_S0_GATE */
+#define GPIO_SLP_S0_GATE	GPP_H18
 
 #endif /* __BASEBOARD_GPIO_H__ */