From af92d07503600695df44f59aa7c8f9c19b4e462d Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 14 Mar 2022 15:08:27 +0800 Subject: mb/google/brya: Remove mainboard.asl Use C code to generate MS0X entry and provide variant hook. BUG=b:207144468 TEST=check SSDT table has the same entry. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x148) } Else { \_SB.PCI0.STXS (0x148) } } } Signed-off-by: Eric Lai Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779 Tested-by: build bot (Jenkins) Reviewed-by: Kangheui Won Reviewed-by: Tim Wawrzynczak --- .../google/brya/variants/baseboard/nissa/include/baseboard/gpio.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google/brya/variants/baseboard/nissa') diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h index 068aaa4835..51e4b207f9 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h @@ -16,5 +16,7 @@ #define GPIO_EC_IN_RW GPP_F18 /* GPIO IRQ for tight timestamps */ #define EC_SYNC_IRQ GPD2_IRQ +/* GPP_H18 used as dummy here since nissa not selected HAVE_SLP_S0_GATE */ +#define GPIO_SLP_S0_GATE GPP_H18 #endif /* __BASEBOARD_GPIO_H__ */ -- cgit v1.2.3