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authorT Michael Turney <quic_mturney@quicinc.com>2022-01-20 11:55:40 -0800
committerShelley Chen <shchen@google.com>2022-02-15 01:11:26 +0000
commitd43e688ed2fe94ed429658ced02764527af8cb0f (patch)
tree0aa30c2b7c70530f2ce5e9a56b412d08719f40ba /src/drivers/spi/Kconfig
parent02b2afa8e9dacf0dfdd730902ead02580596df65 (diff)
drivers: spi_flash: Addressing mode change for SPI NOR
As 4-byte addressing mode is not support in coreboot, change the addressing mode of SPI NOR from 4-bytes to 3-bytes. BUG=b:215605946 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/drivers/spi/Kconfig')
-rw-r--r--src/drivers/spi/Kconfig11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig
index 13a73b8df2..b7650dd31d 100644
--- a/src/drivers/spi/Kconfig
+++ b/src/drivers/spi/Kconfig
@@ -162,6 +162,17 @@ config SPI_FLASH_HAS_VOLATILE_GROUP
Allows chipset to group write/erase operations under a single volatile
group.
+config SPI_FLASH_EXIT_4_BYTE_ADDR_MODE
+ bool
+ default n
+ help
+ This will send an Exit 4-Byte Address Mode (E9h) command before the first
+ access to the SPI flash. On some platforms with SPI flashes larger than 32MB,
+ the SPI flash may power up in 4-byte addressing mode and this command needs
+ to be sent before coreboot's 3-byte address commands can be interpreted correctly.
+ On flashes that don't support 4-byte addressing mode or where it is already
+ disabled, this command should be a no-op.
+
endif # SPI_FLASH
config HAVE_EM100PRO_SPI_CONSOLE_SUPPORT