From d43e688ed2fe94ed429658ced02764527af8cb0f Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Thu, 20 Jan 2022 11:55:40 -0800 Subject: drivers: spi_flash: Addressing mode change for SPI NOR As 4-byte addressing mode is not support in coreboot, change the addressing mode of SPI NOR from 4-bytes to 3-bytes. BUG=b:215605946 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Veerabhadrarao Badiganti Signed-off-by: Shaik Sajida Bhanu Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50586 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Shelley Chen --- src/drivers/spi/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/drivers/spi/Kconfig') diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 13a73b8df2..b7650dd31d 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -162,6 +162,17 @@ config SPI_FLASH_HAS_VOLATILE_GROUP Allows chipset to group write/erase operations under a single volatile group. +config SPI_FLASH_EXIT_4_BYTE_ADDR_MODE + bool + default n + help + This will send an Exit 4-Byte Address Mode (E9h) command before the first + access to the SPI flash. On some platforms with SPI flashes larger than 32MB, + the SPI flash may power up in 4-byte addressing mode and this command needs + to be sent before coreboot's 3-byte address commands can be interpreted correctly. + On flashes that don't support 4-byte addressing mode or where it is already + disabled, this command should be a no-op. + endif # SPI_FLASH config HAVE_EM100PRO_SPI_CONSOLE_SUPPORT -- cgit v1.2.3