diff options
| -rw-r--r-- | src/drivers/spi/Kconfig | 11 | ||||
| -rw-r--r-- | src/drivers/spi/spi_flash.c | 4 | ||||
| -rw-r--r-- | src/drivers/spi/spi_flash_internal.h | 2 |
3 files changed, 17 insertions, 0 deletions
diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 13a73b8df2..b7650dd31d 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -162,6 +162,17 @@ config SPI_FLASH_HAS_VOLATILE_GROUP Allows chipset to group write/erase operations under a single volatile group. +config SPI_FLASH_EXIT_4_BYTE_ADDR_MODE + bool + default n + help + This will send an Exit 4-Byte Address Mode (E9h) command before the first + access to the SPI flash. On some platforms with SPI flashes larger than 32MB, + the SPI flash may power up in 4-byte addressing mode and this command needs + to be sent before coreboot's 3-byte address commands can be interpreted correctly. + On flashes that don't support 4-byte addressing mode or where it is already + disabled, this command should be a no-op. + endif # SPI_FLASH config HAVE_EM100PRO_SPI_CONSOLE_SUPPORT diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index f3cecd5fc6..ded88eda09 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -515,6 +515,10 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash) " CONFIG_ROM_SIZE 0x%x!!\n", flash->size, CONFIG_ROM_SIZE); } + + if (CONFIG(SPI_FLASH_EXIT_4_BYTE_ADDR_MODE) && ENV_INITIAL_STAGE) + spi_flash_cmd(&flash->spi, CMD_EXIT_4BYTE_ADDR_MODE, NULL, 0); + return 0; } diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 4a7beeab3e..e3883112ee 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -22,6 +22,8 @@ #define CMD_BLOCK_ERASE 0xD8 +#define CMD_EXIT_4BYTE_ADDR_MODE 0xe9 + /* Common status */ #define STATUS_WIP 0x01 |