diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-10-31 14:02:13 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-08 14:38:28 +0000 |
| commit | ad65e8c041b1d375936267bacc578254407e095f (patch) | |
| tree | f2a0a29e7b3a354bba1dba5a6003e67d6621b30f /src/cpu/intel/slot_1/l2_cache.c | |
| parent | df1aea1f2a13ea3fbee6ea2c9d4137ba3ee762b8 (diff) | |
cpu: Include <cpu/cpu.h> instead of <arch/cpu.h>
Also sort includes.
Change-Id: Ia4a3807e45777e2a596878fe09e3c80b1fd2704d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/cpu/intel/slot_1/l2_cache.c')
| -rw-r--r-- | src/cpu/intel/slot_1/l2_cache.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index fa433660b6..e4f8e9532b 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -23,12 +23,12 @@ * Covington-core Celerons do not have L2 cache. */ -#include <stdint.h> -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/l2_cache.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> +#include <stdint.h> /* Latency Tables */ struct latency_entry { |