diff options
Diffstat (limited to 'src/cpu/intel/slot_1/l2_cache.c')
| -rw-r--r-- | src/cpu/intel/slot_1/l2_cache.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index fa433660b6..e4f8e9532b 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -23,12 +23,12 @@ * Covington-core Celerons do not have L2 cache. */ -#include <stdint.h> -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/l2_cache.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> +#include <stdint.h> /* Latency Tables */ struct latency_entry { |