diff options
| author | Xiang Wang <wxjstz@126.com> | 2018-08-29 17:21:19 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-05 10:04:57 +0000 |
| commit | 21ed107958b3a2525f01875162d5a83a7900d4b4 (patch) | |
| tree | a598872bb0270788b51f748f7f5bc3e3e8abf282 /src/arch/riscv/Makefile.inc | |
| parent | 384e9aed8c477922c960e2cbd429bd3a15b371de (diff) | |
riscv: add entry assembly file for RAMSTAGE
RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling
needs to be moved to ddr memory. So add a assembly file to do this.
Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/riscv/Makefile.inc')
| -rw-r--r-- | src/arch/riscv/Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index c4859408f3..ae327f2f16 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -97,6 +97,10 @@ endif #CONFIG_ARCH_ROMSTAGE_RISCV ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = +ramstage-y += ramstage.S +ramstage-y += mcall.c +ramstage-y += trap_util.S +ramstage-y += trap_handler.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c |