diff options
| author | Xiang Wang <wxjstz@126.com> | 2018-08-29 17:21:19 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-05 10:04:57 +0000 |
| commit | 21ed107958b3a2525f01875162d5a83a7900d4b4 (patch) | |
| tree | a598872bb0270788b51f748f7f5bc3e3e8abf282 /src/arch | |
| parent | 384e9aed8c477922c960e2cbd429bd3a15b371de (diff) | |
riscv: add entry assembly file for RAMSTAGE
RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling
needs to be moved to ddr memory. So add a assembly file to do this.
Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/riscv/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/arch/riscv/include/arch/header.ld | 4 | ||||
| -rw-r--r-- | src/arch/riscv/ramstage.S | 53 |
3 files changed, 60 insertions, 1 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index c4859408f3..ae327f2f16 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -97,6 +97,10 @@ endif #CONFIG_ARCH_ROMSTAGE_RISCV ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = +ramstage-y += ramstage.S +ramstage-y += mcall.c +ramstage-y += trap_util.S +ramstage-y += trap_handler.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld index 3e078d8b90..4b1104778c 100644 --- a/src/arch/riscv/include/arch/header.ld +++ b/src/arch/riscv/include/arch/header.ld @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <rules.h> + /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_ARCH(riscv) @@ -21,7 +23,7 @@ PHDRS to_load PT_LOAD; } -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBLOCK || ENV_RAMSTAGE ENTRY(_start) #else ENTRY(stage_entry) diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S new file mode 100644 index 0000000000..906215ca01 --- /dev/null +++ b/src/arch/riscv/ramstage.S @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/encoding.h> +#include <mcall.h> + +.section ".text._start", "ax", %progbits +.globl _start +_start: + # initialize stack point for each hart + # and the stack must be page-aligned. + # 0xDEADBEEF used to check stack overflow + csrr a0, mhartid + la t0, _stack + slli t1, a0, RISCV_PGSHIFT + add t0, t0, t1 + li t1, 0xDEADBEEF + sd t1, 0(t0) + li t1, RISCV_PGSIZE - HLS_SIZE + add sp, t0, t1 + + # initialize hart-local storage + csrr a0, mhartid + call hls_init + + # initialize entry of interrupt/exception + la t0, trap_entry + csrw mtvec, t0 + + # clear any pending interrupts + csrwi mip, 0 + + call exit_car + # set up the mstatus register for VM + call mstatus_init + tail main + + # These codes need to be implemented on a specific SoC + .weak exit_car +exit_car: + ret |