From 21ed107958b3a2525f01875162d5a83a7900d4b4 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Wed, 29 Aug 2018 17:21:19 +0800 Subject: riscv: add entry assembly file for RAMSTAGE RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling needs to be moved to ddr memory. So add a assembly file to do this. Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/28384 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/riscv/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/arch/riscv/Makefile.inc') diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index c4859408f3..ae327f2f16 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -97,6 +97,10 @@ endif #CONFIG_ARCH_ROMSTAGE_RISCV ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = +ramstage-y += ramstage.S +ramstage-y += mcall.c +ramstage-y += trap_util.S +ramstage-y += trap_handler.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c -- cgit v1.2.3