intel/fsp: Update cannonlake FSP header

Update cannonlake FSP header file to revision 7.x.15.46. The following
item had been updated:
1. Remove/Hide restricted structure.
2. Add EBR as extention of RMT features.
3. Add cpu wakeup timer UPD.
4. Remove XHCI access lock UPD.

TEST=NONE

Change-Id: I065edbeffdaf555ea7d54ec3fdce56d026789c52
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2 files changed, 23 insertions, 1627 deletions

diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
index fe9933f7fb..dded50d383 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
@@ -2248,9 +2248,15 @@ typedef struct {
 **/
   UINT8                       RMTLoopCount;
 
-/** Offset 0x0511
+/** Offset 0x0511 - BER Support
+  Enable/Disable the Rank Margin Tool interpolation/extrapolation.
+  0:Disable, 1:Enable
+**/
+  UINT8                       EnBER;
+
+/** Offset 0x0512
 **/
-  UINT8                       ReservedFspmUpd[15];
+  UINT8                       ReservedFspmUpd[14];
 } FSP_M_CONFIG;
 
 /** Fsp M Test Configuration
@@ -2619,709 +2625,6 @@ typedef struct {
   UINT8                       ReservedFspmTestUpd[11];
 } FSP_M_TEST_CONFIG;
 
-/** Fsp M Restricted Configuration
-**/
-typedef struct {
-
-/** Offset 0x05B0
-**/
-  UINT32                      Signature;
-
-/** Offset 0x05B4 - Sa Sv Remap Base Override
-  SvRemapBaseOverride
-**/
-  UINT16                      SaSvRemapBaseOverride;
-
-/** Offset 0x05B6 - Sa System Agent ClockGating Enable
-  SystemAgentClockGatingEnable
-**/
-  UINT8                       SaSystemAgentClockGatingEnable;
-
-/** Offset 0x05B7 - Sa Pcie Pll Shutdown Enable
-  PciePllShutdownEnable
-**/
-  UINT8                       SaPciePllShutdownEnable;
-
-/** Offset 0x05B8 - Sa SV_DMI_GEN1_halt
-  SV_DMI_GEN1_halt
-**/
-  UINT8                       SaSV_DMI_GEN1_halt;
-
-/** Offset 0x05B9 - Sa SV_nFTS_DMI_auto
-  SV_nFTS_DMI_auto
-**/
-  UINT8                       SaSV_nFTS_DMI_auto;
-
-/** Offset 0x05BA - Sa Sv DMI_nFTS
-  SvDMI_nFTS
-**/
-  UINT8                       SaSvDMI_nFTS;
-
-/** Offset 0x05BB - Sa nFTS_auto
-  nFTS_auto
-**/
-  UINT8                       SanFTS_auto;
-
-/** Offset 0x05BC - Sa SvPEG_nFTS
-  SvPEG_nFTS
-**/
-  UINT8                       SaSvPEG_nFTS[4];
-
-/** Offset 0x05C0 - Sa SvPEG_gen3_ccFTS
-  SvPEG_gen3_ccFTS
-**/
-  UINT8                       SaSvPEG_gen3_ccFTS[4];
-
-/** Offset 0x05C4 - Sa SvPEG_gen3_nccFTS
-  SvPEG_gen3_nccFTS
-**/
-  UINT8                       SaSvPEG_gen3_nccFTS[4];
-
-/** Offset 0x05C8 - Sa nFTS_gen3_auto
-  nFTS_gen3_auto
-**/
-  UINT8                       SanFTS_gen3_auto;
-
-/** Offset 0x05C9 - Sa SVIAER
-  SVIAER
-**/
-  UINT8                       SaSVIAER;
-
-/** Offset 0x05CA - Sa Sv Scrambler Dmi
-  SvScramblerDmi
-**/
-  UINT8                       SaSvScramblerDmi;
-
-/** Offset 0x05CB
-**/
-  UINT8                       UnusedUpdSpace9[1];
-
-/** Offset 0x05CC - Sa Sv Scrambler Peg
-  SvScramblerPeg
-**/
-  UINT8                       SaSvScramblerPeg[4];
-
-/** Offset 0x05D0 - Sa Sv Dmi Serr
-  SvDmiSerr
-**/
-  UINT8                       SaSvDmiSerr;
-
-/** Offset 0x05D1
-**/
-  UINT8                       UnusedUpdSpace10[3];
-
-/** Offset 0x05D4 - Sa Sv Scrambler Peg Gen3
-  SvScramblerPegGen3
-**/
-  UINT8                       SaSvScramblerPegGen3[4];
-
-/** Offset 0x05D8 - Sa Sv Peg Serr
-  SvPegSerr
-**/
-  UINT8                       SaSvPegSerr[4];
-
-/** Offset 0x05DC - Sa Test Tx ClkGating
-  TestTxClkGating
-**/
-  UINT8                       SaTestTxClkGating;
-
-/** Offset 0x05DD - Sa Test Rx ClkGating
-  TestRxClkGating
-**/
-  UINT8                       SaTestRxClkGating;
-
-/** Offset 0x05DE - Sa Test Low Pwr Mode
-  TestLowPwrMode
-**/
-  UINT8                       SaTestLowPwrMode;
-
-/** Offset 0x05DF - Sa Sr Mode
-  SrMode
-**/
-  UINT8                       SaSrMode;
-
-/** Offset 0x05E0 - Sa Sr Seq
-  SrSeq
-**/
-  UINT8                       SaSrSeq;
-
-/** Offset 0x05E1 - Sa Burst Spacing
-  BurstSpacing
-**/
-  UINT8                       SaBurstSpacing;
-
-/** Offset 0x05E2 - SvPolicyEnable
-  Enable: SV policy is enabled, Disable(Default): SV policy is disabled
-  $EN_DIS
-**/
-  UINT8                       SaRestrictedSvPolicyEnable;
-
-/** Offset 0x05E3 - Cpu Sv Boot Mode
-  0: Auto (Default), 1: Commercial boot mode, 2: SV boot mode, 3: SV boot JTAG mode
-  with SB loop, 4: SV boot JTAG mode without SB loop
-  0: Auto , 1: Commercial boot mode, 2: SV boot mode, 3: SV boot JTAG mode with SB
-  loop, 4: SV boot JTAG mode without SB loop
-**/
-  UINT8                       SaCpuSvBootMode;
-
-/** Offset 0x05E4 - CpuSvBootMode
-  Enable: FlexCon is enabled, Disble(Default): FlexCon is disabled
-  $EN_DIS
-**/
-  UINT8                       XmlCliEnable;
-
-/** Offset 0x05E5 - LoadValidationFv
-  Enable: Enable loading of ValidationFV, Disable(Default)
-  $EN_DIS
-**/
-  UINT8                       LoadValidationFv;
-
-/** Offset 0x05E6 - SvReserveMemoryBelowPrmrr
-  Enable: Enable reserve SV memory below PMRR, Disable(Default)
-  $EN_DIS
-**/
-  UINT8                       SvReserveMemoryBelowPrmrr;
-
-/** Offset 0x05E7 - Sa Test Sample Part Status Override
-  0-Passthrough,  1-Production part,  2-Preproduction part
-**/
-  UINT8                       SaTestSamplePartStatusOverride;
-
-/** Offset 0x05E8 - Sa Test Grunit ClockGating
-  Enable Sa Test Grunit ClockGating
-  $EN_DIS
-**/
-  UINT8                       SaTestGrunitClockGating;
-
-/** Offset 0x05E9 - Sa Test Dmi Cap Reg Lock
-  DMI Capability Register Lock
-**/
-  UINT8                       SaTestDmiCapRegLock;
-
-/** Offset 0x05EA - Sa Test Dmi Max Payload Size
-  DMI Max Payload Size
-**/
-  UINT8                       SaTestDmiMaxPayloadSize;
-
-/** Offset 0x05EB - Sa Pcie VcLim Lock
-  Lock bit
-**/
-  UINT8                       SaPcieVcLimLock;
-
-/** Offset 0x05EC - Sa Pcie VCm Cmp Lim
-  VCm Completions override
-**/
-  UINT8                       SaPcieVCmCmpLim;
-
-/** Offset 0x05ED - Sa Pcie VCm PLim
-  posted VCm Requests override
-**/
-  UINT8                       SaPcieVCmPLim;
-
-/** Offset 0x05EE - Sa Pcie VCm NpLim
-  non-posted VCm Requests override
-**/
-  UINT8                       SaPcieVCmNpLim;
-
-/** Offset 0x05EF - Sa Laguna Credit WA
-  Laguna Credit WA
-**/
-  UINT8                       SaLagunaCreditWA;
-
-/** Offset 0x05F0 - Sa Sv Dmi Compliance Deemphasis
-  SvDmiComplianceDeemphasis
-**/
-  UINT8                       SaSvDmiComplianceDeemphasis;
-
-/** Offset 0x05F1 - Prefetch NonPrefetch Ratio
-  0: All prefetch, 1: Seven of Eight Prefetch, 2: Three of Four Prefetch, 3: Half
-  Prefetch Half Non-Prefetch(Default), 4: Three of Four Non-Prefetch, 5: Seven of
-  Eight Prefetch, 6: All Non-prefetch
-  0: All prefetch, 1: Seven of Eight Prefetch, 2: Three of Four Prefetch, 3: Half
-  Prefetch Half Non-Prefetch, 4: Three of Four Non-Prefetch, 5: Seven of Eight Prefetch,
-  6: All Non-prefetch
-**/
-  UINT8                       PrefetchNonPrefetchRatio;
-
-/** Offset 0x05F2 - SaPreMemRestrictedRsvd
-  Reserved for SA Pre-Mem Restricted
-  $EN_DIS
-**/
-  UINT8                       SaPreMemRestrictedRsvd[30];
-
-/** Offset 0x0610 - MSEG Size
-  MSEG Size. Valid values 0 : 512K , 1 : 1M , 2 : 1.5M , 3 : 2M , 4 : 2.4M , 5 : 3M
-  0 : 512K , 1 : 1M , 2 : 1.5M , 3 : 2M , 4 : 2.4M , 5 : 3M
-**/
-  UINT64                      MsegSize;
-
-/** Offset 0x0618 - Force TXT Enable
-  Force TXT Enable; 0: disable, 1: enable
-  $EN_DIS
-**/
-  UINT8                       ForceTxtEnable;
-
-/** Offset 0x0619 - SaPreMemRestrictedRsvd
-  Reserved for SA Pre-Mem Restricted
-  $EN_DIS
-**/
-  UINT8                       CpuPreMemRestrictedRsvd[23];
-
-/** Offset 0x0630 - Dmi Test Tran Co Over En
-  Enable/Disable Lane Transmitter Coefficient.
-**/
-  UINT8                       PchTestDmiTranCoOverEn[4];
-
-/** Offset 0x0634 - Dmi Test Tran Co Over Post Cur
-  Lane Transmitter Post-Cursor Coefficient Override.
-**/
-  UINT8                       PchTestDmiTranCoOverPostCur[4];
-
-/** Offset 0x0638 - Dmi Test Tran Co Over Pre Cur
-  Lane Transmitter Pre-Cursor Coefficient Override.
-**/
-  UINT8                       PchTestDmiTranCoOverPreCur[4];
-
-/** Offset 0x063C - Dmi Test Up Port Tran Preset
-  Upstream Port Lane Transmitter Preset.
-**/
-  UINT8                       PchTestDmiUpPortTranPreset[4];
-
-/** Offset 0x0640 - Dmi Test UpPort Tran Preset En
-  0: POR setting, 1: force enable, 2: force disable.
-**/
-  UINT8                       PchTestDmiUpPortTranPresetEn;
-
-/** Offset 0x0641 - Dmi Test Rtlepceb
-  DMI Remote Transmit Link Equalization Preset/Coefficient Evaluation Bypass (RTLEPCEB).
-**/
-  UINT8                       PchTestDmiRtlepceb;
-
-/** Offset 0x0642 - DMI ME UMA Root Space Check
-  DMI IOSF Root Space attribute check for RS3 for cycles targeting MEUMA.
-  0: POR, 1: enable, 2: disable
-**/
-  UINT8                       PchTestDmiMeUmaRootSpaceCheck;
-
-/** Offset 0x0643 - ModPhy Selection Policy
-  ModPhy Selection for ChipsetInitTable 
-**/
-  UINT8                       ModPhySelection;
-
-/** Offset 0x0644 - HECI Communication
-  Test, 0: POR, 1: enable, 2: disable, Disables HECI communication causing ME to enter
-  error state.
-  $EN_DIS
-**/
-  UINT8                       HeciCommunication;
-
-/** Offset 0x0645 - HECI3 Interface Communication
-  Test, 0: POR, 1: enable, 2: disable, Adds or Removes HECI3 Device from PCI space.
-  $EN_DIS
-**/
-  UINT8                       HeciCommunication3;
-
-/** Offset 0x0646 - Notification test for Host Reset
-  Test, 0: POR, 1: enable, 2: disable, Enable test for notification when Host Reset
-  $EN_DIS
-**/
-  UINT8                       HostResetNotification;
-
-/** Offset 0x0647 - Send Manufacturing Reset And Halt On S3 Resume
-  Test, 0: POR, 1: enable, 2: disable, Enable sending Manufacturing Reset and Halt
-  on S3 Resume
-  $EN_DIS
-**/
-  UINT8                       ManufRstAndHaltOnS3Resume;
-
-/** Offset 0x0648 - Force Unlock AES
-  0(Default)=Disable, 1=Enable
-  $EN_DIS
-**/
-  UINT8                       ForceUnlockAes;
-
-/** Offset 0x0649 - PreMemRestrictedRsvd2
-  Reserved for Pre-Mem RestrictedReserved
-  $EN_DIS
-**/
-  UINT8                       PreMemRestrictedRsvd2[23];
-
-/** Offset 0x0660 - Asynchronous ODT
-  This option configures the Memory Controler Asynchronous ODT control
-  0:Enabled, 1:Disabled
-**/
-  UINT8                       AsyncOdtDis;
-
-/** Offset 0x0661 - Power Down Mode
-  This option controls command bus tristating during idle periods
-  0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
-**/
-  UINT8                       PowerDownMode;
-
-/** Offset 0x0662 - Time Measure
-  Time Measure: 0(Default)=Disable, 1=Enable
-  $EN_DIS
-**/
-  UINT8                       MrcTimeMeasure;
-
-/** Offset 0x0663 - DLL Weak Lock Support
-  Enables/Disable DLL Weak Lock Support
-  $EN_DIS
-**/
-  UINT8                       WeaklockEn;
-
-/** Offset 0x0664 - Fore 1 DPC config
-  Enables/Disable Fore 1 DPC config
-  $EN_DIS
-**/
-  UINT8                       Force1Dpc;
-
-/** Offset 0x0665 - Fore Single Rank config
-  Enables/Disable Fore Single Rank config
-  $EN_DIS
-**/
-  UINT8                       ForceSingleRank;
-
-/** Offset 0x0666 - SelfRefresh IdleTimer
-  SelfRefresh IdleTimer, Default is 512
-**/
-  UINT16                      SrefCfgIdleTmr;
-
-/** Offset 0x0668 - Strong Weak Leaker
-  Strong Weak Leaker value. 7=def
-**/
-  UINT8                       StrongWkLeaker;
-
-/** Offset 0x0669
-**/
-  UINT8                       MrcRestrictedRsvd0x0669[1];
-
-/** Offset 0x066A - Opportunistic Read
-  Enables/Disable Opportunistic Read (Def= Enable)
-  $EN_DIS
-**/
-  UINT8                       OpportunisticRead;
-
-/** Offset 0x066B - Stacked Mode
-  Memory Stacked Mode Support (Def = Disable)
-  $EN_DIS
-**/
-  UINT8                       MemStackMode;
-
-/** Offset 0x066C - Stacked Mode Ch Bit
-  Channel hash bit used during Stacked Mode(Def= BIT28)
-  0:BIT28, 1:BIT29, 2:BIT30, 3:BIT31, 4:BIT32, 5:BIT33, 6:BIT34
-**/
-  UINT8                       StackModeChBit;
-
-/** Offset 0x066D - Low Memory Channel
-  Selecting which Physical Channel is mapped to low memory.
-  0:Channel A, 1:Channel B
-**/
-  UINT8                       LowMemChannel;
-
-/** Offset 0x066E - Cycle Bypass Support
-  Enables/Disable Cycle Bypass Support(Def=Disable)
-  $EN_DIS
-**/
-  UINT8                       Disable2CycleBypass;
-
-/** Offset 0x066F - MC Register Offset
-  Apply user offsets to select MC registers(Def=Disable)
-  $EN_DIS
-**/
-  UINT8                       MCREGOFFSET;
-
-/** Offset 0x0670 - CA Vref Ctl Offset
-  Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.CAVref
-  0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0,
-  13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11,
-  24:+12, 0xFF:RANDOM
-**/
-  UINT8                       CAVrefCtlOffset;
-
-/** Offset 0x0671 - Ch0 DQ Vref Ctrl Offset
-  Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch0VrefCtl
-  0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0,
-  13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11,
-  24:+12, 0xFF:RANDOM
-**/
-  UINT8                       Ch0VrefCtlOffset;
-
-/** Offset 0x0672 - Ch1 DQ Vref Ctrl Offset
-  Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch1VrefCtl
-  0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0,
-  13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11,
-  24:+12, 0xFF:RANDOM
-**/
-  UINT8                       Ch1VrefCtlOffset;
-
-/** Offset 0x0673 - Ch0 Clk PI Code Offset
-  Offset to be applied to DDRCLKCH0_CR_DDRCRCLKPICODE.PiSettingRank[0-3]
-  0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM
-**/
-  UINT8                       Ch0ClkPiCodeOffset;
-
-/** Offset 0x0674 - Ch1 Clk PI Code Offset
-  Offset to be applied to DDRCLKCH1_CR_DDRCRCLKPICODE.PiSettingRank[0-3]
-  0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM
-**/
-  UINT8                       Ch1ClkPiCodeOffset;
-
-/** Offset 0x0675 - Ch0 RcvEn Offset
-  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RcvEn
-  0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
-**/
-  UINT8                       Ch0RcvEnOffset;
-
-/** Offset 0x0676 - Ch1 RcvEn Offset
-  Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.RcvEn
-  0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
-**/
-  UINT8                       Ch1RcvEnOffset;
-
-/** Offset 0x0677 - Ch0 Rx Dqs Offset
-  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset
-  0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
-**/
-  UINT8                       Ch0RxDqsOffset;
-
-/** Offset 0x0678 - Ch1 Rx Dqs Offset
-  Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset
-  0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
-**/
-  UINT8                       Ch1RxDqsOffset;
-
-/** Offset 0x0679 - Ch0 Tx Dq Offset
-  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset
-  0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
-**/
-  UINT8                       Ch0TxDqOffset;
-
-/** Offset 0x067A - Ch1 Tx Dq Offset
-  Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset
-  0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
-**/
-  UINT8                       Ch1TxDqOffset;
-
-/** Offset 0x067B - Ch0 Tx Dqs Offset
-  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset
-  0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
-**/
-  UINT8                       Ch0TxDqsOffset;
-
-/** Offset 0x067C - Ch1 Tx Dqs Offset
-  Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset
-  0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM
-**/
-  UINT8                       Ch1TxDqsOffset;
-
-/** Offset 0x067D - Ch0 Vref Offset
-  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
-  0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM
-**/
-  UINT8                       Ch0VrefOffset;
-
-/** Offset 0x067E - Ch1 Vref Offset
-  Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
-  0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM
-**/
-  UINT8                       Ch1VrefOffset;
-
-/** Offset 0x067F - tRRSG
-  Delay between Read-to-Read commands in the same Bank Group for DDR4 or Same Rank
-  for DDR3/LPDDR3. 0-Auto, Range 4-54.
-**/
-  UINT8                       tRRSG;
-
-/** Offset 0x0680 - tRRDG
-  Delay between Read-to-Read commands in different Bank Group for DDR4 or Same Rank
-  for DDR3/LPDDR3. 0-Auto, Range 4-54.
-**/
-  UINT8                       tRRDG;
-
-/** Offset 0x0681 - tRRDR
-  Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54.
-**/
-  UINT8                       tRRDR;
-
-/** Offset 0x0682 - tRRDD
-  Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
-**/
-  UINT8                       tRRDD;
-
-/** Offset 0x0683 - tWRSG
-  Delay between Write-to-Read commands in the same Bank Group for DDR4 or Same Rank
-  for DDR3/LPDDR3. 0-Auto, Range 4-86.
-**/
-  UINT8                       tWRSG;
-
-/** Offset 0x0684 - tWRDG
-  Delay between Write-to-Read commands in different Bank Group for DDR4 or Same Rank
-  for DDR3/LPDDR3. 0-Auto, Range 4-54.
-**/
-  UINT8                       tWRDG;
-
-/** Offset 0x0685 - tWRDR
-  Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54.
-**/
-  UINT8                       tWRDR;
-
-/** Offset 0x0686 - tWRDD
-  Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
-**/
-  UINT8                       tWRDD;
-
-/** Offset 0x0687 - tWWSG
-  Delay between Write-to-Write commands in the same Bank Group for DDR4 or Same Rank
-  for DDR3/LPDDR3. 0-Auto, Range 4-54.
-**/
-  UINT8                       tWWSG;
-
-/** Offset 0x0688 - tWWDG
-  Delay between Write-to-Write commands in different Bank Group for DDR4 or Same Rank
-  for DDR3/LPDDR3. 0-Auto, Range 4-54.
-**/
-  UINT8                       tWWDG;
-
-/** Offset 0x0689 - tWWDR
-  Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54.
-**/
-  UINT8                       tWWDR;
-
-/** Offset 0x068A - tWWDD
-  Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
-**/
-  UINT8                       tWWDD;
-
-/** Offset 0x068B - tRWSG
-  Delay between Read-to-Write commands in the same Bank Group for DDR4 or Same Rank
-  for DDR3/LPDDR3. 0-Auto, Range 4-54.
-**/
-  UINT8                       tRWSG;
-
-/** Offset 0x068C - tRWDG
-  Delay between Read-to-Write commands in different Bank Group for DDR4 or Same Rank
-  for DDR3/LPDDR3. 0-Auto, Range 4-54.
-**/
-  UINT8                       tRWDG;
-
-/** Offset 0x068D - tRWDR
-  Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54.
-**/
-  UINT8                       tRWDR;
-
-/** Offset 0x068E - tRWDD
-  Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
-**/
-  UINT8                       tRWDD;
-
-/** Offset 0x068F - DCTT Test
-  Select which test to run
-  0:Basic walking memory test, 1:Row Hammer test
-**/
-  UINT8                       DcttTest;
-
-/** Offset 0x0690 - DCTT: Iterations on Row
-  Number of repetitions on a Row
-**/
-  UINT8                       DcttRhIterationOnRow;
-
-/** Offset 0x0691 - Page Close Delay Prompt
-  SubSequence Delay value used to ensure the page closes (In DClks)
-**/
-  UINT8                       DcttRhPageCloseDelay;
-
-/** Offset 0x0692 - Row Hammer Refresh
-  Enable/Disables refreshes during the Row Hammer Test
-  $EN_DIS
-**/
-  UINT8                       DcttRhRefreshEnable;
-
-/** Offset 0x0693 - Data Base
-  Select which data pattern that is used as the base pattern
-  0:Zeros, 1:Ones, 2:Five, 3:A
-**/
-  UINT8                       DcttDataBase;
-
-/** Offset 0x0694 - DCTT: Row Hammer Count
-  Number of Hammers for a given Row.
-**/
-  UINT32                      DcttRhHammerCount;
-
-/** Offset 0x0698 - Row swizzle
-  Select which Row swizzle algorithm to use during Row Hammer test
-  0:No Swizzle, 1:3xOr1_3xOr2, 2:01234567EFCDAB89
-**/
-  UINT8                       DcttRowSwizzleType;
-
-/** Offset 0x0699 - Refresh Multiplier
-  Multiplier applied to tREFI
-**/
-  UINT8                       DcttRefreshMultiplier;
-
-/** Offset 0x069A - Bank Disable Mask
-  Bit Mask Bank Disable for per-Bank tests (Row Hammer)
-**/
-  UINT8                       DcttBankDisableMask;
-
-/** Offset 0x069B - Clock Gate AB
-  Clock Gate AB
-  0:Disable, 1:2 Cycles, 2:3 Cycles, 3:4 Cycles
-**/
-  UINT8                       ScramClockGateAB;
-
-/** Offset 0x069C - Clock Gate C
-  Select which Row swizzle algorithm to use during Row Hammer test
-  0:Disable, 1:2 Cycles, 2:4 Cycles, 3:8 Cycles
-**/
-  UINT8                       ScramClockGateC;
-
-/** Offset 0x069D - Enable DBI AB
-  Enable DBI AB
-  $EN_DIS
-**/
-  UINT8                       ScramEnableDbiAB;
-
-/** Offset 0x069E - MRC Interpreter
-  Select CMOS location match of DD01 or Ctrl-Break key or force entry
-  0:CMOS, 1:Break, 2:Force
-**/
-  UINT8                       Interpreter;
-
-/** Offset 0x069F - ODT mode
-  ODT mode
-  0:Default, 1:Ctt, 2:Vtt, 3:Vddq, 4:Vss,5:Max
-**/
-  UINT8                       IoOdtMode;
-
-/** Offset 0x06A0 - Lock DPR register
-  Lock DPR register. <b>0: Platform POR </b>; 1: Enable; 2: Disable
-  0:Platform POR, 1: Enable, 2: Disable
-**/
-  UINT8                       TestMenuDprLock;
-
-/** Offset 0x06A1 - PerBankRefresh
-  Control of Per Bank Refresh feature for LPDDR DRAMs
-  $EN_DIS
-**/
-  UINT8                       PerBankRefresh;
-
-/** Offset 0x06A2 - Command Tristate
-  Enables/Disable Command Tristate
-  $EN_DIS
-**/
-  UINT8                       CmdTriStateDis;
-
-/** Offset 0x06A3
-**/
-  UINT8                       MrcRestrictedRsvd[1];
-
-/** Offset 0x06A4
-**/
-  UINT8                       ReservedFspmRestrictedUpd[26];
-} FSP_M_RESTRICTED_CONFIG;
-
 /** Fsp M UPD Configuration
 **/
 typedef struct {
@@ -3344,10 +2647,6 @@ typedef struct {
 
 /** Offset 0x05B0
 **/
-  FSP_M_RESTRICTED_CONFIG     FspmRestrictedConfig;
-
-/** Offset 0x06BE
-**/
   UINT16                      UpdTerminator;
 } FSPM_UPD;
 
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
index ac660eba60..2a2412d8ff 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
@@ -1793,9 +1793,10 @@ typedef struct {
   UINT8                       PchScsEmmcHs400DriverStrength;
 
 /** Offset 0x06FA - PCH SerialIo I2C Pads Termination
-  0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak
-  pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination
-  respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5
+  pads termination respectively. One byte for each controller, byte0 for I2C0, byte1
+  for I2C1, and so on.
   0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU
 **/
   UINT8                       PchSerialIoI2cPadsTermination[6];
@@ -2927,11 +2928,18 @@ typedef struct {
 **/
   UINT8                       C1StateUnDemotion;
 
-/** Offset 0x08A2 - ReservedCpuPostMemTest
+/** Offset 0x08A2 - CpuWakeUpTimer
+  Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased
+  to 180 seconds. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       CpuWakeUpTimer;
+
+/** Offset 0x08A3 - ReservedCpuPostMemTest
   Reserved for CPU Post-Mem Test
   $EN_DIS
 **/
-  UINT8                       ReservedCpuPostMemTest[24];
+  UINT8                       ReservedCpuPostMemTest[23];
 
 /** Offset 0x08BA - SgxSinitDataFromTpm
   SgxSinitDataFromTpm default values
@@ -3080,16 +3088,9 @@ typedef struct {
 **/
   UINT8                       PchXhciOcLock;
 
-/** Offset 0x0A61 - PCH USB Access Control setting
-  This policy option controls setting the Access Control (ACCTRL) bit in XHCC1 which
-  will lock write access to registers controlled by its functionality.
-  $EN_DIS
+/** Offset 0x0A61
 **/
-  UINT8                       PchXhciAcLock;
-
-/** Offset 0x0A62
-**/
-  UINT8                       UnusedUpdSpace26[16];
+  UINT8                       UnusedUpdSpace26[17];
 
 /** Offset 0x0A72 - Skip POSTBOOT SAI
   This skip the Post Boot Sai programming. 0: Set Post Boot Sai; 1: Skip Post Boot Sai.
@@ -3108,906 +3109,6 @@ typedef struct {
   UINT8                       ReservedFspsTestUpd[12];
 } FSP_S_TEST_CONFIG;
 
-/** Fsp S Restricted Configuration
-**/
-typedef struct {
-
-/** Offset 0x0A80
-**/
-  UINT32                      Signature;
-
-/** Offset 0x0A84
-**/
-  UINT8                       UnusedUpdSpace27;
-
-/** Offset 0x0A85 - Enable or disable GNA Error Check Disable Bit
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       TestGnaErrorCheckDis;
-
-/** Offset 0x0A86 - Enable or disable VT-d DmaPassThrough
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       DmaPassThrough;
-
-/** Offset 0x0A87 - Enable or disable VT-d CCHit2pend
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       CCHit2pend;
-
-/** Offset 0x0A88 - Enable or disable VT-d ContextInvalidation
-  0(Default)=Disable, 1=Enable
-  $EN_DIS
-**/
-  UINT8                       ContextInvalidation;
-
-/** Offset 0x0A89 - Enable or disable VT-d IotlbInvalidation
-  0(Default)=Disable, 1=Enable
-  $EN_DIS
-**/
-  UINT8                       IotlbInvalidation;
-
-/** Offset 0x0A8A - Enable or disable VT-d ContextCacheDis
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       ContextCacheDis;
-
-/** Offset 0x0A8B - Enable or disable VT-d L1Disable
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       L1Disable;
-
-/** Offset 0x0A8C - Enable or disable VT-d L2Disable
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       L2Disable;
-
-/** Offset 0x0A8D - Enable or disable VT-d L3Disable
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       L3Disable;
-
-/** Offset 0x0A8E - Enable or disable VT-d L1Hit2PendDis
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       L1Hit2PendDis;
-
-/** Offset 0x0A8F - Enable or disable VT-d L3Hit2PendDis
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       L3Hit2PendDis;
-
-/** Offset 0x0A90 - Enable or disable VT-d InvQueueCohDis
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       InvQueueCohDis;
-
-/** Offset 0x0A91 - Enable or disable VT-d SuperPageCap
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       SuperPageCap;
-
-/** Offset 0x0A92 - Enable or disable VT-d QueueInvCapDis
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       QueueInvCapDis;
-
-/** Offset 0x0A93 - Enable or disable VT-d IntrRemapCapDis
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       TestIntrRemapCapDis;
-
-/** Offset 0x0A94 - Enable or disable VT-d SnoopControl
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       SnoopControl;
-
-/** Offset 0x0A95 - Enable or disable VT-d RemapReverseCtrl
-  0=Disable, 1(Default)=Enable
-  $EN_DIS
-**/
-  UINT8                       RemapReverseCtrl;
-
-/** Offset 0x0A96 - Enable or disable VT-d SvPolicyEnable
-  0(Default)=Disable, 1=Enable
-  $EN_DIS
-**/
-  UINT8                       VtdSvPolicyEnable;
-
-/** Offset 0x0A97 - Sa Graphics Pei Test Force Wake
-  Test Force Wake
-**/
-  UINT8                       SaTestForceWake;
-
-/** Offset 0x0A98 - Sa Graphics Pei Test Gfx Pause
-  Test Gfx Pause
-**/
-  UINT8                       SaTestGfxPause;
-
-/** Offset 0x0A99 - Sa Graphics Pei Test Graphics Freq Modify
-  Test Graphics Freq Modify
-**/
-  UINT8                       SaTestGraphicsFreqModify;
-
-/** Offset 0x0A9A - Sa Graphics Pei Test PmLock
-  Test PmLock
-**/
-  UINT8                       SaTestPmLock;
-
-/** Offset 0x0A9B - Sa Graphics Pei Test Pavp Heavy Mode
-  Test Pavp Heavy Mode
-**/
-  UINT8                       SaTestPavpHeavyMode;
-
-/** Offset 0x0A9C - Sa Graphics Pei Test Dop ClockGating
-  Test Dop ClockGating
-**/
-  UINT8                       SaTestDopClockGating;
-
-/** Offset 0x0A9D - Sa Graphics Pei Test Unsolicited Attack Override
-  Test Unsolicited Attack Override
-**/
-  UINT8                       SaTestUnsolicitedAttackOverride;
-
-/** Offset 0x0A9E - Sa Graphics Pei Test WOPCM Support
-  Test WOPCM Support
-**/
-  UINT8                       SaTestWOPCMSupport;
-
-/** Offset 0x0A9F - Sa Graphics Pei Test Pavp Asmf
-  Test Pavp Asmf
-**/
-  UINT8                       SaTestPavpAsmf;
-
-/** Offset 0x0AA0 - Sa Graphics Pei Test Power Gating
-  Test Power Gating
-**/
-  UINT8                       SaTestPowerGating;
-
-/** Offset 0x0AA1 - Sa Graphics Pei Test Unit Level ClockGating
-  Test Unit Level ClockGating
-**/
-  UINT8                       SaTestUnitLevelClockGating;
-
-/** Offset 0x0AA2 - Sa Graphics Pei Test Auto TearDown
-  Test Auto TearDown
-**/
-  UINT8                       SaTestAutoTearDown;
-
-/** Offset 0x0AA3 - Sa Graphics Pei Test Graphics Video Freq
-  Test Graphics Video Freq
-**/
-  UINT8                       SaTestGraphicsVideoFreq;
-
-/** Offset 0x0AA4 - Sa Graphics Pei Test WOPCM Size
-  Test WOPCM Size
-**/
-  UINT8                       SaTestWOPCMSize;
-
-/** Offset 0x0AA5 - Sa Graphics Pei Test Graphics Freq Req
-  Test Graphics Freq Req
-**/
-  UINT8                       SaTestGraphicsFreqReq;
-
-/** Offset 0x0AA6 - Sa Test Peg Aspm L0s Aggression
-  Test Peg Aspm L0s Aggression
-**/
-  UINT8                       SaTestPegAspmL0sAggression[4];
-
-/** Offset 0x0AAA - Sa Clear CorrUnCorrErr Enable
-  Clear CorrUnCorrErr Enable
-  $EN_DIS
-**/
-  UINT8                       SaClearCorrUnCorrErrEnable;
-
-/** Offset 0x0AAB - Sa SvPegArifen
-  SvPegArifen
-**/
-  UINT8                       SaSvPegArifen[4];
-
-/** Offset 0x0AAF - Sa Peg0 Completion Timeout
-  Peg0 Completion Timeout
-**/
-  UINT8                       SaPeg0CompletionTimeout;
-
-/** Offset 0x0AB0 - Sa Peg1 Completion Timeout
-  Peg1 Completion Timeout
-**/
-  UINT8                       SaPeg1CompletionTimeout;
-
-/** Offset 0x0AB1 - Sa Peg2 Completion Timeout
-  Peg2 Completion Timeout
-**/
-  UINT8                       SaPeg2CompletionTimeout;
-
-/** Offset 0x0AB2 - Sa Peg3 Completion Timeout
-  Peg3 Completion Timeout
-**/
-  UINT8                       SaPeg3CompletionTimeout;
-
-/** Offset 0x0AB3 - Sa Sv Peg Compliance Deemphasis
-  SvPegComplianceDeemphasis
-**/
-  UINT8                       SaSvPegComplianceDeemphasis[4];
-
-/** Offset 0x0AB7 - Sa Sv Peg TxLn Staggering Mode
-  SvPegTxLnStaggeringMode
-**/
-  UINT8                       SaSvPegTxLnStaggeringMode[4];
-
-/** Offset 0x0ABB - Sa Sv Peg TxLane Staggering Interval
-  SvPegTxLaneStaggeringInterval
-**/
-  UINT8                       SaSvPegTxLaneStaggeringInterval[4];
-
-/** Offset 0x0ABF - Sa Sv Peg RxLn Staggering Mode
-  SvPegRxLnStaggeringMode
-**/
-  UINT8                       SaSvPegRxLnStaggeringMode[4];
-
-/** Offset 0x0AC3 - Sa Sv Peg RxLane Staggering Interval
-  SvPegRxLaneStaggeringInterval
-**/
-  UINT8                       SaSvPegRxLaneStaggeringInterval[4];
-
-/** Offset 0x0AC7 - Sa Test MpllOffSen
-  TestMpllOffSen
-**/
-  UINT8                       SaTestMpllOffSen;
-
-/** Offset 0x0AC8 - Sa Test MdllOffSen
-  TestMdllOffSen
-**/
-  UINT8                       SaTestMdllOffSen;
-
-/** Offset 0x0AC9 - Sa Test Mode Edram Internal
-  Edram Enable Option
-**/
-  UINT8                       SaTestModeEdramInternal;
-
-/** Offset 0x0ACA - Sa Test Security Lock
-  Enable/Disable Security lock
-**/
-  UINT8                       SaTestSecurityLock;
-
-/** Offset 0x0ACB
-**/
-  UINT8                       UnusedUpdSpace28[49];
-
-/** Offset 0x0AFC - SaPostMemRestrictedRsvd
-  Reserved for SA Post-Mem Restricted
-  $EN_DIS
-**/
-  UINT8                       SaPostMemRestrictedRsvd[22];
-
-/** Offset 0x0B12 - CpuPostMemRestrictedRsvd
-  Reserved for CPU Post-Mem Restricted
-  $EN_DIS
-**/
-  UINT8                       CpuPostMemRestrictedRsvd[16];
-
-/** Offset 0x0B22 - BiosGuardModulePtr
-  BiosGuardModulePtr default values
-**/
-  UINT8                       EnableSgx7a;
-
-/** Offset 0x0B23 - SgxDebugMode
-  SgxDebugMode default values
-**/
-  UINT8                       SgxDebugMode;
-
-/** Offset 0x0B24 - SvLtEnable
-  SvLtEnable default values
-**/
-  UINT8                       SvLtEnable;
-
-/** Offset 0x0B25 - SelectiveEnableSgx
-  SelectiveEnableSgx default values
-**/
-  UINT8                       SelectiveEnableSgx;
-
-/** Offset 0x0B26 - EpcOffset
-  EpcOffset default values
-**/
-  UINT64                      EpcOffset;
-
-/** Offset 0x0B2E - EpcLength
-  EpcLength default values
-**/
-  UINT64                      EpcLength;
-
-/** Offset 0x0B36 - SgxLCP
-  SgxLCP default values
-**/
-  UINT8                       SgxLCP;
-
-/** Offset 0x0B37 - EpcLength
-  EpcLength default values
-**/
-  UINT64                      SgxLEPubKeyHash0;
-
-/** Offset 0x0B3F - EpcLength
-  EpcLength default values
-**/
-  UINT64                      SgxLEPubKeyHash1;
-
-/** Offset 0x0B47 - EpcLength
-  EpcLength default values
-**/
-  UINT64                      SgxLEPubKeyHash2;
-
-/** Offset 0x0B4F - EpcLength
-  EpcLength default values
-**/
-  UINT64                      SgxLEPubKeyHash3;
-
-/** Offset 0x0B57 - CpuPostMemRestrictedRsvd
-  Reserved for CPU Post-Mem Restricted
-  $EN_DIS
-**/
-  UINT8                       SecurityRestrictedRsvd[1];
-
-/** Offset 0x0B58 - MEM CLOSED State on PCH side
-  Enable/Disable MEM CLOSED State on PCH side.
-  $EN_DIS
-**/
-  UINT8                       PchDmiTestMemCloseStateEn;
-
-/** Offset 0x0B59 - Optimized Buffer Flush/Fill (OBFF) protocol for internal on PCH side
-  enable/disable Optimized Buffer Flush/Fill (OBFF) protocol for internal on PCH side.
-  $EN_DIS
-**/
-  UINT8                       PchDmiTestInternalObffEn;
-
-/** Offset 0x0B5A - Determines if force extended transmission of FTS ordered sets
-  Determines if force extended transmission of FTS ordered sets when exiting L0s prior
-  to entering L0.
-**/
-  UINT8                       PchDmiTestDmiExtSync;
-
-/** Offset 0x0B5B - Optimized Buffer Flush/Fill (OBFF) protocol for external on PCH side
-  Enable/Disable Optimized Buffer Flush/Fill (OBFF) protocol for external on PCH side.
-  $EN_DIS
-**/
-  UINT8                       PchDmiTestExternalObffEn;
-
-/** Offset 0x0B5C - Client Obff Enable
-  Client Obff Enable.
-  $EN_DIS
-**/
-  UINT8                       PchDmiTestClientObffEn;
-
-/** Offset 0x0B5D - CxObff Entry Delay
-  CxObff Entry Delay.
-**/
-  UINT8                       PchDmiTestCxObffEntryDelay;
-
-/** Offset 0x0B5E
-**/
-  UINT8                       UnusedUpdSpace29;
-
-/** Offset 0x0B5F - Pch Tc Lock Down
-  Pch Tc Lock Down.
-  $EN_DIS
-**/
-  UINT8                       PchDmiTestPchTcLockDown;
-
-/** Offset 0x0B60 - Enable DMI ASPM after booting to OS
-  Enable DMI ASPM after booting to OS.
-  $EN_DIS
-**/
-  UINT8                       PchDmiTestDelayEnDmiAspm;
-
-/** Offset 0x0B61 - Dmi Aspm Ctrl
-  Dmi Aspm Ctrl.
-  $EN_DIS
-**/
-  UINT8                       PchDmiTestDmiAspmCtrl;
-
-/** Offset 0x0B62 - DMI Secure Reg Lock
-  DMI Secure Reg Lock.
-  0: POR (Enable), 1: Enable, 2: Disable
-**/
-  UINT8                       PchDmiTestDmiSecureRegLock;
-
-/** Offset 0x0B63
-**/
-  UINT8                       UnusedUpdSpace30;
-
-/** Offset 0x0B64 - Configuration Lockdown (BCLD)
-  0: POR (Enable), 1: Enable, 2: Disable.
-  0: POR (Enable), 1: Enable, 2: Disable
-**/
-  UINT8                       PchHdaTestConfigLockdown;
-
-/** Offset 0x0B65 - Low Frequency Link Clock Source (LFLCS)
-  0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL).
-  0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL)
-**/
-  UINT8                       PchHdaTestLowFreqLinkClkSrc;
-
-/** Offset 0x0B66
-**/
-  UINT8                       UnusedUpdSpace31[4];
-
-/** Offset 0x0B6A - PCH Lan Test WOL Fast Support
-  Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm.
-  $EN_DIS
-**/
-  UINT8                       PchLanTestPchWOLFastSupport;
-
-/** Offset 0x0B6B - Smi Unlock bit for SV policy
-  0: Lock; 1: Unlock.
-  $EN_DIS
-**/
-  UINT8                       PchLockDownTestSmiUnlock;
-
-/** Offset 0x0B6C - PchPostMemRestrictedRsvd
-  Reserved for PCH Post-Mem Restricted Reserved
-  $EN_DIS
-**/
-  UINT8                       PchPostMemRestrictedRsvd[24];
-
-/** Offset 0x0B84 - Gen3 EQ Phase2 Tx override
-  Coefficient requested by the remote device is ignored.
-**/
-  UINT8                       PcieRpTestEqPh2Override[24];
-
-/** Offset 0x0B9C - Tx preset to use when TestEqPh2Override is set
-  Tx preset to use when TestEqPh2Override is set.
-**/
-  UINT8                       PcieRpTestEqPh2Preset[24];
-
-/** Offset 0x0BB4 - Enable/Disable ASPM Optionality Compliance
-  Enable/Disable ASPM Optionality Compliance.
-**/
-  UINT8                       PcieRpTestAspmOc[24];
-
-/** Offset 0x0BCC - Force LTR Override
-  Force LTR Override.
-**/
-  UINT8                       PcieRpTestForceLtrOverride[24];
-
-/** Offset 0x0BE4
-**/
-  UINT8                       UnusedUpdSpace32[72];
-
-/** Offset 0x0C2C - PCH Pcie bem
-  PCH Pcie bem.
-**/
-  UINT8                       PcieTestPchPciebem;
-
-/** Offset 0x0C2D - PCH Pcie Test bem Port Index
-  PCH Pcie Test bem Port Index.
-**/
-  UINT8                       PcieTestPchPciebemPortIndex;
-
-/** Offset 0x0C2E - PCH Test PcieRp dbc gen
-  PCH Test PcieRp dbc gen.
-**/
-  UINT8                       PcieTestPchPcieRpdbcgen;
-
-/** Offset 0x0C2F - PCH Test PcieRp dlc gen
-  PCH Test PcieRp dlc gen.
-**/
-  UINT8                       PcieTestPchPcieRpdlcgen;
-
-/** Offset 0x0C30 - PCH Test Pcie Dcgeisma
-  PCH Test Pcie Dcgeisma.
-**/
-  UINT8                       PcieTestPchPcieDcgeisma;
-
-/** Offset 0x0C31 - PCH Test PcieRp scgen
-  PCH Test PcieRp scgen.
-**/
-  UINT8                       PcieTestPchPcieRpscgen;
-
-/** Offset 0x0C32 - PCH Test Pcie Srdbcgen
-  PCH Test Pcie Srdbcgen.
-**/
-  UINT8                       PcieTestPchPcieSrdbcgen;
-
-/** Offset 0x0C33 - PCH Test Pcie Scptcge
-  PCH Test Pcie Scptcge.
-**/
-  UINT8                       PcieTestPchPcieScptcge;
-
-/** Offset 0x0C34 - PCH Test Pcie Fdppge
-  PCH Test Pcie Fdppge.
-**/
-  UINT8                       PcieTestPchPcieFdppge;
-
-/** Offset 0x0C35 - PCH Test Pcie Phyclpge
-  PCH Test Pcie Phyclpge.
-**/
-  UINT8                       PcieTestPchPciePhyclpge;
-
-/** Offset 0x0C36 - PCH Test Pcie Fdcpge
-  PCH Test Pcie Fdcpge.
-**/
-  UINT8                       PcieTestPchPcieFdcpge;
-
-/** Offset 0x0C37 - PCH Test Pcie Detscpge
-  PCH Test Pcie Detscpge.
-**/
-  UINT8                       PcieTestPchPcieDetscpge;
-
-/** Offset 0x0C38 - PCH Test Pcie L23 rdyscpge
-  PCH Test Pcie L23 rdyscpge.
-**/
-  UINT8                       PcieTestPchPcieL23rdyscpge;
-
-/** Offset 0x0C39 - PCH Test Pcie Disscpge
-  PCH Test Pcie Disscpge.
-**/
-  UINT8                       PcieTestPchPcieDisscpge;
-
-/** Offset 0x0C3A - PCH Test Pcie L1 scpge
-  PCH Test Pcie L1 scpge.
-**/
-  UINT8                       PcieTestPchPcieL1scpge;
-
-/** Offset 0x0C3B - PCH Pcie Test Lane Eq En
-  PCH PcieTest Lane Eq En.
-**/
-  UINT8                       PcieTestLaneEqEn;
-
-/** Offset 0x0C3C - PCH Pcie Test Sw Eq Override
-  PCH Pcie bem.
-**/
-  UINT8                       PcieTestSwEqOverride;
-
-/** Offset 0x0C3D - PCH Pcie Test Sw Eq Dwell Time Us
-  PCH Pcie Test Sw Eq Dwell Time Us.
-**/
-  UINT16                      PcieTestSwEqDwellTimeUs;
-
-/** Offset 0x0C3F - PCH Pcie Test Sw Eq Error Threshold
-  PCH Pcie Test Sw Eq Error Threshold.
-**/
-  UINT16                      PcieTestSwEqErrorThreshold;
-
-/** Offset 0x0C41 - PCH Pcie Test Sw Eq Rec Threshold
-  PCH Pcie Test Sw Eq Rec Threshold.
-**/
-  UINT16                      PcieTestSwEqRecThreshold;
-
-/** Offset 0x0C43 - PCH Pcie Test Sw Eq Retrain Timeout Ms
-  PCH Pcie Test Sw Eq Retrain Timeout Ms.
-**/
-  UINT16                      PcieTestSwEqRetrainTimeoutMs;
-
-/** Offset 0x0C45 - PCH Pcie Test Sw Eq Recovery Wait
-  PCH Pcie Test Sw Eq Recovery Wait.
-**/
-  UINT16                      PcieTestSwEqRecoveryWait;
-
-/** Offset 0x0C47 - PCH Pm Register Lock
-  PCH Pm Register Lock.
-**/
-  UINT8                       PchPmTestPchPmRegisterLock;
-
-/** Offset 0x0C48 - PCH Pm Test SlpS0 CsMe PgQDis
-  CPPM VRIC CSME Power Gated Qualification Disable.
-**/
-  UINT8                       PchPmTestSlpS0CsMePgQDis;
-
-/** Offset 0x0C49 - PCH Pm Test Slp S0 Gbe Disc QDis
-  CPPM VRIC GbE Disconnected Qualification Disable.
-**/
-  UINT8                       PchPmTestSlpS0GbeDiscQDis;
-
-/** Offset 0x0C4A - PCH Pm Test Slp S0A Dsp D3 QDis
-  CPPM VRIC Audio DSP is in D3 Qualification Disable.
-**/
-  UINT8                       PchPmTestSlpS0ADspD3QDis;
-
-/** Offset 0x0C4B - PCH Pm Test Slp S0 Xhci D3QDis
-  CPPM VRIC XHCI is in D3 Qualification Disable.
-**/
-  UINT8                       PchPmTestSlpS0XhciD3QDis;
-
-/** Offset 0x0C4C - PCH Pm Test Slp S0 Lpio D3QDis
-  CPPM VRIC LPIO is in D3 Qualification Disable.
-**/
-  UINT8                       PchPmTestSlpS0LpioD3QDis;
-
-/** Offset 0x0C4D - PCH Pm Test Slp S0 Icc Pll W BEn
-  CPPM VRIC ICC PLL Wake Block Enable.
-**/
-  UINT8                       PchPmTestSlpS0IccPllWBEn;
-
-/** Offset 0x0C4E - PCH Pm Test Slp S0 PUGB En
-  PCH Pm CPPM VRIC Power Ungate Block Enable.
-**/
-  UINT8                       PchPmTestSlpS0PUGBEn;
-
-/** Offset 0x0C4F - PCH Pm Test Clear Power Sts
-  @todo ADD DESCRIPTION. Policy for SV usage. NO USE..
-**/
-  UINT8                       PchPmTestPchClearPowerSts;
-
-/** Offset 0x0C50 - PCH Sata Test Rst Pcie Storage Test Mode
-  PCIe Storage remapping Test Mode to override existing PCIe Storage remapping POR
-  setting for development purpose.
-**/
-  UINT8                       SataTestRstPcieStorageTestMode[3];
-
-/** Offset 0x0C53 - PCH Sata Test Rst Pcie Storage Port Config Check
-  Enable/Disable Port Configuration Check for RST PCIe Storage Remapping.
-**/
-  UINT8                       SataTestRstPcieStoragePortConfigCheck[3];
-
-/** Offset 0x0C56 - PCH Sata Test Rst Pcie Storage Device Interface
-  Select the device interface (AHCI/NVME) for remapped device. NO USE.
-**/
-  UINT8                       SataTestRstPcieStorageDeviceInterface[3];
-
-/** Offset 0x0C59 - PCH Sata Test Rst Pcie Storage Device Bar Size Check
-  Enable/Disable Device BAR Size Check for remapped device.
-**/
-  UINT8                       SataTestRstPcieStorageDeviceBarSizeCheck[3];
-
-/** Offset 0x0C5C - PCH Sata Test Rst Pcie Storage Device Bar Select
-  Select the device BAR (BAR0-BAR5) that will be used for Remapping.
-**/
-  UINT8                       SataTestRstPcieStorageDeviceBarSelect[3];
-
-/** Offset 0x0C5F - PCH Sata Test Rst Pcie Storage Device Interrupt
-  Select the device interrupt (Legacy/MSIX) for remapped device.
-**/
-  UINT8                       SataTestRstPcieStorageDeviceInterrupt[3];
-
-/** Offset 0x0C62 - PCH Sata Test Rst Pcie Storage Aspm Programming
-  Enable/Disable ASPM Programming for remapped device.
-**/
-  UINT8                       SataTestRstPcieStorageAspmProgramming[3];
-
-/** Offset 0x0C65 - PCH Sata Test Rst Pcie Storage Save Restore
-  Enable/Disable ASPM Programming for remapped device.
-**/
-  UINT8                       SataTestRstPcieStorageSaveRestore[3];
-
-/** Offset 0x0C68 - Latency Tolerance Reporting Mechanism
-  Latency Tolerance Reporting Mechanism.
-**/
-  UINT8                       SataTestLtrEnable;
-
-/** Offset 0x0C69 - Latency Tolerance Reporting Mechanism
-  Latency Tolerance Reporting Mechanism.
-**/
-  UINT8                       SataTestLtrConfigLock;
-
-/** Offset 0x0C6A - Latency Tolerance Reporting Mechanism
-  Latency Tolerance Reporting Mechanism.
-**/
-  UINT8                       SataTestLtrOverride;
-
-/** Offset 0x0C6B - Latency Tolerance Reporting Mechanism
-  Latency Tolerance Reporting Mechanism.
-**/
-  UINT8                       SataTestSnoopLatencyOverrideMultiplier;
-
-/** Offset 0x0C6C - Latency Tolerance Reporting Mechanism
-  Latency Tolerance Reporting Mechanism.
-**/
-  UINT16                      SataTestSnoopLatencyOverrideValue;
-
-/** Offset 0x0C6E - Latency Tolerance Reporting Mechanism
-  Latency Tolerance Reporting Mechanism.
-**/
-  UINT8                       SataTestSataAssel;
-
-/** Offset 0x0C6F
-**/
-  UINT8                       UnusedUpdSpace33[2];
-
-/** Offset 0x0C71 - This locks down Enables the thermal sensor
-  0: Disabled, 1: Enabled.
-  $EN_DIS
-**/
-  UINT8                       PchTestTselLock;
-
-/** Offset 0x0C72 - This locks down Catastrophic Power-Down Enable and Catastrophic Trip Point Register
-  0: Disabled, 1: Enabled.
-  $EN_DIS
-**/
-  UINT8                       PchTestTscLock;
-
-/** Offset 0x0C73 - This locks down PHL and PHLC
-  0: Disabled, 1: Enabled.
-  $EN_DIS
-**/
-  UINT8                       PchTestPhlcLock;
-
-/** Offset 0x0C74
-**/
-  UINT8                       UnusedUpdSpace34[10];
-
-/** Offset 0x0C7E - USB EP Type Lock Policy
-  USB EP Type Lock Policy.
-**/
-  UINT32                      PchTestEPTypeLockPolicy;
-
-/** Offset 0x0C82 - USB EP Type Lock Policy Control 1
-  USB EP Type Lock Policy Control 1.
-**/
-  UINT32                      PchTestEPTypeLockPolicyPortControl1;
-
-/** Offset 0x0C86 - USB EP Type Lock Policy Control 2
-  USB EP Type Lock Policy Control 2.
-**/
-  UINT32                      PchTestEPTypeLockPolicyPortControl2;
-
-/** Offset 0x0C8A
-**/
-  UINT8                       UnusedUpdSpace35[4];
-
-/** Offset 0x0C8E - Xhci Controller Enable
-  0: Disable; 1: Enable.
-**/
-  UINT8                       PchTestControllerEnabled;
-
-/** Offset 0x0C8F
-**/
-  UINT8                       UnusedUpdSpace36;
-
-/** Offset 0x0C90 - Unlock to enable NOA for SV usage
-  1: Unlock to enable NOA usage. 0: Set Xhci OC registers, Set Xhci OCCDone bit, XHCI
-  Access Control Bit.
-  $EN_DIS
-**/
-  UINT8                       PchTestUnlockUsbForSvNoa;
-
-/** Offset 0x0C91 - Enable XHCI Clock Gating for SV usage
-  1: Enable XHCI Clock Gating. 0: Disable XHCI Clock Gating. Policy for SV usage.
-  $EN_DIS
-**/
-  UINT8                       PchTestClkGatingXhci;
-
-/** Offset 0x0C92 - Restricted Cyclone Pcie Switch WA
-  Restricted Cyclone Pcie Switch WA.
-**/
-  UINT8                       PchTestCyclonePcieSwitchWA;
-
-/** Offset 0x0C93 - Restricted Pch Root Port
-  Restricted Pch Root Port.
-**/
-  UINT8                       PchTestPchRootPort;
-
-/** Offset 0x0C94
-**/
-  UINT8                       UnusedUpdSpace37[2];
-
-/** Offset 0x0C96 - Restricted Flash Lock Down
-  Restricted Flash Lock Down.
-**/
-  UINT8                       PchTestFlashLockDown;
-
-/** Offset 0x0C97
-**/
-  UINT8                       UnusedUpdSpace38[2];
-
-/** Offset 0x0C99 - PCH PMC ER Debug mode
-  Disable/Enable Energy Reporting Debug Mode.
-  $EN_DIS
-**/
-  UINT8                       TestPchPmErDebugMode;
-
-/** Offset 0x0C9A
-**/
-  UINT8                       UnusedUpdSpace39[2];
-
-/** Offset 0x0C9C - USB2/TS LDO Dynamic Shutdown
-  Enable/Disable USB2/TS LDO Dynamic Shutdown
-  0: POR, 1: force enable, 2: force disable
-**/
-  UINT8                       TestUsbTsLdoShutdown;
-
-/** Offset 0x0C9D - OPI PLL Power Gating
-  OPI PLL Power Gating.
-  0: POR, 1: force enable, 2: force disable
-**/
-  UINT8                       PchDmiTestOpiPllPowerGating;
-
-/** Offset 0x0C9E - HDA Power/Clock Gating (PGD/CGD)
-  Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
-  FORCE_ENABLE, 2: FORCE_DISABLE.
-  0: POR, 1: Force Enable, 2: Force Disable
-**/
-  UINT8                       PchHdaTestPowerClockGating;
-
-/** Offset 0x0C9F - CNVi BT Core
-  Enable/Disable CNVi BT Core. 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
-  0: POR, 1: Force Enable, 2: Force Disable
-**/
-  UINT8                       TestCnviBtCore;
-
-/** Offset 0x0CA0 - CNVi BT Wireless Charging 
-  Enable/Disable CNVi BT Wireless Charging. 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
-  0: POR, 1: Force Enable, 2: Force Disable
-**/
-  UINT8                       TestCnviBtWirelessCharging;
-
-/** Offset 0x0CA1 - CNVi WiFi LTR
-  Enable/Disable CNVi WiFi LTR. 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
-  0: POR, 1: Force Enable, 2: Force Disable
-**/
-  UINT8                       TestCnviWifiLtrEn;
-
-/** Offset 0x0CA2 - PCH Pm Latch events C10 exit
-  PCH Pm Latch events C10 exit Enable.
-  0: POR, 1: force enable, 2: force disable
-**/
-  UINT8                       TestPchPmLatchEventsC10Exit;
-
-/** Offset 0x0CA3 - CNVi LTE Coexistence
-  Enable/Disable MFUART2 connection for coexistence between LTE and Wi-Fi/BT. 0: PLATFORM_POR,
-  1: FORCE_ENABLE, 2: FORCE_DISABLE.
-  0: POR, 1: Force Enable, 2: Force Disable
-**/
-  UINT8                       TestCnviLteCoex;
-
-/** Offset 0x0CA4 - PCIE Allow L0s with Gen3
-  Allows PCH rootports to have both L0s and Gen3 speed enabled at the same time.
-  $EN_DIS
-**/
-  UINT8                       PcieAllowL0sWithGen3;
-
-/** Offset 0x0CA5 - CNVi BT Interface
-  This option configures BT device interface to either USB or UART
-  0:UART, 1:USB
-**/
-  UINT8                       TestCnviBtInterface;
-
-/** Offset 0x0CA6 - CNVi BT Uart Type
-  This is a test option which allows configuration of UART type for BT communication
-  0:Serial IO Uart0, 1:ISH Uart0, 2:Uart over external pads
-**/
-  UINT8                       TestCnviBtUartType;
-
-/** Offset 0x0CA7 - Enable/Disable DMI L1 entry disable mode 
-  Enable/Disable DMI L1 entry disable mode.
-**/
-  UINT8                       PcieRpTestDmiL1Edm[24];
-
-/** Offset 0x0CBF - PchSiliconRestrictedRsvd
-  Reserved for PCH Post-Mem Restricted
-  $EN_DIS
-**/
-  UINT8                       PchSiliconRestrictedRsvd[3];
-
-/** Offset 0x0CC2 - Si Config SvPolicyEnable.
-  Platform specific common policies that used by several silicon components. SvPolicyEnable.
-  $EN_DIS
-**/
-  UINT8                       SiSvPolicyEnable;
-
-/** Offset 0x0CC3 - Si Config HsleWorkaround
-  Enable/Disable HSLE model specific workarounds
-  $EN_DIS
-**/
-  UINT8                       HsleWorkaround;
-
-/** Offset 0x0CC4
-**/
-  UINT8                       ReservedFspsRestrictedUpd[4];
-} FSP_S_RESTRICTED_CONFIG;
-
 /** Fsp S UPD Configuration
 **/
 typedef struct {
@@ -4026,10 +3127,6 @@ typedef struct {
 
 /** Offset 0x0A80
 **/
-  FSP_S_RESTRICTED_CONFIG     FspsRestrictedConfig;
-
-/** Offset 0x0CC8
-**/
   UINT16                      UpdTerminator;
 } FSPS_UPD;