diff options
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h | 933 |
1 files changed, 15 insertions, 918 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h index ac660eba60..2a2412d8ff 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h @@ -1793,9 +1793,10 @@ typedef struct { UINT8 PchScsEmmcHs400DriverStrength; /** Offset 0x06FA - PCH SerialIo I2C Pads Termination - 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak - pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination - respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 + pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 + for I2C1, and so on. 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU **/ UINT8 PchSerialIoI2cPadsTermination[6]; @@ -2927,11 +2928,18 @@ typedef struct { **/ UINT8 C1StateUnDemotion; -/** Offset 0x08A2 - ReservedCpuPostMemTest +/** Offset 0x08A2 - CpuWakeUpTimer + Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased + to 180 seconds. 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 CpuWakeUpTimer; + +/** Offset 0x08A3 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[24]; + UINT8 ReservedCpuPostMemTest[23]; /** Offset 0x08BA - SgxSinitDataFromTpm SgxSinitDataFromTpm default values @@ -3080,16 +3088,9 @@ typedef struct { **/ UINT8 PchXhciOcLock; -/** Offset 0x0A61 - PCH USB Access Control setting - This policy option controls setting the Access Control (ACCTRL) bit in XHCC1 which - will lock write access to registers controlled by its functionality. - $EN_DIS +/** Offset 0x0A61 **/ - UINT8 PchXhciAcLock; - -/** Offset 0x0A62 -**/ - UINT8 UnusedUpdSpace26[16]; + UINT8 UnusedUpdSpace26[17]; /** Offset 0x0A72 - Skip POSTBOOT SAI This skip the Post Boot Sai programming. 0: Set Post Boot Sai; 1: Skip Post Boot Sai. @@ -3108,906 +3109,6 @@ typedef struct { UINT8 ReservedFspsTestUpd[12]; } FSP_S_TEST_CONFIG; -/** Fsp S Restricted Configuration -**/ -typedef struct { - -/** Offset 0x0A80 -**/ - UINT32 Signature; - -/** Offset 0x0A84 -**/ - UINT8 UnusedUpdSpace27; - -/** Offset 0x0A85 - Enable or disable GNA Error Check Disable Bit - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 TestGnaErrorCheckDis; - -/** Offset 0x0A86 - Enable or disable VT-d DmaPassThrough - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DmaPassThrough; - -/** Offset 0x0A87 - Enable or disable VT-d CCHit2pend - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 CCHit2pend; - -/** Offset 0x0A88 - Enable or disable VT-d ContextInvalidation - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 ContextInvalidation; - -/** Offset 0x0A89 - Enable or disable VT-d IotlbInvalidation - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 IotlbInvalidation; - -/** Offset 0x0A8A - Enable or disable VT-d ContextCacheDis - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 ContextCacheDis; - -/** Offset 0x0A8B - Enable or disable VT-d L1Disable - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 L1Disable; - -/** Offset 0x0A8C - Enable or disable VT-d L2Disable - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 L2Disable; - -/** Offset 0x0A8D - Enable or disable VT-d L3Disable - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 L3Disable; - -/** Offset 0x0A8E - Enable or disable VT-d L1Hit2PendDis - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 L1Hit2PendDis; - -/** Offset 0x0A8F - Enable or disable VT-d L3Hit2PendDis - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 L3Hit2PendDis; - -/** Offset 0x0A90 - Enable or disable VT-d InvQueueCohDis - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 InvQueueCohDis; - -/** Offset 0x0A91 - Enable or disable VT-d SuperPageCap - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 SuperPageCap; - -/** Offset 0x0A92 - Enable or disable VT-d QueueInvCapDis - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 QueueInvCapDis; - -/** Offset 0x0A93 - Enable or disable VT-d IntrRemapCapDis - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 TestIntrRemapCapDis; - -/** Offset 0x0A94 - Enable or disable VT-d SnoopControl - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 SnoopControl; - -/** Offset 0x0A95 - Enable or disable VT-d RemapReverseCtrl - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 RemapReverseCtrl; - -/** Offset 0x0A96 - Enable or disable VT-d SvPolicyEnable - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 VtdSvPolicyEnable; - -/** Offset 0x0A97 - Sa Graphics Pei Test Force Wake - Test Force Wake -**/ - UINT8 SaTestForceWake; - -/** Offset 0x0A98 - Sa Graphics Pei Test Gfx Pause - Test Gfx Pause -**/ - UINT8 SaTestGfxPause; - -/** Offset 0x0A99 - Sa Graphics Pei Test Graphics Freq Modify - Test Graphics Freq Modify -**/ - UINT8 SaTestGraphicsFreqModify; - -/** Offset 0x0A9A - Sa Graphics Pei Test PmLock - Test PmLock -**/ - UINT8 SaTestPmLock; - -/** Offset 0x0A9B - Sa Graphics Pei Test Pavp Heavy Mode - Test Pavp Heavy Mode -**/ - UINT8 SaTestPavpHeavyMode; - -/** Offset 0x0A9C - Sa Graphics Pei Test Dop ClockGating - Test Dop ClockGating -**/ - UINT8 SaTestDopClockGating; - -/** Offset 0x0A9D - Sa Graphics Pei Test Unsolicited Attack Override - Test Unsolicited Attack Override -**/ - UINT8 SaTestUnsolicitedAttackOverride; - -/** Offset 0x0A9E - Sa Graphics Pei Test WOPCM Support - Test WOPCM Support -**/ - UINT8 SaTestWOPCMSupport; - -/** Offset 0x0A9F - Sa Graphics Pei Test Pavp Asmf - Test Pavp Asmf -**/ - UINT8 SaTestPavpAsmf; - -/** Offset 0x0AA0 - Sa Graphics Pei Test Power Gating - Test Power Gating -**/ - UINT8 SaTestPowerGating; - -/** Offset 0x0AA1 - Sa Graphics Pei Test Unit Level ClockGating - Test Unit Level ClockGating -**/ - UINT8 SaTestUnitLevelClockGating; - -/** Offset 0x0AA2 - Sa Graphics Pei Test Auto TearDown - Test Auto TearDown -**/ - UINT8 SaTestAutoTearDown; - -/** Offset 0x0AA3 - Sa Graphics Pei Test Graphics Video Freq - Test Graphics Video Freq -**/ - UINT8 SaTestGraphicsVideoFreq; - -/** Offset 0x0AA4 - Sa Graphics Pei Test WOPCM Size - Test WOPCM Size -**/ - UINT8 SaTestWOPCMSize; - -/** Offset 0x0AA5 - Sa Graphics Pei Test Graphics Freq Req - Test Graphics Freq Req -**/ - UINT8 SaTestGraphicsFreqReq; - -/** Offset 0x0AA6 - Sa Test Peg Aspm L0s Aggression - Test Peg Aspm L0s Aggression -**/ - UINT8 SaTestPegAspmL0sAggression[4]; - -/** Offset 0x0AAA - Sa Clear CorrUnCorrErr Enable - Clear CorrUnCorrErr Enable - $EN_DIS -**/ - UINT8 SaClearCorrUnCorrErrEnable; - -/** Offset 0x0AAB - Sa SvPegArifen - SvPegArifen -**/ - UINT8 SaSvPegArifen[4]; - -/** Offset 0x0AAF - Sa Peg0 Completion Timeout - Peg0 Completion Timeout -**/ - UINT8 SaPeg0CompletionTimeout; - -/** Offset 0x0AB0 - Sa Peg1 Completion Timeout - Peg1 Completion Timeout -**/ - UINT8 SaPeg1CompletionTimeout; - -/** Offset 0x0AB1 - Sa Peg2 Completion Timeout - Peg2 Completion Timeout -**/ - UINT8 SaPeg2CompletionTimeout; - -/** Offset 0x0AB2 - Sa Peg3 Completion Timeout - Peg3 Completion Timeout -**/ - UINT8 SaPeg3CompletionTimeout; - -/** Offset 0x0AB3 - Sa Sv Peg Compliance Deemphasis - SvPegComplianceDeemphasis -**/ - UINT8 SaSvPegComplianceDeemphasis[4]; - -/** Offset 0x0AB7 - Sa Sv Peg TxLn Staggering Mode - SvPegTxLnStaggeringMode -**/ - UINT8 SaSvPegTxLnStaggeringMode[4]; - -/** Offset 0x0ABB - Sa Sv Peg TxLane Staggering Interval - SvPegTxLaneStaggeringInterval -**/ - UINT8 SaSvPegTxLaneStaggeringInterval[4]; - -/** Offset 0x0ABF - Sa Sv Peg RxLn Staggering Mode - SvPegRxLnStaggeringMode -**/ - UINT8 SaSvPegRxLnStaggeringMode[4]; - -/** Offset 0x0AC3 - Sa Sv Peg RxLane Staggering Interval - SvPegRxLaneStaggeringInterval -**/ - UINT8 SaSvPegRxLaneStaggeringInterval[4]; - -/** Offset 0x0AC7 - Sa Test MpllOffSen - TestMpllOffSen -**/ - UINT8 SaTestMpllOffSen; - -/** Offset 0x0AC8 - Sa Test MdllOffSen - TestMdllOffSen -**/ - UINT8 SaTestMdllOffSen; - -/** Offset 0x0AC9 - Sa Test Mode Edram Internal - Edram Enable Option -**/ - UINT8 SaTestModeEdramInternal; - -/** Offset 0x0ACA - Sa Test Security Lock - Enable/Disable Security lock -**/ - UINT8 SaTestSecurityLock; - -/** Offset 0x0ACB -**/ - UINT8 UnusedUpdSpace28[49]; - -/** Offset 0x0AFC - SaPostMemRestrictedRsvd - Reserved for SA Post-Mem Restricted - $EN_DIS -**/ - UINT8 SaPostMemRestrictedRsvd[22]; - -/** Offset 0x0B12 - CpuPostMemRestrictedRsvd - Reserved for CPU Post-Mem Restricted - $EN_DIS -**/ - UINT8 CpuPostMemRestrictedRsvd[16]; - -/** Offset 0x0B22 - BiosGuardModulePtr - BiosGuardModulePtr default values -**/ - UINT8 EnableSgx7a; - -/** Offset 0x0B23 - SgxDebugMode - SgxDebugMode default values -**/ - UINT8 SgxDebugMode; - -/** Offset 0x0B24 - SvLtEnable - SvLtEnable default values -**/ - UINT8 SvLtEnable; - -/** Offset 0x0B25 - SelectiveEnableSgx - SelectiveEnableSgx default values -**/ - UINT8 SelectiveEnableSgx; - -/** Offset 0x0B26 - EpcOffset - EpcOffset default values -**/ - UINT64 EpcOffset; - -/** Offset 0x0B2E - EpcLength - EpcLength default values -**/ - UINT64 EpcLength; - -/** Offset 0x0B36 - SgxLCP - SgxLCP default values -**/ - UINT8 SgxLCP; - -/** Offset 0x0B37 - EpcLength - EpcLength default values -**/ - UINT64 SgxLEPubKeyHash0; - -/** Offset 0x0B3F - EpcLength - EpcLength default values -**/ - UINT64 SgxLEPubKeyHash1; - -/** Offset 0x0B47 - EpcLength - EpcLength default values -**/ - UINT64 SgxLEPubKeyHash2; - -/** Offset 0x0B4F - EpcLength - EpcLength default values -**/ - UINT64 SgxLEPubKeyHash3; - -/** Offset 0x0B57 - CpuPostMemRestrictedRsvd - Reserved for CPU Post-Mem Restricted - $EN_DIS -**/ - UINT8 SecurityRestrictedRsvd[1]; - -/** Offset 0x0B58 - MEM CLOSED State on PCH side - Enable/Disable MEM CLOSED State on PCH side. - $EN_DIS -**/ - UINT8 PchDmiTestMemCloseStateEn; - -/** Offset 0x0B59 - Optimized Buffer Flush/Fill (OBFF) protocol for internal on PCH side - enable/disable Optimized Buffer Flush/Fill (OBFF) protocol for internal on PCH side. - $EN_DIS -**/ - UINT8 PchDmiTestInternalObffEn; - -/** Offset 0x0B5A - Determines if force extended transmission of FTS ordered sets - Determines if force extended transmission of FTS ordered sets when exiting L0s prior - to entering L0. -**/ - UINT8 PchDmiTestDmiExtSync; - -/** Offset 0x0B5B - Optimized Buffer Flush/Fill (OBFF) protocol for external on PCH side - Enable/Disable Optimized Buffer Flush/Fill (OBFF) protocol for external on PCH side. - $EN_DIS -**/ - UINT8 PchDmiTestExternalObffEn; - -/** Offset 0x0B5C - Client Obff Enable - Client Obff Enable. - $EN_DIS -**/ - UINT8 PchDmiTestClientObffEn; - -/** Offset 0x0B5D - CxObff Entry Delay - CxObff Entry Delay. -**/ - UINT8 PchDmiTestCxObffEntryDelay; - -/** Offset 0x0B5E -**/ - UINT8 UnusedUpdSpace29; - -/** Offset 0x0B5F - Pch Tc Lock Down - Pch Tc Lock Down. - $EN_DIS -**/ - UINT8 PchDmiTestPchTcLockDown; - -/** Offset 0x0B60 - Enable DMI ASPM after booting to OS - Enable DMI ASPM after booting to OS. - $EN_DIS -**/ - UINT8 PchDmiTestDelayEnDmiAspm; - -/** Offset 0x0B61 - Dmi Aspm Ctrl - Dmi Aspm Ctrl. - $EN_DIS -**/ - UINT8 PchDmiTestDmiAspmCtrl; - -/** Offset 0x0B62 - DMI Secure Reg Lock - DMI Secure Reg Lock. - 0: POR (Enable), 1: Enable, 2: Disable -**/ - UINT8 PchDmiTestDmiSecureRegLock; - -/** Offset 0x0B63 -**/ - UINT8 UnusedUpdSpace30; - -/** Offset 0x0B64 - Configuration Lockdown (BCLD) - 0: POR (Enable), 1: Enable, 2: Disable. - 0: POR (Enable), 1: Enable, 2: Disable -**/ - UINT8 PchHdaTestConfigLockdown; - -/** Offset 0x0B65 - Low Frequency Link Clock Source (LFLCS) - 0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL). - 0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL) -**/ - UINT8 PchHdaTestLowFreqLinkClkSrc; - -/** Offset 0x0B66 -**/ - UINT8 UnusedUpdSpace31[4]; - -/** Offset 0x0B6A - PCH Lan Test WOL Fast Support - Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm. - $EN_DIS -**/ - UINT8 PchLanTestPchWOLFastSupport; - -/** Offset 0x0B6B - Smi Unlock bit for SV policy - 0: Lock; 1: Unlock. - $EN_DIS -**/ - UINT8 PchLockDownTestSmiUnlock; - -/** Offset 0x0B6C - PchPostMemRestrictedRsvd - Reserved for PCH Post-Mem Restricted Reserved - $EN_DIS -**/ - UINT8 PchPostMemRestrictedRsvd[24]; - -/** Offset 0x0B84 - Gen3 EQ Phase2 Tx override - Coefficient requested by the remote device is ignored. -**/ - UINT8 PcieRpTestEqPh2Override[24]; - -/** Offset 0x0B9C - Tx preset to use when TestEqPh2Override is set - Tx preset to use when TestEqPh2Override is set. -**/ - UINT8 PcieRpTestEqPh2Preset[24]; - -/** Offset 0x0BB4 - Enable/Disable ASPM Optionality Compliance - Enable/Disable ASPM Optionality Compliance. -**/ - UINT8 PcieRpTestAspmOc[24]; - -/** Offset 0x0BCC - Force LTR Override - Force LTR Override. -**/ - UINT8 PcieRpTestForceLtrOverride[24]; - -/** Offset 0x0BE4 -**/ - UINT8 UnusedUpdSpace32[72]; - -/** Offset 0x0C2C - PCH Pcie bem - PCH Pcie bem. -**/ - UINT8 PcieTestPchPciebem; - -/** Offset 0x0C2D - PCH Pcie Test bem Port Index - PCH Pcie Test bem Port Index. -**/ - UINT8 PcieTestPchPciebemPortIndex; - -/** Offset 0x0C2E - PCH Test PcieRp dbc gen - PCH Test PcieRp dbc gen. -**/ - UINT8 PcieTestPchPcieRpdbcgen; - -/** Offset 0x0C2F - PCH Test PcieRp dlc gen - PCH Test PcieRp dlc gen. -**/ - UINT8 PcieTestPchPcieRpdlcgen; - -/** Offset 0x0C30 - PCH Test Pcie Dcgeisma - PCH Test Pcie Dcgeisma. -**/ - UINT8 PcieTestPchPcieDcgeisma; - -/** Offset 0x0C31 - PCH Test PcieRp scgen - PCH Test PcieRp scgen. -**/ - UINT8 PcieTestPchPcieRpscgen; - -/** Offset 0x0C32 - PCH Test Pcie Srdbcgen - PCH Test Pcie Srdbcgen. -**/ - UINT8 PcieTestPchPcieSrdbcgen; - -/** Offset 0x0C33 - PCH Test Pcie Scptcge - PCH Test Pcie Scptcge. -**/ - UINT8 PcieTestPchPcieScptcge; - -/** Offset 0x0C34 - PCH Test Pcie Fdppge - PCH Test Pcie Fdppge. -**/ - UINT8 PcieTestPchPcieFdppge; - -/** Offset 0x0C35 - PCH Test Pcie Phyclpge - PCH Test Pcie Phyclpge. -**/ - UINT8 PcieTestPchPciePhyclpge; - -/** Offset 0x0C36 - PCH Test Pcie Fdcpge - PCH Test Pcie Fdcpge. -**/ - UINT8 PcieTestPchPcieFdcpge; - -/** Offset 0x0C37 - PCH Test Pcie Detscpge - PCH Test Pcie Detscpge. -**/ - UINT8 PcieTestPchPcieDetscpge; - -/** Offset 0x0C38 - PCH Test Pcie L23 rdyscpge - PCH Test Pcie L23 rdyscpge. -**/ - UINT8 PcieTestPchPcieL23rdyscpge; - -/** Offset 0x0C39 - PCH Test Pcie Disscpge - PCH Test Pcie Disscpge. -**/ - UINT8 PcieTestPchPcieDisscpge; - -/** Offset 0x0C3A - PCH Test Pcie L1 scpge - PCH Test Pcie L1 scpge. -**/ - UINT8 PcieTestPchPcieL1scpge; - -/** Offset 0x0C3B - PCH Pcie Test Lane Eq En - PCH PcieTest Lane Eq En. -**/ - UINT8 PcieTestLaneEqEn; - -/** Offset 0x0C3C - PCH Pcie Test Sw Eq Override - PCH Pcie bem. -**/ - UINT8 PcieTestSwEqOverride; - -/** Offset 0x0C3D - PCH Pcie Test Sw Eq Dwell Time Us - PCH Pcie Test Sw Eq Dwell Time Us. -**/ - UINT16 PcieTestSwEqDwellTimeUs; - -/** Offset 0x0C3F - PCH Pcie Test Sw Eq Error Threshold - PCH Pcie Test Sw Eq Error Threshold. -**/ - UINT16 PcieTestSwEqErrorThreshold; - -/** Offset 0x0C41 - PCH Pcie Test Sw Eq Rec Threshold - PCH Pcie Test Sw Eq Rec Threshold. -**/ - UINT16 PcieTestSwEqRecThreshold; - -/** Offset 0x0C43 - PCH Pcie Test Sw Eq Retrain Timeout Ms - PCH Pcie Test Sw Eq Retrain Timeout Ms. -**/ - UINT16 PcieTestSwEqRetrainTimeoutMs; - -/** Offset 0x0C45 - PCH Pcie Test Sw Eq Recovery Wait - PCH Pcie Test Sw Eq Recovery Wait. -**/ - UINT16 PcieTestSwEqRecoveryWait; - -/** Offset 0x0C47 - PCH Pm Register Lock - PCH Pm Register Lock. -**/ - UINT8 PchPmTestPchPmRegisterLock; - -/** Offset 0x0C48 - PCH Pm Test SlpS0 CsMe PgQDis - CPPM VRIC CSME Power Gated Qualification Disable. -**/ - UINT8 PchPmTestSlpS0CsMePgQDis; - -/** Offset 0x0C49 - PCH Pm Test Slp S0 Gbe Disc QDis - CPPM VRIC GbE Disconnected Qualification Disable. -**/ - UINT8 PchPmTestSlpS0GbeDiscQDis; - -/** Offset 0x0C4A - PCH Pm Test Slp S0A Dsp D3 QDis - CPPM VRIC Audio DSP is in D3 Qualification Disable. -**/ - UINT8 PchPmTestSlpS0ADspD3QDis; - -/** Offset 0x0C4B - PCH Pm Test Slp S0 Xhci D3QDis - CPPM VRIC XHCI is in D3 Qualification Disable. -**/ - UINT8 PchPmTestSlpS0XhciD3QDis; - -/** Offset 0x0C4C - PCH Pm Test Slp S0 Lpio D3QDis - CPPM VRIC LPIO is in D3 Qualification Disable. -**/ - UINT8 PchPmTestSlpS0LpioD3QDis; - -/** Offset 0x0C4D - PCH Pm Test Slp S0 Icc Pll W BEn - CPPM VRIC ICC PLL Wake Block Enable. -**/ - UINT8 PchPmTestSlpS0IccPllWBEn; - -/** Offset 0x0C4E - PCH Pm Test Slp S0 PUGB En - PCH Pm CPPM VRIC Power Ungate Block Enable. -**/ - UINT8 PchPmTestSlpS0PUGBEn; - -/** Offset 0x0C4F - PCH Pm Test Clear Power Sts - @todo ADD DESCRIPTION. Policy for SV usage. NO USE.. -**/ - UINT8 PchPmTestPchClearPowerSts; - -/** Offset 0x0C50 - PCH Sata Test Rst Pcie Storage Test Mode - PCIe Storage remapping Test Mode to override existing PCIe Storage remapping POR - setting for development purpose. -**/ - UINT8 SataTestRstPcieStorageTestMode[3]; - -/** Offset 0x0C53 - PCH Sata Test Rst Pcie Storage Port Config Check - Enable/Disable Port Configuration Check for RST PCIe Storage Remapping. -**/ - UINT8 SataTestRstPcieStoragePortConfigCheck[3]; - -/** Offset 0x0C56 - PCH Sata Test Rst Pcie Storage Device Interface - Select the device interface (AHCI/NVME) for remapped device. NO USE. -**/ - UINT8 SataTestRstPcieStorageDeviceInterface[3]; - -/** Offset 0x0C59 - PCH Sata Test Rst Pcie Storage Device Bar Size Check - Enable/Disable Device BAR Size Check for remapped device. -**/ - UINT8 SataTestRstPcieStorageDeviceBarSizeCheck[3]; - -/** Offset 0x0C5C - PCH Sata Test Rst Pcie Storage Device Bar Select - Select the device BAR (BAR0-BAR5) that will be used for Remapping. -**/ - UINT8 SataTestRstPcieStorageDeviceBarSelect[3]; - -/** Offset 0x0C5F - PCH Sata Test Rst Pcie Storage Device Interrupt - Select the device interrupt (Legacy/MSIX) for remapped device. -**/ - UINT8 SataTestRstPcieStorageDeviceInterrupt[3]; - -/** Offset 0x0C62 - PCH Sata Test Rst Pcie Storage Aspm Programming - Enable/Disable ASPM Programming for remapped device. -**/ - UINT8 SataTestRstPcieStorageAspmProgramming[3]; - -/** Offset 0x0C65 - PCH Sata Test Rst Pcie Storage Save Restore - Enable/Disable ASPM Programming for remapped device. -**/ - UINT8 SataTestRstPcieStorageSaveRestore[3]; - -/** Offset 0x0C68 - Latency Tolerance Reporting Mechanism - Latency Tolerance Reporting Mechanism. -**/ - UINT8 SataTestLtrEnable; - -/** Offset 0x0C69 - Latency Tolerance Reporting Mechanism - Latency Tolerance Reporting Mechanism. -**/ - UINT8 SataTestLtrConfigLock; - -/** Offset 0x0C6A - Latency Tolerance Reporting Mechanism - Latency Tolerance Reporting Mechanism. -**/ - UINT8 SataTestLtrOverride; - -/** Offset 0x0C6B - Latency Tolerance Reporting Mechanism - Latency Tolerance Reporting Mechanism. -**/ - UINT8 SataTestSnoopLatencyOverrideMultiplier; - -/** Offset 0x0C6C - Latency Tolerance Reporting Mechanism - Latency Tolerance Reporting Mechanism. -**/ - UINT16 SataTestSnoopLatencyOverrideValue; - -/** Offset 0x0C6E - Latency Tolerance Reporting Mechanism - Latency Tolerance Reporting Mechanism. -**/ - UINT8 SataTestSataAssel; - -/** Offset 0x0C6F -**/ - UINT8 UnusedUpdSpace33[2]; - -/** Offset 0x0C71 - This locks down Enables the thermal sensor - 0: Disabled, 1: Enabled. - $EN_DIS -**/ - UINT8 PchTestTselLock; - -/** Offset 0x0C72 - This locks down Catastrophic Power-Down Enable and Catastrophic Trip Point Register - 0: Disabled, 1: Enabled. - $EN_DIS -**/ - UINT8 PchTestTscLock; - -/** Offset 0x0C73 - This locks down PHL and PHLC - 0: Disabled, 1: Enabled. - $EN_DIS -**/ - UINT8 PchTestPhlcLock; - -/** Offset 0x0C74 -**/ - UINT8 UnusedUpdSpace34[10]; - -/** Offset 0x0C7E - USB EP Type Lock Policy - USB EP Type Lock Policy. -**/ - UINT32 PchTestEPTypeLockPolicy; - -/** Offset 0x0C82 - USB EP Type Lock Policy Control 1 - USB EP Type Lock Policy Control 1. -**/ - UINT32 PchTestEPTypeLockPolicyPortControl1; - -/** Offset 0x0C86 - USB EP Type Lock Policy Control 2 - USB EP Type Lock Policy Control 2. -**/ - UINT32 PchTestEPTypeLockPolicyPortControl2; - -/** Offset 0x0C8A -**/ - UINT8 UnusedUpdSpace35[4]; - -/** Offset 0x0C8E - Xhci Controller Enable - 0: Disable; 1: Enable. -**/ - UINT8 PchTestControllerEnabled; - -/** Offset 0x0C8F -**/ - UINT8 UnusedUpdSpace36; - -/** Offset 0x0C90 - Unlock to enable NOA for SV usage - 1: Unlock to enable NOA usage. 0: Set Xhci OC registers, Set Xhci OCCDone bit, XHCI - Access Control Bit. - $EN_DIS -**/ - UINT8 PchTestUnlockUsbForSvNoa; - -/** Offset 0x0C91 - Enable XHCI Clock Gating for SV usage - 1: Enable XHCI Clock Gating. 0: Disable XHCI Clock Gating. Policy for SV usage. - $EN_DIS -**/ - UINT8 PchTestClkGatingXhci; - -/** Offset 0x0C92 - Restricted Cyclone Pcie Switch WA - Restricted Cyclone Pcie Switch WA. -**/ - UINT8 PchTestCyclonePcieSwitchWA; - -/** Offset 0x0C93 - Restricted Pch Root Port - Restricted Pch Root Port. -**/ - UINT8 PchTestPchRootPort; - -/** Offset 0x0C94 -**/ - UINT8 UnusedUpdSpace37[2]; - -/** Offset 0x0C96 - Restricted Flash Lock Down - Restricted Flash Lock Down. -**/ - UINT8 PchTestFlashLockDown; - -/** Offset 0x0C97 -**/ - UINT8 UnusedUpdSpace38[2]; - -/** Offset 0x0C99 - PCH PMC ER Debug mode - Disable/Enable Energy Reporting Debug Mode. - $EN_DIS -**/ - UINT8 TestPchPmErDebugMode; - -/** Offset 0x0C9A -**/ - UINT8 UnusedUpdSpace39[2]; - -/** Offset 0x0C9C - USB2/TS LDO Dynamic Shutdown - Enable/Disable USB2/TS LDO Dynamic Shutdown - 0: POR, 1: force enable, 2: force disable -**/ - UINT8 TestUsbTsLdoShutdown; - -/** Offset 0x0C9D - OPI PLL Power Gating - OPI PLL Power Gating. - 0: POR, 1: force enable, 2: force disable -**/ - UINT8 PchDmiTestOpiPllPowerGating; - -/** Offset 0x0C9E - HDA Power/Clock Gating (PGD/CGD) - Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: - FORCE_ENABLE, 2: FORCE_DISABLE. - 0: POR, 1: Force Enable, 2: Force Disable -**/ - UINT8 PchHdaTestPowerClockGating; - -/** Offset 0x0C9F - CNVi BT Core - Enable/Disable CNVi BT Core. 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE. - 0: POR, 1: Force Enable, 2: Force Disable -**/ - UINT8 TestCnviBtCore; - -/** Offset 0x0CA0 - CNVi BT Wireless Charging - Enable/Disable CNVi BT Wireless Charging. 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE. - 0: POR, 1: Force Enable, 2: Force Disable -**/ - UINT8 TestCnviBtWirelessCharging; - -/** Offset 0x0CA1 - CNVi WiFi LTR - Enable/Disable CNVi WiFi LTR. 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE. - 0: POR, 1: Force Enable, 2: Force Disable -**/ - UINT8 TestCnviWifiLtrEn; - -/** Offset 0x0CA2 - PCH Pm Latch events C10 exit - PCH Pm Latch events C10 exit Enable. - 0: POR, 1: force enable, 2: force disable -**/ - UINT8 TestPchPmLatchEventsC10Exit; - -/** Offset 0x0CA3 - CNVi LTE Coexistence - Enable/Disable MFUART2 connection for coexistence between LTE and Wi-Fi/BT. 0: PLATFORM_POR, - 1: FORCE_ENABLE, 2: FORCE_DISABLE. - 0: POR, 1: Force Enable, 2: Force Disable -**/ - UINT8 TestCnviLteCoex; - -/** Offset 0x0CA4 - PCIE Allow L0s with Gen3 - Allows PCH rootports to have both L0s and Gen3 speed enabled at the same time. - $EN_DIS -**/ - UINT8 PcieAllowL0sWithGen3; - -/** Offset 0x0CA5 - CNVi BT Interface - This option configures BT device interface to either USB or UART - 0:UART, 1:USB -**/ - UINT8 TestCnviBtInterface; - -/** Offset 0x0CA6 - CNVi BT Uart Type - This is a test option which allows configuration of UART type for BT communication - 0:Serial IO Uart0, 1:ISH Uart0, 2:Uart over external pads -**/ - UINT8 TestCnviBtUartType; - -/** Offset 0x0CA7 - Enable/Disable DMI L1 entry disable mode - Enable/Disable DMI L1 entry disable mode. -**/ - UINT8 PcieRpTestDmiL1Edm[24]; - -/** Offset 0x0CBF - PchSiliconRestrictedRsvd - Reserved for PCH Post-Mem Restricted - $EN_DIS -**/ - UINT8 PchSiliconRestrictedRsvd[3]; - -/** Offset 0x0CC2 - Si Config SvPolicyEnable. - Platform specific common policies that used by several silicon components. SvPolicyEnable. - $EN_DIS -**/ - UINT8 SiSvPolicyEnable; - -/** Offset 0x0CC3 - Si Config HsleWorkaround - Enable/Disable HSLE model specific workarounds - $EN_DIS -**/ - UINT8 HsleWorkaround; - -/** Offset 0x0CC4 -**/ - UINT8 ReservedFspsRestrictedUpd[4]; -} FSP_S_RESTRICTED_CONFIG; - /** Fsp S UPD Configuration **/ typedef struct { @@ -4026,10 +3127,6 @@ typedef struct { /** Offset 0x0A80 **/ - FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; - -/** Offset 0x0CC8 -**/ UINT16 UpdTerminator; } FSPS_UPD; |