diff options
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h | 717 |
1 files changed, 8 insertions, 709 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h index fe9933f7fb..dded50d383 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h @@ -2248,9 +2248,15 @@ typedef struct { **/ UINT8 RMTLoopCount; -/** Offset 0x0511 +/** Offset 0x0511 - BER Support + Enable/Disable the Rank Margin Tool interpolation/extrapolation. + 0:Disable, 1:Enable +**/ + UINT8 EnBER; + +/** Offset 0x0512 **/ - UINT8 ReservedFspmUpd[15]; + UINT8 ReservedFspmUpd[14]; } FSP_M_CONFIG; /** Fsp M Test Configuration @@ -2619,709 +2625,6 @@ typedef struct { UINT8 ReservedFspmTestUpd[11]; } FSP_M_TEST_CONFIG; -/** Fsp M Restricted Configuration -**/ -typedef struct { - -/** Offset 0x05B0 -**/ - UINT32 Signature; - -/** Offset 0x05B4 - Sa Sv Remap Base Override - SvRemapBaseOverride -**/ - UINT16 SaSvRemapBaseOverride; - -/** Offset 0x05B6 - Sa System Agent ClockGating Enable - SystemAgentClockGatingEnable -**/ - UINT8 SaSystemAgentClockGatingEnable; - -/** Offset 0x05B7 - Sa Pcie Pll Shutdown Enable - PciePllShutdownEnable -**/ - UINT8 SaPciePllShutdownEnable; - -/** Offset 0x05B8 - Sa SV_DMI_GEN1_halt - SV_DMI_GEN1_halt -**/ - UINT8 SaSV_DMI_GEN1_halt; - -/** Offset 0x05B9 - Sa SV_nFTS_DMI_auto - SV_nFTS_DMI_auto -**/ - UINT8 SaSV_nFTS_DMI_auto; - -/** Offset 0x05BA - Sa Sv DMI_nFTS - SvDMI_nFTS -**/ - UINT8 SaSvDMI_nFTS; - -/** Offset 0x05BB - Sa nFTS_auto - nFTS_auto -**/ - UINT8 SanFTS_auto; - -/** Offset 0x05BC - Sa SvPEG_nFTS - SvPEG_nFTS -**/ - UINT8 SaSvPEG_nFTS[4]; - -/** Offset 0x05C0 - Sa SvPEG_gen3_ccFTS - SvPEG_gen3_ccFTS -**/ - UINT8 SaSvPEG_gen3_ccFTS[4]; - -/** Offset 0x05C4 - Sa SvPEG_gen3_nccFTS - SvPEG_gen3_nccFTS -**/ - UINT8 SaSvPEG_gen3_nccFTS[4]; - -/** Offset 0x05C8 - Sa nFTS_gen3_auto - nFTS_gen3_auto -**/ - UINT8 SanFTS_gen3_auto; - -/** Offset 0x05C9 - Sa SVIAER - SVIAER -**/ - UINT8 SaSVIAER; - -/** Offset 0x05CA - Sa Sv Scrambler Dmi - SvScramblerDmi -**/ - UINT8 SaSvScramblerDmi; - -/** Offset 0x05CB -**/ - UINT8 UnusedUpdSpace9[1]; - -/** Offset 0x05CC - Sa Sv Scrambler Peg - SvScramblerPeg -**/ - UINT8 SaSvScramblerPeg[4]; - -/** Offset 0x05D0 - Sa Sv Dmi Serr - SvDmiSerr -**/ - UINT8 SaSvDmiSerr; - -/** Offset 0x05D1 -**/ - UINT8 UnusedUpdSpace10[3]; - -/** Offset 0x05D4 - Sa Sv Scrambler Peg Gen3 - SvScramblerPegGen3 -**/ - UINT8 SaSvScramblerPegGen3[4]; - -/** Offset 0x05D8 - Sa Sv Peg Serr - SvPegSerr -**/ - UINT8 SaSvPegSerr[4]; - -/** Offset 0x05DC - Sa Test Tx ClkGating - TestTxClkGating -**/ - UINT8 SaTestTxClkGating; - -/** Offset 0x05DD - Sa Test Rx ClkGating - TestRxClkGating -**/ - UINT8 SaTestRxClkGating; - -/** Offset 0x05DE - Sa Test Low Pwr Mode - TestLowPwrMode -**/ - UINT8 SaTestLowPwrMode; - -/** Offset 0x05DF - Sa Sr Mode - SrMode -**/ - UINT8 SaSrMode; - -/** Offset 0x05E0 - Sa Sr Seq - SrSeq -**/ - UINT8 SaSrSeq; - -/** Offset 0x05E1 - Sa Burst Spacing - BurstSpacing -**/ - UINT8 SaBurstSpacing; - -/** Offset 0x05E2 - SvPolicyEnable - Enable: SV policy is enabled, Disable(Default): SV policy is disabled - $EN_DIS -**/ - UINT8 SaRestrictedSvPolicyEnable; - -/** Offset 0x05E3 - Cpu Sv Boot Mode - 0: Auto (Default), 1: Commercial boot mode, 2: SV boot mode, 3: SV boot JTAG mode - with SB loop, 4: SV boot JTAG mode without SB loop - 0: Auto , 1: Commercial boot mode, 2: SV boot mode, 3: SV boot JTAG mode with SB - loop, 4: SV boot JTAG mode without SB loop -**/ - UINT8 SaCpuSvBootMode; - -/** Offset 0x05E4 - CpuSvBootMode - Enable: FlexCon is enabled, Disble(Default): FlexCon is disabled - $EN_DIS -**/ - UINT8 XmlCliEnable; - -/** Offset 0x05E5 - LoadValidationFv - Enable: Enable loading of ValidationFV, Disable(Default) - $EN_DIS -**/ - UINT8 LoadValidationFv; - -/** Offset 0x05E6 - SvReserveMemoryBelowPrmrr - Enable: Enable reserve SV memory below PMRR, Disable(Default) - $EN_DIS -**/ - UINT8 SvReserveMemoryBelowPrmrr; - -/** Offset 0x05E7 - Sa Test Sample Part Status Override - 0-Passthrough, 1-Production part, 2-Preproduction part -**/ - UINT8 SaTestSamplePartStatusOverride; - -/** Offset 0x05E8 - Sa Test Grunit ClockGating - Enable Sa Test Grunit ClockGating - $EN_DIS -**/ - UINT8 SaTestGrunitClockGating; - -/** Offset 0x05E9 - Sa Test Dmi Cap Reg Lock - DMI Capability Register Lock -**/ - UINT8 SaTestDmiCapRegLock; - -/** Offset 0x05EA - Sa Test Dmi Max Payload Size - DMI Max Payload Size -**/ - UINT8 SaTestDmiMaxPayloadSize; - -/** Offset 0x05EB - Sa Pcie VcLim Lock - Lock bit -**/ - UINT8 SaPcieVcLimLock; - -/** Offset 0x05EC - Sa Pcie VCm Cmp Lim - VCm Completions override -**/ - UINT8 SaPcieVCmCmpLim; - -/** Offset 0x05ED - Sa Pcie VCm PLim - posted VCm Requests override -**/ - UINT8 SaPcieVCmPLim; - -/** Offset 0x05EE - Sa Pcie VCm NpLim - non-posted VCm Requests override -**/ - UINT8 SaPcieVCmNpLim; - -/** Offset 0x05EF - Sa Laguna Credit WA - Laguna Credit WA -**/ - UINT8 SaLagunaCreditWA; - -/** Offset 0x05F0 - Sa Sv Dmi Compliance Deemphasis - SvDmiComplianceDeemphasis -**/ - UINT8 SaSvDmiComplianceDeemphasis; - -/** Offset 0x05F1 - Prefetch NonPrefetch Ratio - 0: All prefetch, 1: Seven of Eight Prefetch, 2: Three of Four Prefetch, 3: Half - Prefetch Half Non-Prefetch(Default), 4: Three of Four Non-Prefetch, 5: Seven of - Eight Prefetch, 6: All Non-prefetch - 0: All prefetch, 1: Seven of Eight Prefetch, 2: Three of Four Prefetch, 3: Half - Prefetch Half Non-Prefetch, 4: Three of Four Non-Prefetch, 5: Seven of Eight Prefetch, - 6: All Non-prefetch -**/ - UINT8 PrefetchNonPrefetchRatio; - -/** Offset 0x05F2 - SaPreMemRestrictedRsvd - Reserved for SA Pre-Mem Restricted - $EN_DIS -**/ - UINT8 SaPreMemRestrictedRsvd[30]; - -/** Offset 0x0610 - MSEG Size - MSEG Size. Valid values 0 : 512K , 1 : 1M , 2 : 1.5M , 3 : 2M , 4 : 2.4M , 5 : 3M - 0 : 512K , 1 : 1M , 2 : 1.5M , 3 : 2M , 4 : 2.4M , 5 : 3M -**/ - UINT64 MsegSize; - -/** Offset 0x0618 - Force TXT Enable - Force TXT Enable; 0: disable, 1: enable - $EN_DIS -**/ - UINT8 ForceTxtEnable; - -/** Offset 0x0619 - SaPreMemRestrictedRsvd - Reserved for SA Pre-Mem Restricted - $EN_DIS -**/ - UINT8 CpuPreMemRestrictedRsvd[23]; - -/** Offset 0x0630 - Dmi Test Tran Co Over En - Enable/Disable Lane Transmitter Coefficient. -**/ - UINT8 PchTestDmiTranCoOverEn[4]; - -/** Offset 0x0634 - Dmi Test Tran Co Over Post Cur - Lane Transmitter Post-Cursor Coefficient Override. -**/ - UINT8 PchTestDmiTranCoOverPostCur[4]; - -/** Offset 0x0638 - Dmi Test Tran Co Over Pre Cur - Lane Transmitter Pre-Cursor Coefficient Override. -**/ - UINT8 PchTestDmiTranCoOverPreCur[4]; - -/** Offset 0x063C - Dmi Test Up Port Tran Preset - Upstream Port Lane Transmitter Preset. -**/ - UINT8 PchTestDmiUpPortTranPreset[4]; - -/** Offset 0x0640 - Dmi Test UpPort Tran Preset En - 0: POR setting, 1: force enable, 2: force disable. -**/ - UINT8 PchTestDmiUpPortTranPresetEn; - -/** Offset 0x0641 - Dmi Test Rtlepceb - DMI Remote Transmit Link Equalization Preset/Coefficient Evaluation Bypass (RTLEPCEB). -**/ - UINT8 PchTestDmiRtlepceb; - -/** Offset 0x0642 - DMI ME UMA Root Space Check - DMI IOSF Root Space attribute check for RS3 for cycles targeting MEUMA. - 0: POR, 1: enable, 2: disable -**/ - UINT8 PchTestDmiMeUmaRootSpaceCheck; - -/** Offset 0x0643 - ModPhy Selection Policy - ModPhy Selection for ChipsetInitTable -**/ - UINT8 ModPhySelection; - -/** Offset 0x0644 - HECI Communication - Test, 0: POR, 1: enable, 2: disable, Disables HECI communication causing ME to enter - error state. - $EN_DIS -**/ - UINT8 HeciCommunication; - -/** Offset 0x0645 - HECI3 Interface Communication - Test, 0: POR, 1: enable, 2: disable, Adds or Removes HECI3 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication3; - -/** Offset 0x0646 - Notification test for Host Reset - Test, 0: POR, 1: enable, 2: disable, Enable test for notification when Host Reset - $EN_DIS -**/ - UINT8 HostResetNotification; - -/** Offset 0x0647 - Send Manufacturing Reset And Halt On S3 Resume - Test, 0: POR, 1: enable, 2: disable, Enable sending Manufacturing Reset and Halt - on S3 Resume - $EN_DIS -**/ - UINT8 ManufRstAndHaltOnS3Resume; - -/** Offset 0x0648 - Force Unlock AES - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 ForceUnlockAes; - -/** Offset 0x0649 - PreMemRestrictedRsvd2 - Reserved for Pre-Mem RestrictedReserved - $EN_DIS -**/ - UINT8 PreMemRestrictedRsvd2[23]; - -/** Offset 0x0660 - Asynchronous ODT - This option configures the Memory Controler Asynchronous ODT control - 0:Enabled, 1:Disabled -**/ - UINT8 AsyncOdtDis; - -/** Offset 0x0661 - Power Down Mode - This option controls command bus tristating during idle periods - 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto -**/ - UINT8 PowerDownMode; - -/** Offset 0x0662 - Time Measure - Time Measure: 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 MrcTimeMeasure; - -/** Offset 0x0663 - DLL Weak Lock Support - Enables/Disable DLL Weak Lock Support - $EN_DIS -**/ - UINT8 WeaklockEn; - -/** Offset 0x0664 - Fore 1 DPC config - Enables/Disable Fore 1 DPC config - $EN_DIS -**/ - UINT8 Force1Dpc; - -/** Offset 0x0665 - Fore Single Rank config - Enables/Disable Fore Single Rank config - $EN_DIS -**/ - UINT8 ForceSingleRank; - -/** Offset 0x0666 - SelfRefresh IdleTimer - SelfRefresh IdleTimer, Default is 512 -**/ - UINT16 SrefCfgIdleTmr; - -/** Offset 0x0668 - Strong Weak Leaker - Strong Weak Leaker value. 7=def -**/ - UINT8 StrongWkLeaker; - -/** Offset 0x0669 -**/ - UINT8 MrcRestrictedRsvd0x0669[1]; - -/** Offset 0x066A - Opportunistic Read - Enables/Disable Opportunistic Read (Def= Enable) - $EN_DIS -**/ - UINT8 OpportunisticRead; - -/** Offset 0x066B - Stacked Mode - Memory Stacked Mode Support (Def = Disable) - $EN_DIS -**/ - UINT8 MemStackMode; - -/** Offset 0x066C - Stacked Mode Ch Bit - Channel hash bit used during Stacked Mode(Def= BIT28) - 0:BIT28, 1:BIT29, 2:BIT30, 3:BIT31, 4:BIT32, 5:BIT33, 6:BIT34 -**/ - UINT8 StackModeChBit; - -/** Offset 0x066D - Low Memory Channel - Selecting which Physical Channel is mapped to low memory. - 0:Channel A, 1:Channel B -**/ - UINT8 LowMemChannel; - -/** Offset 0x066E - Cycle Bypass Support - Enables/Disable Cycle Bypass Support(Def=Disable) - $EN_DIS -**/ - UINT8 Disable2CycleBypass; - -/** Offset 0x066F - MC Register Offset - Apply user offsets to select MC registers(Def=Disable) - $EN_DIS -**/ - UINT8 MCREGOFFSET; - -/** Offset 0x0670 - CA Vref Ctl Offset - Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.CAVref - 0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0, - 13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11, - 24:+12, 0xFF:RANDOM -**/ - UINT8 CAVrefCtlOffset; - -/** Offset 0x0671 - Ch0 DQ Vref Ctrl Offset - Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch0VrefCtl - 0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0, - 13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11, - 24:+12, 0xFF:RANDOM -**/ - UINT8 Ch0VrefCtlOffset; - -/** Offset 0x0672 - Ch1 DQ Vref Ctrl Offset - Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch1VrefCtl - 0:-12,1:-11, 2:-10, 3:-9, 4:-8, 5:-7, 6:-6, 7:-5, 8:-4, 9:-3, 10:-2, 11:-1, 12:0, - 13:+1, 14:+2, 15:+3, 16:+4, 17:+5, 18:+6, 19:+7, 20:+8, 21:+9, 22:+10, 23:+11, - 24:+12, 0xFF:RANDOM -**/ - UINT8 Ch1VrefCtlOffset; - -/** Offset 0x0673 - Ch0 Clk PI Code Offset - Offset to be applied to DDRCLKCH0_CR_DDRCRCLKPICODE.PiSettingRank[0-3] - 0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM -**/ - UINT8 Ch0ClkPiCodeOffset; - -/** Offset 0x0674 - Ch1 Clk PI Code Offset - Offset to be applied to DDRCLKCH1_CR_DDRCRCLKPICODE.PiSettingRank[0-3] - 0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM -**/ - UINT8 Ch1ClkPiCodeOffset; - -/** Offset 0x0675 - Ch0 RcvEn Offset - Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RcvEn - 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM -**/ - UINT8 Ch0RcvEnOffset; - -/** Offset 0x0676 - Ch1 RcvEn Offset - Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.RcvEn - 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM -**/ - UINT8 Ch1RcvEnOffset; - -/** Offset 0x0677 - Ch0 Rx Dqs Offset - Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset - 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM -**/ - UINT8 Ch0RxDqsOffset; - -/** Offset 0x0678 - Ch1 Rx Dqs Offset - Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset - 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM -**/ - UINT8 Ch1RxDqsOffset; - -/** Offset 0x0679 - Ch0 Tx Dq Offset - Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset - 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM -**/ - UINT8 Ch0TxDqOffset; - -/** Offset 0x067A - Ch1 Tx Dq Offset - Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset - 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM -**/ - UINT8 Ch1TxDqOffset; - -/** Offset 0x067B - Ch0 Tx Dqs Offset - Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset - 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM -**/ - UINT8 Ch0TxDqsOffset; - -/** Offset 0x067C - Ch1 Tx Dqs Offset - Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset - 0:-3,1:-2, 2:-1, 3:0, 4:1, 5:2, 6:3, 0xFF:RANDOM -**/ - UINT8 Ch1TxDqsOffset; - -/** Offset 0x067D - Ch0 Vref Offset - Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset - 0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM -**/ - UINT8 Ch0VrefOffset; - -/** Offset 0x067E - Ch1 Vref Offset - Offset to be applied to DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN.VrefOffset - 0:-6,1:-5, 2:-4, 3:-3, 4:-2, 5:-1, 6:0, 7:1, 8:2, 9:3, 10:4, 11:5, 12:6, 0xFF:RANDOM -**/ - UINT8 Ch1VrefOffset; - -/** Offset 0x067F - tRRSG - Delay between Read-to-Read commands in the same Bank Group for DDR4 or Same Rank - for DDR3/LPDDR3. 0-Auto, Range 4-54. -**/ - UINT8 tRRSG; - -/** Offset 0x0680 - tRRDG - Delay between Read-to-Read commands in different Bank Group for DDR4 or Same Rank - for DDR3/LPDDR3. 0-Auto, Range 4-54. -**/ - UINT8 tRRDG; - -/** Offset 0x0681 - tRRDR - Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRRDR; - -/** Offset 0x0682 - tRRDD - Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRRDD; - -/** Offset 0x0683 - tWRSG - Delay between Write-to-Read commands in the same Bank Group for DDR4 or Same Rank - for DDR3/LPDDR3. 0-Auto, Range 4-86. -**/ - UINT8 tWRSG; - -/** Offset 0x0684 - tWRDG - Delay between Write-to-Read commands in different Bank Group for DDR4 or Same Rank - for DDR3/LPDDR3. 0-Auto, Range 4-54. -**/ - UINT8 tWRDG; - -/** Offset 0x0685 - tWRDR - Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWRDR; - -/** Offset 0x0686 - tWRDD - Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWRDD; - -/** Offset 0x0687 - tWWSG - Delay between Write-to-Write commands in the same Bank Group for DDR4 or Same Rank - for DDR3/LPDDR3. 0-Auto, Range 4-54. -**/ - UINT8 tWWSG; - -/** Offset 0x0688 - tWWDG - Delay between Write-to-Write commands in different Bank Group for DDR4 or Same Rank - for DDR3/LPDDR3. 0-Auto, Range 4-54. -**/ - UINT8 tWWDG; - -/** Offset 0x0689 - tWWDR - Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWWDR; - -/** Offset 0x068A - tWWDD - Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWWDD; - -/** Offset 0x068B - tRWSG - Delay between Read-to-Write commands in the same Bank Group for DDR4 or Same Rank - for DDR3/LPDDR3. 0-Auto, Range 4-54. -**/ - UINT8 tRWSG; - -/** Offset 0x068C - tRWDG - Delay between Read-to-Write commands in different Bank Group for DDR4 or Same Rank - for DDR3/LPDDR3. 0-Auto, Range 4-54. -**/ - UINT8 tRWDG; - -/** Offset 0x068D - tRWDR - Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRWDR; - -/** Offset 0x068E - tRWDD - Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRWDD; - -/** Offset 0x068F - DCTT Test - Select which test to run - 0:Basic walking memory test, 1:Row Hammer test -**/ - UINT8 DcttTest; - -/** Offset 0x0690 - DCTT: Iterations on Row - Number of repetitions on a Row -**/ - UINT8 DcttRhIterationOnRow; - -/** Offset 0x0691 - Page Close Delay Prompt - SubSequence Delay value used to ensure the page closes (In DClks) -**/ - UINT8 DcttRhPageCloseDelay; - -/** Offset 0x0692 - Row Hammer Refresh - Enable/Disables refreshes during the Row Hammer Test - $EN_DIS -**/ - UINT8 DcttRhRefreshEnable; - -/** Offset 0x0693 - Data Base - Select which data pattern that is used as the base pattern - 0:Zeros, 1:Ones, 2:Five, 3:A -**/ - UINT8 DcttDataBase; - -/** Offset 0x0694 - DCTT: Row Hammer Count - Number of Hammers for a given Row. -**/ - UINT32 DcttRhHammerCount; - -/** Offset 0x0698 - Row swizzle - Select which Row swizzle algorithm to use during Row Hammer test - 0:No Swizzle, 1:3xOr1_3xOr2, 2:01234567EFCDAB89 -**/ - UINT8 DcttRowSwizzleType; - -/** Offset 0x0699 - Refresh Multiplier - Multiplier applied to tREFI -**/ - UINT8 DcttRefreshMultiplier; - -/** Offset 0x069A - Bank Disable Mask - Bit Mask Bank Disable for per-Bank tests (Row Hammer) -**/ - UINT8 DcttBankDisableMask; - -/** Offset 0x069B - Clock Gate AB - Clock Gate AB - 0:Disable, 1:2 Cycles, 2:3 Cycles, 3:4 Cycles -**/ - UINT8 ScramClockGateAB; - -/** Offset 0x069C - Clock Gate C - Select which Row swizzle algorithm to use during Row Hammer test - 0:Disable, 1:2 Cycles, 2:4 Cycles, 3:8 Cycles -**/ - UINT8 ScramClockGateC; - -/** Offset 0x069D - Enable DBI AB - Enable DBI AB - $EN_DIS -**/ - UINT8 ScramEnableDbiAB; - -/** Offset 0x069E - MRC Interpreter - Select CMOS location match of DD01 or Ctrl-Break key or force entry - 0:CMOS, 1:Break, 2:Force -**/ - UINT8 Interpreter; - -/** Offset 0x069F - ODT mode - ODT mode - 0:Default, 1:Ctt, 2:Vtt, 3:Vddq, 4:Vss,5:Max -**/ - UINT8 IoOdtMode; - -/** Offset 0x06A0 - Lock DPR register - Lock DPR register. <b>0: Platform POR </b>; 1: Enable; 2: Disable - 0:Platform POR, 1: Enable, 2: Disable -**/ - UINT8 TestMenuDprLock; - -/** Offset 0x06A1 - PerBankRefresh - Control of Per Bank Refresh feature for LPDDR DRAMs - $EN_DIS -**/ - UINT8 PerBankRefresh; - -/** Offset 0x06A2 - Command Tristate - Enables/Disable Command Tristate - $EN_DIS -**/ - UINT8 CmdTriStateDis; - -/** Offset 0x06A3 -**/ - UINT8 MrcRestrictedRsvd[1]; - -/** Offset 0x06A4 -**/ - UINT8 ReservedFspmRestrictedUpd[26]; -} FSP_M_RESTRICTED_CONFIG; - /** Fsp M UPD Configuration **/ typedef struct { @@ -3344,10 +2647,6 @@ typedef struct { /** Offset 0x05B0 **/ - FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; - -/** Offset 0x06BE -**/ UINT16 UpdTerminator; } FSPM_UPD; |