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2022-05-16mb/google/nissa/var/nivviks: Update GPIOs to support nirwenReka Norman
Nirwen is an additional nissa reference board which is almost identical to nivviks, so is reusing the nivviks coreboot variant. However, there are two GPIO changes, so update the GPIO tables to handle these based on board_id. nivviks: GPP_D6 -> WWAN_EN GPP_E13 -> NC nirwen: GPP_D6 -> SSD_CLKREQ_ODL GPP_E13 -> WWAN_EN BUG=b:218929856 TEST=Boot to OS on nivviks Change-Id: I494ed127714069a8f36d16d11ca4e8a1f3d37827 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/nissa/var/nivviks: Disable pen garage based on fw_configReka Norman
BUG=b:218929856 TEST=Boot to OS on nivviks. Set fw_config in CBI and check that pen garage is enabled/disabled as expected. Change-Id: I2c3f5403e0f11443ad3647b8c4ae624f0b88a111 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/nissa/var/nivviks: Disable MIPI WFC based on fw_configReka Norman
BUG=b:218929856 TEST=Boot to OS on nivviks. Change fw_config in CBI and check that WFC is enabled/disabled as expected. Change-Id: Iac4bb358d904579376e0810f8c2644b3bde4f1e6 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/brya: Remove Rcomp resistors override for NissaUsha P
This patch sets the RComp resistor values to default values needed. BUG=b:231202733 TEST=Build and boot nivviks and nereid. Verify the Rcomp values are set to default values from debug FSP log. [SPEW ] Updating Rcomp Targets: [SPEW ] RcompTarget[RdOdt]: 48 [SPEW ] RcompTarget[WrDS]: 30 [SPEW ] RcompTarget[WrDSCmd]: 20 [SPEW ] RcompTarget[WrDSCtl]: 20 [SPEW ] RcompTarget[WrDSClk]: 20 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I2c7a54c49e282446ece77ca406951782282a009a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16mb/google/brya/var/crota: Enable DRIVERS_GENESYSLOGIC_GL9750Terry Chen
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Crota. BUG=b:231686917 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ie10167e48256a61801b2623ae4500db5e67e73cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16arch/x86/null_breakpoint: Remove handler before jumping to payloadArthur Heymans
If a payload did any NULL dereferencing it would be broken and jump back to coreboot code. This fixes the SeaBIOS, FILO and possibly other payloads too. Fixes: 3f01cd14533f ("arch/x86: Add support for catching null dereferences through debug regs") TESTED on qemu/i440fx. Change-Id: I80f69b71f4d0fab3126e4b9f8c8dc7737b372174 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64345 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Stefan Ott <coreboot@desire.ch> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16intelblocks: Add function to program GPE_EN before GPIO lockingMaulik V Vaghela
Since coreboot locks GPIO registers after GPIO configuration, OS is not able to program GPE_EN register to program wake events. This causes the issue of event not getting logged into event log (since GPE_EN bit is not set). GPE_EN register programming is required for the GPIO pins which are capable of generating SCI for the system wake. Elog mechanism relies on GPE_EN and GPE_STS bit to log correct wake signal. This patch add supports to program GPE_EN register before coreboot locks the GPIO registers. Note that coreboot will only program GPE_EN bits for GPIO capable of generating SCI. This will help resolve issue where we don't see wake event GPIO in event log. BUG=b:222375516 BRANCH=firmware-brya-14505.B TEST=Compile code for Brya and see GPE_EN bits set from the kernel console Change-Id: I27e525f50c374c2cc9675e77eaa7774683a6e7c2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16soc/inte/*/gpio; Add GPE_EN and GPE_STS register definitionMaulik V Vaghela
coreboot needs to set GPE_EN bit for the GPIOs which are wake capable from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not be able to write GPE_EN register post GPIO has been locked. This patch adds support in SoC code to provide correct offset for GPE_EN and GPE_STS registers to the common code. Plan is to use this offsets to set GPE_EN bits before GPIO locking in coreboot which will be part of subsequent CL. BUG=b:222375516 BRANCH=firmware-brya-14505.B TEST=Check if code compiles for Brya and correct offset values are printed. Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/crota: Change ELAN touchscreen i2c address and HIDTerry Chen
Change ELAN touchscreen i2c address to 0x16 and change HID to ELAN900C BUG=b:231684121 TEST=local build and tested with ELAN touch screen Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ide005a0681e236c3102090c1c36ab81926849000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16mb/google/nissa/var/nivviks: Disable SD card based on fw_configReka Norman
BUG=b:218929856 TEST=Boot to OS on nivviks. Change fw_config in CBI and check that SD card is enabled/disabled as expected. Change-Id: Idcf38343bb290b1eff6a2e440f868b03acba3288 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16drivers/i2c/tpm: Work around missing firmware_version in Ti50 < 0.0.15Reka Norman
Ti50 firmware versions below 0.0.15 don't support the firmware_version register and trying to access it causes I2C errors. Some nissa boards are still using Ti50 0.0.12, so add a workaround Kconfig to skip reading the firmware version and select it for nissa. The firmware version is only read to print it to the console, so it's fine to skip this. This workaround will be removed once all ODM stocks are updated to 0.0.15 or higher. A similar workaround Kconfig was added in CB:63011 then removed in CB:63158 which added support for separate handling of Cr50 and Ti50. But we actually still need this workaround until all Ti50 stocks are upgraded to 0.0.15 or higher. BUG=b:224650720 TEST=Boot to OS on nereid with Ti50 0.0.14 Change-Id: Ia30d44ac231c42eba3ffb1cb1e6d83bb6593f926 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-16mb/google/nissa/var/nivviks: Use interrupt with lock for pen detect GPIOEric Lai
With GPIO_DRIVER_LOCK kernel driver can't change to IRQ. Thus, we need to set it as INT in coreboot to make the IRQ work. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16soc/intel/common: Use mp_run_on_all_cpus_synchronously for APs MTRR initKane Chen
By using mp_run_on_all_cpus_synchronously to run APs MTRR init, it gurantees the BSP will run post_cpus_add_romcache until all APs finishes _x86_setup_mtrrs task. BUG=b:225766934 TEST=Test on redrix and found the MTRR race condition on AP/BSP is gone. Change-Id: I1fd889f880a0c605e6c739423a434d2adbc12d26 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16cpu/x86/mp_init.c: Add mp_run_on_all_cpus_synchronouslyKane Chen
MTRR is a core level register which means 2 threads in one core share same MTRR. There is a race condition could happen that AP overrides BSP MTRR unintentionally. In order to prevent such race condition between BSP and APs, this patch provides a function to let BSP assign tasks to all APs and wait them to complete the assigned tasks. BUG=b:225766934 Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63566 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16soc/intel/common/block/smbus: Add smbus block read write functionsShelly Chang
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com> Change-Id: Ib795f25abe5bbd95555b68af39c637d7c93aa819 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64251 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16soc/amd/picasso/acpi: Change GPIO controller interrupt to sharedRaul E Rangel
This change matches what we already do for cezanne. It will allow the GPIO controller to work correctly in windows. BUG=b:175146875 TEST=Boot windows and verify GPIO controller binds correctly and touch screen works. Also boot linux and verify touchpad still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I998e286de18d3e3f8b2fe610d17aef94a6cf5477 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-05-16mb/amd/chausie/devicetree: add USB PHY configurationFelix Held
Specify the USB PHY settings in the devicetree instead of relying on the FSP defaults. The USB PHY configuration for Chausie are taken from the internal UEFI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cc38e6e26d53802773fe3c405415de15cca98a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16mb/lenovo/t60: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad T60 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Change-Id: I47f878533d36857d002d2e2605cc8bc7e1d960c9 Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-16lib/spd: Demote log about using default DDR4 params to NOTICEEric Lai
Demote log level from error to notice. People should aware the SPD decode might be wrong if it's not the support type. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I55f0968b78baaa2fc9a6bbebf6712fb8bfd349f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16sb/amd/agesa/hudson/hudson.c: Use BIT() macrosElyes Haouas
Also, code reformatting to reduce coding style difference. Change-Id: I488050a6ab852520734b16032af9a683a3ad1a46 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16sb/amd/*/*/acpi: Reduce stylistic differencesElyes Haouas
Change-Id: I1375b1d18113000b31266030fd7115e23d7cce5f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16northbridge/intel/i945: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Iea9630ce7e5bfcc9d1c8699a81bd1c61a0705de8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h: Correct SPD_PERSONALITY_BYTEElyes Haouas
Regarding Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules DDR3 - Document Release 6 (JEDEC Standard No. 21-C Page 4.1.2.11 – 69) memory buffer personality bytes is located at bytes 102 ~ 116. Change-Id: I7d225fb5e80b537b4c0ce1c23b7a4524e9109a7b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16cpu/amd: Remove unused <cpu/x86/pae.h>Elyes Haouas
Found using: diff <(git grep -l '#include <cpu/x86/pae.h>' -- src/) <(git grep -l 'memset_pae\|MEMSET_PAE_\|MAPPING_ERROR\|map_2M_page\|paging_identity_map_addr\|paging_enable_for_car\|paging_set_default_pat\|paging_set_pat\|PAT_ENCODE\|PAT_UC_MINUS\|PAT_WB\|PAT_WP\|PAT_WT\|PAT_WC\|PAT_UC\|paging_set_nxe\|paging_disable_pae\|paging_enable_pae\|paging_enable_pae_cr3' -- src/) Change-Id: I4cab4b66c3d123dbb8a948a5596aa4975b31139b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16soc/intel/apollolake/romstage.c: Remove unused <cpu/x86/pae.h>Elyes Haouas
Found using: diff <(git grep -l '#include <cpu/x86/pae.h>' -- src/) <(git grep -l 'memset_pae\|MEMSET_PAE_\|MAPPING_ERROR\|map_2M_page\|paging_identity_map_addr\|paging_enable_for_car\|paging_set_default_pat\|paging_set_pat\|PAT_ENCODE\|PAT_UC_MINUS\|PAT_WB\|PAT_WP\|PAT_WT\|PAT_WC\|PAT_UC\|paging_set_nxe\|paging_disable_pae\|paging_enable_pae\|paging_enable_pae_cr3' -- src/) Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If0f69fa8fe4a336b4e4d2a148d1e7a911af3c2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16src: Remove unused <cf9_reset.h>Elyes Haouas
Found using: diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<" Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16mb/{google,ocp}: Remove unused <bootstate.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id4550842a31f89e7eb6c1543512794eeb5e24937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16soc/intel: Remove unused <cpu/intel/common/common.h>Elyes HAOUAS
Change-Id: I25d112941db8214a7e450de5fb512ef8c2c5f5e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16soc/intel: Remove unused <cpu/x86/tsc.h>Elyes HAOUAS
Change-Id: I322a94186b92033fc27ba97785b55df09aa317f7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16mb/google/stout: Use pci_update_config32()Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie1d2965b384e5653958f7f8503c62b8a16fa7bc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16mainboard/amd/padmelon: Use pci_or_config32()Elyes Haouas
Change-Id: I8d55fc93f6ec413d0cbcea2f8e0a90a76f1803cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-15soc/intel/alderlake: Move array declarationArthur Heymans
Clang does not like array declarations inside plain switch cases. There are 2 options to fix this: use a block inside the switch statement, or declare it outside the switch statement. This does the latter. Change-Id: I9a02136fd63ac171b2bec4647c30c7eece930246 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-15soc/intel/apl: Drop cbfs bootblockArthur Heymans
The bootblock is loaded from IFWI so there is no need to have it in cbfs. Also remove the FIT handling as that is also handled by the IFWI. TESTED: up/squared still boots Change-Id: I8e70e080765dd7306074a8cf71c8795b8fbbb8a2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63225 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-14soc/intel/acpi_bert.c: Fix formatted print type for size_tArthur Heymans
Change-Id: I2b02bcecda2257f191c0d0fc9935b1eb673ab3d2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-14mb/google/eldrid: Fix use of floatArthur Heymans
Floats are not allowed in coreboot. As the compiler rounded down the value, do so in the code too as this is a known good value. Change-Id: I4e180d4cb8e0e1aa68186bfc1daffdc5c339dc64 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-14soc/intel/alderlake: Fix Coverity CID 1488814Tarun Tuli
CID 1488814:  Uninitialized variables  (UNINIT) Commit c66ea98 introduced an issue after static analysis on merge. Because every APIC is associated with a CPU, this did not result in any issues at runtime but should be fixed/cleaned up. Now, the path name is initialized to null. Fixes: Coverity CID 1488814, commit c66ea98 TEST=Built on brya Change-Id: I0cfc8fd7a0c39e6610a9361630e3755293084f3d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-13mb/google/brya/variants/osiris: Init devicetree for osirisDavid Wu
Init basic override devicetree based on schematics BUG=b:224423318 TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie69957b39b5c299846c64f67fb29207cf858e50e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64199 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13mb/google/brya/variants/osiris: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for osiris BUG=b:224423318 TEST=FW_NAME=osiris emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I014bd7ebf94bf687362f7ee734cadfa83f3bde2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-05-13vendorcode/google/sar.c: Fix formatted print of size_tArthur Heymans
Change-Id: If765f492befd9d08b5fe9e98c887bcf24ce1a7db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-13soc/intel/xeon_sp: Remove set but unused variableArthur Heymans
Change-Id: I3c8c1787c77ed08942c6550ca556875904be2fa2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64242 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13soc/intel/xeon_sp/skx: Use correct formatted print for size_tArthur Heymans
Change-Id: I2acad0763d19b50c02472dfdd33084acbafe4c84 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-13mb/google/glados: Fix unused variableArthur Heymans
Commit f89cb241eec introduced a regression where the RcompTarget was not updated according to the SPD. Change-Id: I07715224b11937604b107e370d957745b245ddd9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64239 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13soc/intel/alderlake: Use correct formatted print for size_tArthur Heymans
Change-Id: Ifc0374ed49ecefc57dec8e72e73bac031838a9f5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64238 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13soc/intel/block/crashlog: Remove unused variableArthur Heymans
Change-Id: I2f89d11c163f56163d5c361a3edad14418bf9fa7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-13nb/intel/snb/raminit_mrc.c: Remove set but unused variableArthur Heymans
Change-Id: I1cf656b404b0e880c061b273ef259ca40a6d499a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-13soc/intel/denverton_ns: Remove always false statementArthur Heymans
This fixes building with clang. Change-Id: I7405f031298a35589e435e888af911d916662d23 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63069 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13soc/intel/tigerlake/meminit.c: Fix clang static assertsArthur Heymans
Clang does not like static asserts on integral constant expressions. Change-Id: If5890a357ed95153d8ae2efa727c111b05bc6455 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-13drivers/intel/fsp1_1: Use C over CPPArthur Heymans
This fixes building with clang. Change-Id: Ida464d9ff96af3ff485682fbbf904bb2253ec44f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-13Kconfig: Have CONFIG_ASAN depend on COMPILER_GCCArthur Heymans
-fsanitize=kernel-address is not implemented in clang Change-Id: Ib8660bf99b940ff9eac7461f5946df0891dd3a4f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-13nb/intel/gm45: Enable 64bit supportArthur Heymans
This patch does the following: - Allow selecting 64bit from Kconfig - Fix up integer to pointer conversion that gcc complains about - Add a buildtest target in configs Tested on Thinkpad X200: boots fine to the payload Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-13nb/intel/gm45/iommu.c: Fix clearing GTTArthur Heymans
This was dead code as it was checking for the wrong bit (bit 11 indicates the use of shadow GTT). It was doing it at the wrong place regardless as no BARs are set up. Move the code clearing GTT into the GMA .init code and do it unconditionally: if the GTT does not match 2M then the cycles are simply not decoded. Tested on thinkpad X200. Change-Id: Iac3264d484e66e9ca4b3cd3df90ad87a476e31ce Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-13nb/intel/gm45/dsdt: Fix number of PCI bussesArthur Heymans
Linux complained that the numbers in DSDT (256) don't match with the values in MMCONF (64). Change-Id: I2ccac64934e8d284e68945f86ec46cb2bf896277 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-13nb/intel/gm45: Allow for PCI BARs above 4GArthur Heymans
Linux needs to know that allocating BARs above 4G is fine so reserve a region in ACPI for that. Tested on thinkpad X200: a PCIe window gets allocated above 4G and Linux does not relocate it. Change-Id: I62a8a656481eba01add3d7d06b42e3352206df1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-12mb/google/skyrim: allow MKBP devices and disable TBMC deviceIan Feng
Enable MKBP (Matrix Keyboard Protocol) interface for all skyrim family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:230682161 TEST=manual test on Skyrim: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I79ee2fdbb325491c9e3df5b9cff0c0c1181a7001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-05-12soc/intel/alderlake: provide a list of D-states to enter LPMTarun Tuli
Implement sub-function 1 (Get Device Constraints) of the Low Power S0 Idle Device-Specific Method (_DSM). This provides a way in which to describe various devices required D-states to enter LPM (S0ix). The information can be used to help in diagnostics and understanding of S0ix entry failure. Values were derived from Intel document 595644 (rev 0.45) and the ADL FSP sample ASL. This implementation adds support for ADL. Other SoC's could be ported to be included as well. If they aren't, they will default to the existing behavior of a single hardcoded device to ensure compatibility with Windows. TEST=Built and tested on brya by verifying SSDT contents Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
2022-05-12mb/google/deltaur: Remove mainboard from treeTim Wawrzynczak
This board never made it to production, and development on it has long since stopped; it is a maintenance burden, therefore drop it from the tree. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ieb12a95ff56c3437cb88df8ef3f6ae115ad53446 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-12soc/amd/sabrina/fsp_m_params: fix modification of constantFred Reitberger
mcfg->usb_phy is a pointer to a struct usb_phy_config. The config is constant. Changing a constant is undefined behavior, so create a local static instance of usb_phy_config that can be modified safely. Change-Id: Iedbc49109dcd1da9198fcb2a8f84e2b567cd8f86 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64130 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12vc/amd/fsp/sabrina/UsbUpd: update USB settings structure to match FSPFelix Held
This file started as a copy from Cezanne. Sabrina has less USB ports than Cezanne. Also the struct definition of fch_usb2_phy has changed and FSP_USB_STRUCT_MINOR_VERSION is also updated. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ef2b62373b178d729b3230d0d8539986cc631ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/64129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-12soc/amd/sabrina/fsp_m_params: add defines for FSP USB struct versionFelix Held
Add and use defines instead of magic values in fsp_m_params.c. The values will be updated to match the Sabrina FSP in a follow-up commit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I91da9e9d2b95e169dd73153766f24cf8afbfa4ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/64128 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12soc/amd/sabrina/fsp_m_params: don't hard-code USB PHY config table sizeFelix Held
Use sizeof instead of having a hard-coded struct length. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3c39d770a7719e30572e71b6a6c24fa2ad4a9426 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-12mb/google/corsola: Enable TPM_GOOGLE_TI50Yu-Ping Wu
Replace TPM_GOOGLE_CR50 with TPM_GOOGLE_TI50. BUG=b:232066387 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I0cc787b3104bc47f6f856497bbc0870e0519dc28 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64252 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12mb/google/skyrim/var/skyrim: Add USB WWAN configurationKarthikeyan Ramasubramanian
Add Fibcom FM101-GL USB WWAN configuration with the required power sequence as suggested in Fibocom FM101-GL Hardware Guide V1.0. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the WWAN module is enumerated in the output of lsusb. localhost ~ # lsusb Bus 004 Device 003: ID 2cb7:01a2 Fibocom Wireless Inc. Fibocom FM101-GL Module Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I39f8e7204e31d9a4d093aacd838a18e6d2f44970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64004 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12mb/google/skyrim/var/skyrim: Add VL822 USB hubKarthikeyan Ramasubramanian
In Skyrim, USB-A port and WWAN modules are connected to the SoC USB ports through an external hub. Update the USB configuration in the devicetree accordingly. Enable the ACPI driver for external USB hub. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the hub and USB-A ports are enumerated correctly in the output of lusub command. Change-Id: Ibf6a3da8add7361fc50adcf7c62e46df234685dc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63586 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12drivers/usb: Add chip driver for external USB hubKarthikeyan Ramasubramanian
Add chip driver for soldered down external USB hub. This driver adds ACPI objects for the hub and any downstream facing ports. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the hub and any configured ports have ACPI devices defined in SSDT. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I11d7ccc42d3dce8e136eb771f120825980e5c027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63968 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12mb/google/brask/variants/moli: Set GPP_E14 as the default value.Raihow Shi
We found HDMI-DDIA didn't get hot plug detection,so set GPP_E14 as the default value to let HDMI-DDIA get hot plug detection. BUG=b:231769129 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I1b5cc1465fec519be4bbe5e027be0dc25815f4fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/64138 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12mb/google/nissa/var/craask: Add supported touchpadTyler Wang
Add related settings for synaptics touchpad. BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3b3bb5cec56901dadaaa1c5699781df45c237257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-12include/memory_info.h: Increase DIMM_INFO_TOTAL to 32Johnny Lin
For multiple sockets platform 16 may not be enough, so increase it to 32. Tested=On a platform that has more than 16 memory DIMM, SMBIOS type 17 can show all DIMM tables. Change-Id: If72a8622ac1e7e67646aa4dd24b99637fb8b1297 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: lichenchen.carl <lichenchen.carl@bytedance.com>
2022-05-12mb/starlabs/labtop: Enable Max Charge for CMLSean Rhodes
Enable the max charge feature for cml, as the EC supports it since Star Labs EC firmware 1.06. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I779a686960b63025fb5f40e826ed117f402a0b2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64093 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12ec/starlabs/merlin: Remove offset for Max Charge when not supportedSean Rhodes
Set the MAX_CHARGE offset to dead_code_t for boards that don't support the function. The avoids erroneous values being written to the EC. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I306c8a60818b780ef3bfb842e7fcc4d8500d6b03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-12mb/google/brya/var/agah: Enable PCIe RP 3 for LANTony Huang
Using CLKREQ 4 and CLKSRC 4 BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: Ie0e362013551036a03ef69a98c6f1793e0e75c41 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-12arch/x86: Add support for catching null dereferences through debug regsRobert Zieba
This commit adds support for catching null dereferences and execution through x86's debug registers. This is particularly useful when running 32-bit coreboot as paging is not enabled to catch these through page faults. This commit adds three new configs to support this feature: DEBUG_HW_BREAKPOINTS, DEBUG_NULL_DEREF_BREAKPOINTS and DEBUG_NULL_DEREF_HALT. BUG=b:223902046 TEST=Ran on nipperkin device, verifying that HW breakpoints work as expected. Change-Id: I113590689046a13c2a552741bbfe7668a834354a Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-12soc/amd/non-car: Don't add bootblock cbfs fileArthur Heymans
The bootblock.elf file gets embedded in the BIOSPSP part and loaded by the PSP in dram. The top aligned bootblock in cbfs is unused. Tested on Cezanne/Guybrush. Change-Id: I72f0092e0e3628b388f6da6a417c2857a510b187 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-12soc/intel/apl: Write to cbfs regions using intermediate targetsArthur Heymans
This also adds messages when adding the files. Change-Id: Ie812084cc243a18cbc2913804ef2190dd9d6ed9b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-12security/intel/cbnt/Makefile.inc: Improve build flowArthur Heymans
Using 'files_added::' is no longer needed as all files have already been added to the build. This has the advantage of showing all final entries in the FIT table and CBFS during the build process as adding the bpm to cbfs and fit is moved earlier. Change-Id: I22aa140202f0665b7095a01cb138af4986aa9ac3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-12soc/intel/common/block/fast_spi/Makefile.inc: Improve cosmeticsArthur Heymans
Change-Id: I41bbdabf7b846386651e64f4afb5b7b9fb38e1cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-12soc/amd/*/Makefile.inc: Do some cosmeticsArthur Heymans
The first target for the add_intermediate targets is always $(obj)/coreboot.pre. Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-12Kconfig: Add an option to skip adding a cbfs bootblock on x86Arthur Heymans
Some targets don't need this as the bootblock is loaded differently. Change-Id: Ia42448f7e9dd0635c72857fbc1fab54508932721 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-12Makefile.inc: Add x86 bootblock as a separate targetArthur Heymans
Some platforms don't need a top aligned bootblock in cbfs like Intel APL or modern AMD platforms as the bootblock is loaded differently. So they don't need the top aligned cbfs bootblock. To not clutter the main make file move out adding the bootblock. Change-Id: I4de9d7fedf1ae5a37a3310dd42eb07b44c030930 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-12Makefile.inc: Generate master header and pointer as C structsArthur Heymans
The makefiles don't like cbfs file names with spaces in them so update the file name with '_' instead of spaces. To keep the master header at the top of cbfs, add a placeholder. This removes the need to handle the cbfs master header in cbfstool. This functionality will be dropped in a later CL. On x86 reserve some space in the linker script to add the pointer. On non-x86 generate a pointer inside a C struct file. As a bonus this would actually fix the master header pointer mechanism on Intel/APL as only the bootblock inside IFWI gets memory mapped. TESTED on thinkpad X201: SeaBIOS correctly finds the cbfs master header. Change-Id: I3ba01be7da1f09a8cac287751497c18cda97d293 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-11commonlib: Add timestamp IDs for Chrome OS hypervisorMattias Nissler
Chrome OS is experimenting with a hypervisor layer that boots after firmware, but before the OS. From the OS' perspective, it can be considered an extension of firmware, and hence it makes sense to emit timestamp to track hypervisor boot latency. This change adds timestamp IDs in the 1200-1300 range for this purpose. BUG=b:217638034 BRANCH=none TEST=Manual: cbmem -a TS_CRHV_BOOT to add a timestamp, cbmem -t to verify that it got added to the timestamp table. Change-Id: If70447eea2c2edf42b43e0198b827c1348b935ea Signed-off-by: Mattias Nissler <mnissler@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-11mb/google/brya/var/crota: enable wifi sarScott Chao
BUG=b:216594621 BRANCH=brya TEST=build pass and SAR table be changed according to tablet/ desktop mode Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I62265e8931da48d20cf41e0c91ccb1a5b4bc1167 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-11mb/google/brya/var/kinox: Disable thunderbolt interfaceDtrain Hsu
Disable all of the TBT devices in devicetree since kinox doesn't support thunderbolt. The change also need to disable TBT in fitimage (chrome-internal:4731094). BUG=b:231654363 TEST=Build and run on DUT. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I944680dd1f41ac6f375015a3a138eb00c41b58a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-11mb/google/brask/variants/moli: correct tcss_usb3 portCasper Chang
Correct tcss_usb3_port to meet Moli's schematic design. BUG=b:220814038 TEST=emerge-brask coreboot Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-11device/dram/common.h: Use C over CPPArthur Heymans
This fixes building with clang. Change-Id: Ia8511ab46184aa0d8ee3a79c3ef22614aeb61298 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-11amd/*/gcccar.inc: Replace local declarationsArthur Heymans
Although useful to declare local symbols inside macros clang does not support them. Using the \@ symbol which increments each time the macro is used we can do the same. With BUILD_TIMELESS=1 the binaries don't change and do build with GCC so nothing is lost here. Change-Id: I01054e2bdcb63810b21eb51b46bdc6e1bd999516 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-11soc/*: Use __fallthrough statementArthur Heymans
Clang needs an attribute not a comment. Change-Id: I78f87d80bd4f366ed6cfa74619dd107ac61bc935 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-11*.h: Fix up typos in guardingArthur Heymans
Clang complains about this. Change-Id: I421d6c5daa373d1537e4ac2243438e7f1f6208d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63067 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-11sec/intel/txt: Use 'bios_acm_error' variableArthur Heymans
Use the variable intended for this use. This fixes building with clang. Change-Id: I4ee61fb9533b90ddb1a1592d5d9945761739ddb6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63062 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-11superio/kbc1100: Fix set but unused variablesArthur Heymans
This fixes building with clang. Change-Id: I865038ffab9cd7be8aa6a42e629f108b55c08f59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-05-11mb/*/bootblock.c: Fix set but unused variable over inb loopArthur Heymans
Change-Id: Iba80c4a5960c6fb59f542b33e8e769576ccfed59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-05-11vendorcode/amd/cimx/sb900: Drop codeArthur Heymans
No mainboard is using this code. Change-Id: I4374360c211593a8468b6226f3d1729885b533e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-11amd/fam15tn/gcccar.inc: Fix msr access with clangArthur Heymans
Change-Id: I21bebd475dce373a77626d2e78a0ab10678ea8b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-11amd/f15tn/gcccar.inc: Fix macro with ClangArthur Heymans
Change-Id: I0d95ac9d548e410a81188307cc92f77224baea0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-11drivers/intel/gma/opregion.c: Fix uninitialised variable useArthur Heymans
Change-Id: I87cff1e0360e23e37201381ed8a6920ee36b2747 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61892 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-11drivers/usb/ehci_debug.c: Fix unused variable warningArthur Heymans
Clang complains about unused variables when DEBUG_CONSOLE_INIT is not set. Change-Id: Icf5fd69fbf54b0d40bfdb17d1396d77dcb0a6060 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-11security/tpm/crtm.c: Remove set but unused variableArthur Heymans
Change-Id: I3c97cb57fe13adee217783973691748d6c542abe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-09soc/mediatek: Demote log level of SPMI clock calibration problem to infoRex-BC Chen
It's expected that the mismatch logs will be shown when doing calibration for spmi clock. If it is failed to do calibration for spmi clock for all data, the system will enter "die". Therefore, we adjust the log level from BIOS_ERR to BIOS_INFO. BUG=b:231531254 TEST=emerge-cherry coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/64090 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-09soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xFzhiyong tao
PMIC_CPSDSA4[4:0] controls the power-down at the specified time slot. Setting it to 0xA would cause an extra delay of 20ms compared to 0xF. The value of time slot is from 0x0 to 0x1F which represents the delay when reset occurs. To avoid the delay, change the value from 0xA to 0xF. This modification is based on chapter 3.7 in the MT8186 functional specification. BUG=b:218630683, b:218630684 TEST=the power-off waveform is correct. Signed-off-by: zhiyong tao <zhiyong.tao@mediatek.corp-partner.google.com> Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64038 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-06soc/amd/picasso: Use read*pArthur Heymans
This avoids compiler warnings on 64bit builds that complains about casting pointer to non matching integer size. Change-Id: I29fdb73ae1c0508796a21b650bf4fd1ac6688021 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-06mb/google/brask/variants/moli: enable BT offloadCasper Chang
Enable BT offload of NAU88L25B on Moli with fw_config NAU88L25B_I2S. BUG=b:220814038 TEST=emerge-brask coreboot, Check BT offload enabled in CPU log and audio works. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I72d91d2dafffa7d9604b7dd3d697cb3b2b04b152 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-05 01:17:41 +0000