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authorTony Huang <tony-huang@quanta.corp-partner.google.com>2022-05-09 16:15:43 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-05-12 18:33:16 +0000
commit1ffec679fe16af01340f193df45a64d538ba63a8 (patch)
treec62cb12e1fe4c1e7735a275bda1c376b44248590 /src
parent3f01cd14533f12f04a87a9cf1111dd948094bac4 (diff)
mb/google/brya/var/agah: Enable PCIe RP 3 for LAN
Using CLKREQ 4 and CLKSRC 4 BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: Ie0e362013551036a03ef69a98c6f1793e0e75c41 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/brya/variants/agah/overridetree.cb6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb
index 70bc09289d..01f0252258 100644
--- a/src/mainboard/google/brya/variants/agah/overridetree.cb
+++ b/src/mainboard/google/brya/variants/agah/overridetree.cb
@@ -157,6 +157,12 @@ chip soc/intel/alderlake
end
end
device ref pcie_rp3 on
+ # Enable PCIE 3 using clk 4
+ register "pch_pcie_rp[PCH_RP(3)]" = "{
+ .clk_src = 4,
+ .clk_req = 4,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
chip drivers/net
register "customized_leds" = "0x05af"
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D2)"