vendorcode/amd/cimx/sb900: Drop code

No mainboard is using this code. Change-Id: I4374360c211593a8468b6226f3d1729885b533e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
author: Arthur Heymans <arthur@aheymans.xyz> 2022-03-23 22:03:24 +0100
committer: Arthur Heymans <arthur@aheymans.xyz> 2022-05-11 05:59:06 +0000
commit: e2ffcc6068cb278689fc656742fa61a38ebe9fe4 (patch)
tree: e8c3917de38c3fe8ee01f5e0f8a4479f4ad3d318 /src
parent: 3a077965dedfc757d05ee88561012981da591677 (diff)
40 files changed, 0 insertions, 15126 deletions
diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc
index 97c35741ab..ca6c75647c 100644
--- a/src/southbridge/amd/common/Makefile.inc
+++ b/src/southbridge/amd/common/Makefile.inc
@@ -1,5 +1,4 @@
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
diff --git a/src/vendorcode/amd/cimx/Makefile.inc b/src/vendorcode/amd/cimx/Makefile.inc
index bb9b78c88f..33fc2e3e8f 100644
--- a/src/vendorcode/amd/cimx/Makefile.inc
+++ b/src/vendorcode/amd/cimx/Makefile.inc
@@ -1,2 +1 @@
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
diff --git a/src/vendorcode/amd/cimx/sb900/AcpiLib.c b/src/vendorcode/amd/cimx/sb900/AcpiLib.c
deleted file mode 100644
index 845b34df12..0000000000
--- a/src/vendorcode/amd/cimx/sb900/AcpiLib.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-//
-//
-// Routine Description:
-//
-//  Locate ACPI table
-//
-// Arguments:
-//
-//  Signature - table signature
-//
-//Returns:
-//
-//  pointer to ACPI table
-//
-//
-VOID*
-ACPI_LocateTable (
-  IN       unsigned int Signature
-  )
-{
-  UINT32  i;
-  UINT32* RsdPtr;
-  UINT32* Rsdt;
-  UINTN   tableOffset;
-  DESCRIPTION_HEADER* CurrentTable;
-  RsdPtr = (UINT32*) (UINTN)0xe0000;
-  Rsdt = NULL;
-  do {
-//    if ( *RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP' ) {
-//    if ( (*RsdPtr == 0x52534420) && (*(RsdPtr + 1) == 0x50545220) ) {
-    if ( (*RsdPtr == 0x20445352) && (*(RsdPtr + 1) == 0x20525450) ) {
-      Rsdt = (UINT32*) (UINTN) ((RSDP_HEADER*)RsdPtr)->RsdtAddress;
-      break;
-    }
-    RsdPtr += 4;
-  } while ( RsdPtr <= (UINT32*) (UINTN)0xffff0 );
-  if ( Rsdt != NULL && ACPI_GetTableChecksum (Rsdt) == 0 ) {
-    for ( i = 0; i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; i++ ) {
-      tableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + i * 4);
-      CurrentTable = (DESCRIPTION_HEADER*)tableOffset;
-      if ( CurrentTable->Signature == Signature ) {
-        return CurrentTable;
-      }
-    }
-  }
-  return NULL;
-}
-
-//
-//
-//  Routine Description:
-//
-//  Update table checksum
-//
-//  Arguments:
-//
-//  TablePtr - table pointer
-//
-//  Returns:
-//
-//  none
-//
-//
-VOID
-ACPI_SetTableChecksum (
-  IN       VOID* TablePtr
-  )
-{
-  UINT8 Checksum;
-  Checksum = 0;
-  ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;
-  Checksum = ACPI_GetTableChecksum (TablePtr);
-  ((DESCRIPTION_HEADER*)TablePtr)->Checksum = (UINT8) (0x100 - Checksum);
-}
-
-//
-//
-//  Routine Description:
-//
-//  Get table checksum
-//
-//  Arguments:
-//
-//  TablePtr - table pointer
-//
-//  Returns:
-//
-//  none
-//
-//
-UINT8
-ACPI_GetTableChecksum (
-  IN       VOID* TablePtr
-  )
-{
-  return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length);
-}
-
-
-UINT8
-GetByteSum (
-  IN       VOID* pData,
-  IN       UINT32 Length
-  )
-{
-  UINT32  i;
-  UINT8 Checksum;
-  Checksum = 0;
-  for ( i = 0; i < Length; i++ ) {
-    Checksum = Checksum + (*((UINT8*)pData + i));
-  }
-  return Checksum;
-}
-VOID
-GetSbAcpiMmioBase (
-  OUT     UINT32*    AcpiMmioBase
-  )
-{
-  UINT32    Value16;
-
-  ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint16, &Value16);
-  *AcpiMmioBase = Value16 << 16;
-}
-
-VOID
-GetSbAcpiPmBase (
-  OUT     UINT16*    AcpiPmBase
-  )
-{
-  ReadPMIO (SB_PMIOA_REG60, AccWidthUint16, AcpiPmBase);
-}
-
-VOID
-SetAcpiPma (
-  IN     UINT8    pmaControl
-  )
-{
-  UINT16 pmaBase;
-  UINT16 dwValue;
-  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74, AccWidthUint16, &dwValue);
-  dwValue &= ~BIT6;
-  WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74, AccWidthUint16, &dwValue);
-  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, &pmaBase);
-  WriteIo8 (pmaBase, pmaControl);
-  RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, ~BIT7, pmaControl << 7);
-}
-
diff --git a/src/vendorcode/amd/cimx/sb900/AcpiLib.h b/src/vendorcode/amd/cimx/sb900/AcpiLib.h
deleted file mode 100644
index c604023736..0000000000
--- a/src/vendorcode/amd/cimx/sb900/AcpiLib.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-/**
- * RSDP - ACPI 2.0 table RSDP
- */
-typedef struct _RSDP {
-  unsigned long long  Signature;        ///< RSDP signature "RSD PTR"
-  unsigned char  Checksum;          ///< checksum of the first 20 bytes
-  unsigned char  OEMID[6];          ///< OEM ID, "LXBIOS"
-  unsigned char  Revision;          ///< 0 for APCI 1.0, 2 for ACPI 2.0
-  unsigned int  RsdtAddress;      ///< physical address of RSDT
-  unsigned int  Length;           ///< total length of RSDP (including extended part)
-  unsigned long long  XsdtAddress;      ///< physical address of XSDT
-  unsigned char  ExtendedChecksum;  ///< chechsum of whole table
-  unsigned char  Reserved[3];       ///< Reserved
-} RSDP_HEADER;
-
-
-/// DESCRIPTION_HEADER - ACPI common table header
-typedef struct _DESCRIPTION_HEADER {
-  unsigned int  Signature;        ///< ACPI signature (4 ASCII characters)
-  unsigned int  Length;           ///< Length of table, in bytes, including header
-  unsigned char  Revision;          ///< ACPI Specification minor version #
-  unsigned char  Checksum;          ///< To make sum of entire table == 0
-  unsigned char  OEMID[6];          ///< OEM identification
-  unsigned char  OEMTableID[8];     ///< OEM table identification
-  unsigned int  OEMRevision;      ///< OEM revision number
-  unsigned int  CreatorID;        ///< ASL compiler vendor ID
-  unsigned int  CreatorRevision;  ///< ASL compiler revision number
-} DESCRIPTION_HEADER;
-
-void* ACPI_LocateTable (IN unsigned int Signature);
-void  ACPI_SetTableChecksum (IN void* TablePtr);
-unsigned char ACPI_GetTableChecksum (IN void* TablePtr);
-unsigned char GetByteSum (IN void* pData, IN unsigned int Length);
diff --git a/src/vendorcode/amd/cimx/sb900/AmdLib.c b/src/vendorcode/amd/cimx/sb900/AmdLib.c
deleted file mode 100644
index 415b4baf65..0000000000
--- a/src/vendorcode/amd/cimx/sb900/AmdLib.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-UINT8
-getNumberOfCpuCores (
-  OUT VOID
-  )
-{
-  UINT8 Result;
-  Result = 1;
-  Result = ReadNumberOfCpuCores ();
-  return Result;
-}
-
-UINT32
-readAlink (
-  IN       UINT32 Index
-  )
-{
-  UINT32 Data;
-  WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
-  ReadIO (ALINK_ACCESS_DATA, AccWidthUint32, &Data);
-  //Clear Index
-  Index = 0;
-  WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
-  return Data;
-}
-
-VOID
-writeAlink (
-  IN       UINT32 Index,
-  IN       UINT32 Data
-  )
-{
-  WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
-  WriteIO (ALINK_ACCESS_DATA, AccWidthUint32 | S3_SAVE, &Data);
-  //Clear Index
-  Index = 0;
-  WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
-}
-
-VOID
-rwAlink (
-  IN       UINT32 Index,
-  IN       UINT32 AndMask,
-  IN       UINT32 OrMask
-  )
-{
-  UINT32 AccessType;
-  AccessType = Index & 0xE0000000;
-  if (AccessType == (AXINDC << 29)) {
-    writeAlink ((SB_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF);
-    Index = (SB_AX_DATAC_REG34 | AccessType);
-  } else if (AccessType == (AXINDP << 29)) {
-    writeAlink ((SB_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF);
-    Index = (SB_AX_DATAP_REG3C | AccessType);
-  }
-  writeAlink (Index, ((readAlink (Index) & AndMask) | OrMask) );
-}
-
diff --git a/src/vendorcode/amd/cimx/sb900/AmdSbLib.c b/src/vendorcode/amd/cimx/sb900/AmdSbLib.c
deleted file mode 100644
index 72023af0c3..0000000000
--- a/src/vendorcode/amd/cimx/sb900/AmdSbLib.c
+++ /dev/null
@@ -1,336 +0,0 @@
-/**
- * @file
- *
- * Southbridge IO access common routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-
-/**< SbStall - Reserved  */
-VOID
-SbStall (
-  IN       UINT32 uSec
-  )
-{
-  UINT16 timerAddr;
-  UINT32 startTime;
-  UINT32 elapsedTime;
-
-  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr);
-  if ( timerAddr == 0 ) {
-    uSec = uSec / 2;
-    while ( uSec != 0 ) {
-      ReadIO (0x80, AccWidthUint8, (UINT8 *) (&startTime));
-      uSec--;
-    }
-  } else {
-    ReadIO (timerAddr, AccWidthUint32, &startTime);
-    for ( ;; ) {
-      ReadIO (timerAddr, AccWidthUint32, &elapsedTime);
-      if ( elapsedTime < startTime ) {
-        elapsedTime = elapsedTime + 0xFFFFFFFF - startTime;
-      } else {
-        elapsedTime = elapsedTime - startTime;
-      }
-      if ( (elapsedTime * 28 / 100) > uSec ) {
-        break;
-      }
-    }
-  }
-}
-
-/**< cimSbStall - Reserved  */
-VOID
-cimSbStall (
-  IN       UINT32 uSec
-  )
-{
-  UINT16 timerAddr;
-  UINT32 startTime;
-  UINT32 elapsedTime;
-
-  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr);
-  if ( timerAddr == 0 ) {
-    uSec = uSec / 2;
-    while ( uSec != 0 ) {
-      ReadIo8 (0x80);
-      uSec--;
-    }
-  } else {
-    startTime = ReadIo32 (timerAddr);
-    for ( ;; ) {
-      elapsedTime = ReadIo32 (timerAddr);
-      if ( elapsedTime < startTime ) {
-        elapsedTime = elapsedTime + 0xFFFFFFFF - startTime;
-      } else {
-        elapsedTime = elapsedTime - startTime;
-      }
-      if ( (elapsedTime * 28 / 100) > uSec ) {
-        break;
-      }
-    }
-  }
-}
-
-/**< SbReset - Reserved  */
-VOID
-SbReset ()
-{
-  RWIO (0xcf9, AccWidthUint8, 0x0, 0x06);
-}
-
-/**< outPort80 - Reserved  */
-VOID
-outPort80 (
-  IN  UINT32 pcode
-  )
-{
-  WriteIO (0x80, AccWidthUint8, &pcode);
-  return;
-}
-
-/**< outPort1080 - Reserved  */
-VOID
-outPort1080 (
-  IN  UINT32 pcode
-  )
-{
-  WriteIo32 (0x1080, pcode);
-  return;
-}
-
-/**< AmdSbCopyMem - Reserved  */
-VOID
-AmdSbCopyMem (
-  IN      VOID*   pDest,
-  IN      VOID*   pSource,
-  IN      UINTN   Length
-  )
-{
-  UINTN  i;
-  UINT8  *Ptr;
-  UINT8  *Source;
-  Ptr = (UINT8*)pDest;
-  Source = (UINT8*)pSource;
-  for (i = 0; i < Length; i++) {
-    *Ptr = *Source;
-    Source++;
-    Ptr++;
-  }
-}
-
-/** GetRomSigPtr - Reserved **/
-VOID*
-GetRomSigPtr (
-  IN UINTN* RomSigPtr
-  )
-{
-  UINTN  RomPtr;
-  UINT32 RomSig;
-  RomPtr = 0xFFF20000;  // 1M
-  ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
-  if ( RomSig != 0x55AA55AA ) {
-    RomPtr = 0xFFE20000; //2M
-    ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
-    if ( RomSig != 0x55AA55AA ) {
-      RomPtr = 0xFFC20000; //4M
-      ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
-      if ( RomSig != 0x55AA55AA ) {
-        RomPtr = 0xFF820000; //8M
-        ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
-        if ( RomSig != 0x55AA55AA ) {
-          RomPtr = 0xFF020000; //16M
-          ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
-          if ( RomSig != 0x55AA55AA ) {
-            RomPtr = 0x0; // not found
-          }
-        }
-      }
-    }
-  }
-  *RomSigPtr = RomPtr;
-  return RomSigPtr;
-}
-
-VOID
-RWXhciIndReg (
-  IN       UINT32 Index,
-  IN       UINT32 AndMask,
-  IN       UINT32 OrMask
-  )
-{
-  UINT32  IndReg;
-  WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
-  ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
-  IndReg &= AndMask;
-  IndReg |= OrMask;
-  WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
-
-#ifndef XHCI_SUPPORT_ONE_CONTROLLER
-  WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
-  ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
-  IndReg &= AndMask;
-  IndReg |= OrMask;
-  WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
-#endif
-}
-
-VOID
-RWXhci0IndReg (
-  IN       UINT32 Index,
-  IN       UINT32 AndMask,
-  IN       UINT32 OrMask
-  )
-{
-  UINT32  IndReg;
-  WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
-  ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
-  IndReg &= AndMask;
-  IndReg |= OrMask;
-  WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
-}
-
-VOID
-RWXhci1IndReg (
-  IN       UINT32 Index,
-  IN       UINT32 AndMask,
-  IN       UINT32 OrMask
-  )
-{
-  UINT32  IndReg;
-  WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
-  ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
-  IndReg &= AndMask;
-  IndReg |= OrMask;
-  WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
-}
-
-VOID
-AcLossControl (
-  IN       UINT8 AcLossControlValue
-  )
-{
-  AcLossControlValue &= 0x03;
-  AcLossControlValue |= BIT2;
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG5B, AccWidthUint8, 0xF0, AcLossControlValue);
-}
-
-VOID
-SbVgaInit (
-  VOID
-  )
-{
-  // OBS194249 Cobia_Nutmeg_DP-VGA Electrical SI validation_Lower RGB Luminance level BGADJ=0x1F & DACADJ=0x1B
-  //
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xff, BIT5 );
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0x00, 0x17 );
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0x00, ((BGADJ << 2) + (((DACADJ & 0xf0) >> 4) & 0x3)));
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0x00, 0x16 );
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0x0f, ((DACADJ & 0x0f) << 4));
-
-  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x00))) = (0x08 << 4) + (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 16) & 0xff);
-  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x01))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 8) & 0xff);
-  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x02))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 0) & 0xff);
-  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x03))) = (UINT8) (0x03);
-  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x04))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 0) & 0xff);
-  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x05))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 8) & 0xff);
-  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x06))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 16) & 0xff);
-  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x07))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 24) & 0xff);
-  *((UINT8*) ((UINTN)(PKT_LEN_REG))) = 0x08;
-  *((UINT8*) ((UINTN)(PKT_CTRL_REG))) = 0x01;
-  //RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, ~(BIT5), 0 );
-}
-
-VOID
-RecordSbConfigPtr (
-  IN       UINT32 SbConfigPtr
-  )
-{
-  RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 0) & 0xFF) );
-  RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 8) & 0xFF) );
-  RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 16) & 0xFF) );
-  RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 24) & 0xFF) );
-}
-
-VOID
-SbGpioInit (
-  IN       SB_GPIO_INIT_ENTRY *SbGpioInitTable
-  )
-{
-  while ( SbGpioInitTable->GpioPin < 0xFF ) {
-    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SbGpioInitTable->GpioPin, AccWidthUint8, 0, SbGpioInitTable->GpioMux );
-    RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SbGpioInitTable->GpioPin, AccWidthUint8, ~ (BIT5 + BIT6), ((SbGpioInitTable->GpioOutEnB + (SbGpioInitTable->GpioOut << 1)) << 5) );
-    SbGpioInitTable ++;
-  }
-}
-
-VOID
-SbGpioControl (
-  IN       SB_GPIO_CONTROL_ENTRY *SbGpio
-  )
-{
-  UINT8 GpioCurrent;
-  ReadMEM (ACPI_MMIO_BASE + GPIO_BASE + SbGpio->GpioPin, AccWidthUint8, &GpioCurrent );
-  if ((GpioCurrent & BIT5) == 0) {
-    RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SbGpio->GpioPin, AccWidthUint8, ~ BIT6, (SbGpio->GpioControl << 6) );
-  }
-  GpioCurrent &= BIT7;
-  SbGpio->GpioControl = GpioCurrent >> 7;
-}
-
-VOID
-SbFlashUsbSmi (
-  VOID
-  )
-{
-  if ( ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) & (BIT4) ) {
-    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) &= ~ (BIT4);
-    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) |= (BIT4);
-  }
-}
-
-VOID
-SbEnableUsbIrq1Irq12ToPicApic (
-  VOID
-  )
-{
-  ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) |= (BIT1);
-}
-
diff --git a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h
deleted file mode 100644
index 47a7048560..0000000000
--- a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/**
- * @file
- *
- * Southbridge IO access common routine define file
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-
-//AMDSBLIB Routines
-
-/*--------------------------- Documentation Pages ---------------------------*/
-/**< SbStall - Reserved  */
-void  SbStall (IN unsigned int uSec);
-
-/**< cimSbStall - Reserved  */
-void  cimSbStall (IN unsigned int uSec);
-
-/**< SbReset - Reserved  */
-void SbReset (void);
-
-/**< outPort80 - Reserved  */
-void outPort80 (IN unsigned int pcode);
-
-/**< outPort80 - Reserved  */
-void outPort1080 (IN unsigned int pcode);
-
-/**< getEfuseStatue - Reserved  */
-void getEfuseStatus (IN void* Value);
-
-/**< getEfuseByte - Reserved  */
-unsigned char getEfuseByte (IN unsigned char Index);
-
-/**< AmdSbDispatcher - Reserved  */
-AGESA_STATUS  AmdSbDispatcher (IN void *pConfig);
-
-/**< AmdSbCopyMem - Reserved  */
-void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length);
-
-/**< GetRomSigPtr - Reserved  */
-void* GetRomSigPtr (IN UINTN * RomSigPtr);
-
-/**< RWXhciIndReg - Reserved  */
-void RWXhciIndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
-
-/**< RWXhciIndReg - Reserved  */
-void RWXhci0IndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
-
-/**< RWXhciIndReg - Reserved  */
-void RWXhci1IndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
-
-/**< AcLossControl - Reserved  */
-void AcLossControl (IN unsigned char AcLossControlValue);
-
-/**< SbVgaInit - Reserved  */
-void SbVgaInit (void);
-
-/**< RecordSbConfigPtr - Reserved  */
-void RecordSbConfigPtr (IN unsigned int SbConfigPtr);
-
-/**< SbGpioInit - Reserved  */
-void
-SbGpioInit (
-  IN       SB_GPIO_INIT_ENTRY *SbGpioInitTable
-  );
-
-/**< SbGpioControl - Reserved  */
-void
-SbGpioControl (
-  IN       SB_GPIO_CONTROL_ENTRY *SbGpio
-  );
-
-/**< SbFlashUsbSmi - Reserved  */
-void SbFlashUsbSmi (void);
-
-/**< SbEnableUsbIrq1Irq12ToPicApic - Reserved  */
-void SbEnableUsbIrq1Irq12ToPicApic (void);
-
diff --git a/src/vendorcode/amd/cimx/sb900/Azalia.c b/src/vendorcode/amd/cimx/sb900/Azalia.c
deleted file mode 100644
index 9a32018b0a..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Azalia.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/**
- * @file
- *
- * Config Southbridge HD Audio Controller
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-
-//
-// Declaration of local functions
-//
-
-VOID configureAzaliaPinCmd (IN AMDSBCFG* pConfig, IN UINT32 ddBAR0, IN UINT8 dbChannelNum);
-VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN UINT32 ddChannelNum, IN UINT32 ddBAR0);
-
-/**
- * Pin Config for ALC880, ALC882 and ALC883.
- *
- *
- *
- */
-CODECENTRY AzaliaCodecAlc882Table[] =
-{
-  {0x14, 0x01014010},
-  {0x15, 0x01011012},
-  {0x16, 0x01016011},
-  {0x17, 0x01012014},
-  {0x18, 0x01A19030},
-  {0x19, 0x411111F0},
-  {0x1a, 0x01813080},
-  {0x1b, 0x411111F0},
-  {0x1C, 0x411111F0},
-  {0x1d, 0x411111F0},
-  {0x1e, 0x01441150},
-  {0x1f, 0x01C46160},
-  {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0262.
- *
- *
- *
- */
-CODECENTRY AzaliaCodecAlc262Table[] =
-{
-  {0x14, 0x01014010},
-  {0x15, 0x411111F0},
-  {0x16, 0x411111F0},
-  {0x18, 0x01A19830},
-  {0x19, 0x02A19C40},
-  {0x1a, 0x01813031},
-  {0x1b, 0x02014C20},
-  {0x1c, 0x411111F0},
-  {0x1d, 0x411111F0},
-  {0x1e, 0x0144111E},
-  {0x1f, 0x01C46150},
-  {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0269.
- *
- *
- *
- */
-CODECENTRY AzaliaCodecAlc269Table[] =
-{
-  {0x12, 0x99A308F0},
-  {0x14, 0x99130010},
-  {0x15, 0x0121101F},
-  {0x16, 0x99036120},
-  {0x18, 0x01A19850},
-  {0x19, 0x99A309F0},
-  {0x1a, 0x01813051},
-  {0x1b, 0x0181405F},
-  {0x1d, 0x40134601},
-  {0x1e, 0x01442130},
-  {0x11, 0x99430140},
-  {0x20, 0x0030FFFF},
-  {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0861.
- *
- *
- *
- */
-CODECENTRY AzaliaCodecAlc861Table[] =
-{
-  {0x01, 0x8086C601},
-  {0x0B, 0x01014110},
-  {0x0C, 0x01813140},
-  {0x0D, 0x01A19941},
-  {0x0E, 0x411111F0},
-  {0x0F, 0x02214420},
-  {0x10, 0x02A1994E},
-  {0x11, 0x99330142},
-  {0x12, 0x01451130},
-  {0x1F, 0x411111F0},
-  {0x20, 0x411111F0},
-  {0x23, 0x411111F0},
-  {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0889.
- *
- *
- *
- */
-CODECENTRY AzaliaCodecAlc889Table[] =
-{
-  {0x11, 0x411111F0},
-  {0x14, 0x01014010},
-  {0x15, 0x01011012},
-  {0x16, 0x01016011},
-  {0x17, 0x01013014},
-  {0x18, 0x01A19030},
-  {0x19, 0x411111F0},
-  {0x1a, 0x411111F0},
-  {0x1b, 0x411111F0},
-  {0x1C, 0x411111F0},
-  {0x1d, 0x411111F0},
-  {0x1e, 0x01442150},
-  {0x1f, 0x01C42160},
-  {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ADI1984.
- *
- *
- *
- */
-CODECENTRY AzaliaCodecAd1984Table[] =
-{
-  {0x11, 0x0221401F},
-  {0x12, 0x90170110},
-  {0x13, 0x511301F0},
-  {0x14, 0x02A15020},
-  {0x15, 0x50A301F0},
-  {0x16, 0x593301F0},
-  {0x17, 0x55A601F0},
-  {0x18, 0x55A601F0},
-  {0x1A, 0x91F311F0},
-  {0x1B, 0x014511A0},
-  {0x1C, 0x599301F0},
-  {0xff, 0xffffffff}
-};
-
-/**
- * FrontPanel Config table list
- *
- *
- *
- */
-CODECENTRY FrontPanelAzaliaCodecTableList[] =
-{
-  {0x19, 0x02A19040},
-  {0x1b, 0x02214020},
-  {0xff, 0xffffffff}
-};
-
-/**
- * Current HD Audio support codec list
- *
- *
- *
- */
-CODECTBLLIST azaliaCodecTableList[] =
-{
-  {0x010ec0880, &AzaliaCodecAlc882Table[0]},
-  {0x010ec0882, &AzaliaCodecAlc882Table[0]},
-  {0x010ec0883, &AzaliaCodecAlc882Table[0]},
-  {0x010ec0885, &AzaliaCodecAlc882Table[0]},
-  {0x010ec0889, &AzaliaCodecAlc889Table[0]},
-  {0x010ec0262, &AzaliaCodecAlc262Table[0]},
-  {0x010ec0269, &AzaliaCodecAlc269Table[0]},
-  {0x010ec0861, &AzaliaCodecAlc861Table[0]},
-  {0x011d41984, &AzaliaCodecAd1984Table[0]},
-  { (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF}
-};
-
-/**
- * azaliaInitBeforePciEnum - Config HD Audio Before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-azaliaInitBeforePciEnum (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  if ( pConfig->AzaliaController == 1 ) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, BIT0);
-    if ( pConfig->BuildParameters.HdAudioMsi) {
-      RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG44, AccWidthUint32 | S3_SAVE, ~BIT8, BIT8);
-      RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG60, AccWidthUint32 | S3_SAVE, ~BIT16, BIT16);
-    }
-  }
-}
-
-/**
- * azaliaInitAfterPciEnum - Config HD Audio after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-azaliaInitAfterPciEnum (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8   Data;
-  UINT8   i;
-  UINT8   dbEnableAzalia;
-  UINT8   dbPinRouting;
-  UINT8   dbChannelNum;
-  UINT8   dbTempVariable;
-  UINT16   dwTempVariable;
-  UINT32   ddBAR0;
-  UINT32   ddTempVariable;
-  dbEnableAzalia = 0;
-  dbChannelNum = 0;
-  dbTempVariable = 0;
-  dwTempVariable = 0;
-  ddBAR0 = 0;
-  ddTempVariable = 0;
-
-  if ( pConfig->AzaliaController == 1 ) {
-    return;
-  }
-
-  if ( pConfig->AzaliaController != 1 ) {
-    RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
-    if ( pConfig->BuildParameters.AzaliaSsid != 0 ) {
-      RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
-    }
-    ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
-    if ( ddBAR0 != 0 ) {
-      if ( ddBAR0 != 0xFFFFFFFF ) {
-        ddBAR0 &=  ~(0x03FFF);
-        dbEnableAzalia = 1;
-        TRACE ((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n"));
-      }
-    }
-  }
-
-  if ( dbEnableAzalia ) {
-    pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 0);
-    pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 2);
-    pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 4);
-    pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 6);
-    // Get SDIN Configuration
-    if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) {
-      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E);
-      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00);
-    } else {
-      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0);
-      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01);
-    }
-    if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) {
-      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E);
-      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00);
-    } else {
-      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0);
-      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01);
-    }
-    if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) {
-      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E);
-      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00);
-    } else {
-      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0);
-      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01);
-    }
-    if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) {
-      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E);
-      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00);
-    } else {
-      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0);
-      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01);
-    }
-    // INT#A Azalia resource
-    Data = 0x93; // Azalia APIC index
-    WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
-    Data = 0x10; // IRQ16 (INTA#)
-    WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
-
-    i = 11;
-    do {
-      ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
-      dbTempVariable |= BIT0;
-      WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
-      SbStall (1000);
-      ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
-      i--;
-    }  while ((! (dbTempVariable & BIT0)) && (i > 0) );
-
-    if ( i == 0 ) {
-      TRACE ((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n"));
-      return;
-    }
-
-    SbStall (1000);
-    ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
-    if ( dwTempVariable & 0x0F ) {
-
-      TRACE ((DMSG_SB_TRACE, "CIMxSB - At least One Azalia CODEC found \n"));
-      //atleast one azalia codec found
-      dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;
-      do {
-        if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) {
-          configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum);
-        }
-        dbPinRouting >>= 2;
-        dbChannelNum++;
-      }  while ( dbChannelNum != 4 );
-    } else {
-      TRACE ((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n"));
-      //No Azalia codec found
-      if ( pConfig->AzaliaController != 2 ) {
-        dbEnableAzalia = 0;     //set flag to disable Azalia
-      }
-    }
-  }
-
-  if ( dbEnableAzalia ) {
-    //redo clear reset
-    do {
-      dwTempVariable = 0;
-      WriteMEM ( ddBAR0 + SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable);
-      ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
-      dbTempVariable &= ~(BIT0);
-      WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
-      ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
-    }  while ( dbTempVariable & BIT0 );
-
-    if ( pConfig->AzaliaSnoop == 1 ) {
-      RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1 + BIT0);
-    }
-  } else {
-    //disable Azalia controller
-    RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0);
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
-  }
-}
-
-/**
- * configureAzaliaPinCmd - Configuration HD Audio PIN Command
- *
- *
- * @param[in] pConfig              Southbridge configuration structure pointer.
- * @param[in] ddBAR0               HD Audio BAR0 base address.
- * @param[in] dbChannelNum         Channel Number.
- *
- */
-VOID
-configureAzaliaPinCmd (
-  IN       AMDSBCFG* pConfig,
-  IN       UINT32 ddBAR0,
-  IN       UINT8 dbChannelNum
-  )
-{
-  UINT32   ddTempVariable;
-  UINT32   ddChannelNum;
-  CODECTBLLIST*  ptempAzaliaOemCodecTablePtr;
-  CODECENTRY* tempAzaliaCodecEntryPtr;
-
-  if ( (pConfig->AzaliaPinCfg) != 1 ) {
-    return;
-  }
-
-  ddChannelNum = dbChannelNum << 28;
-  ddTempVariable = 0xF0000;
-  ddTempVariable |= ddChannelNum;
-
-  WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-  SbStall (600);
-  ReadMEM (ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-
-  if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF))) {
-    ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR (&azaliaCodecTableList[0]);
-  } else {
-    ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr;
-  }
-
-  TRACE ((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %X \n", ptempAzaliaOemCodecTablePtr));
-
-  while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
-    if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable ) {
-      break;
-    } else {
-      ++ptempAzaliaOemCodecTablePtr;
-    }
-  }
-
-  if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
-    TRACE ((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n"));
-    tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
-    TRACE ((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %X \n", tempAzaliaCodecEntryPtr));
-
-    if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF)) ) {
-      tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (tempAzaliaCodecEntryPtr);
-    }
-    configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
-    if ( pConfig->AzaliaFrontPanel != 1 ) {
-      if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ) {
-        if ( ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == NULL) || ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) {
-          tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (&FrontPanelAzaliaCodecTableList[0]);
-        } else {
-          tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr;
-        }
-        configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
-      }
-    }
-  }
-}
-
-/**
- * configureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table
- *
- *
- * @param[in] tempAzaliaCodecEntryPtr    HD Audio Codec table structure pointer.
- * @param[in] ddChannelNum               HD Audio Channel Number.
- * @param[in] ddBAR0                     HD Audio BAR0 base address.
- *
- */
-VOID
-configureAzaliaSetConfigD4Dword (
-  IN       CODECENTRY* tempAzaliaCodecEntryPtr,
-  IN       UINT32 ddChannelNum,
-  IN       UINT32 ddBAR0
-  )
-{
-  UINT8 dbtemp1;
-  UINT8 dbtemp2;
-  UINT8 i;
-  UINT32 ddtemp;
-  UINT32 ddtemp2;
-  ddtemp = 0;
-  ddtemp2 = 0;
-  while ( (tempAzaliaCodecEntryPtr->Nid) != 0xFF ) {
-    dbtemp1 = 0x20;
-    if ( (tempAzaliaCodecEntryPtr->Nid) == 0x1 ) {
-      dbtemp1 = 0x24;
-    }
-
-    ddtemp =  tempAzaliaCodecEntryPtr->Nid;
-    ddtemp &= 0xff;
-    ddtemp <<= 20;
-    ddtemp |= ddChannelNum;
-
-    ddtemp |= (0x700 << 8);
-    for ( i = 4; i > 0; i-- ) {
-      do {
-        ReadMEM (ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2);
-      } while ( ddtemp2 & BIT0 );
-
-      dbtemp2 = (UINT8) (( (tempAzaliaCodecEntryPtr->Byte40) >> ((4 - i) * 8 ) ) & 0xff);
-      ddtemp =  (ddtemp & 0xFFFF0000) + ((dbtemp1 - i) << 8) + dbtemp2;
-      WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp);
-      SbStall (60);
-    }
-    ++tempAzaliaCodecEntryPtr;
-  }
-}
-
diff --git a/src/vendorcode/amd/cimx/sb900/Debug.c b/src/vendorcode/amd/cimx/sb900/Debug.c
deleted file mode 100644
index b78f5d7afb..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Debug.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-
-#define COM_BASE_ADDRESS   0x3f8
-#define DIVISOR            115200
-#define LF                 0x0a
-#define CR                 0x0d
-
-
-#ifdef CIM_DEBUG
-
-VOID SendBytePort (IN UINT8 Data);
-VOID SendStringPort (IN CHAR8* pstr);
-VOID ItoA (IN UINT32 Value, IN UINT32 Radix, IN CHAR8* pstr);
-
-#ifndef CIM_DEBUG_LEVEL
- #define CIM_DEBUG_LEVEL 0xf
-#endif
-
-VOID
-TraceCode (
-  IN       UINT32 Level,
-  IN       UINT32 Code
-  )
-{
-  if ( ! (Level & CIM_DEBUG_LEVEL) ) {
-    return;
-  }
-#if CIM_DEBUG & 1
-  if ( Code != 0xFF ) {
-    WriteIO (0x80, AccWidthUint8, &Code);
-  }
-#endif
-}
-
-
-VOID
-TraceDebug (
-  IN       UINT32 Level,
-  IN       CHAR8 *Format,
-  )
-{
-  CHAR8 temp[16];
-  va_list  ArgList;
-  UINT32 Radix;
-
-  if ( ! (Level & CIM_DEBUG_LEVEL) ) {
-    return;
-  }
-
-#if CIM_DEBUG & 2
-  ArgList = va_start (ArgList, Format);
-  Format = (CHAR8*) (Format);
-  while ( 1 ) {
-    if ( *Format == 0 ) {
-      break;
-    }
-    if ( *Format == ' % ' ) {
-      Radix = 0;
-      if ( *(Format + 1) == 's' || *(Format + 1) == 'S' ) {
-        SendStringPort ((CHAR8*) (va_arg (ArgList, CHAR8*)));
-        Format += 2;
-        continue;
-      }
-
-      if ( *(Format + 1) == 'd' || *(Format + 1) == 'D' ) {
-        Radix = 10;
-      }
-      if ( *(Format + 1) == 'x' || *(Format + 1) == 'X' ) {
-        Radix = 16;
-      }
-      if ( Radix ) {
-        ItoA (va_arg (ArgList, intqq), Radix, temp);
-        SendStringPort (temp);
-        Format += 2;
-        continue;
-      }
-    }
-    SendBytePort (*Format);
-    if ( *(Format) == 0x0a ) {
-      SendBytePort (0x0d);
-    }
-    Format++;
-  }
-  va_end (ArgList);
-#endif
-}
-
-
-VOID
-ItoA (
-  IN       UINT32 Value,
-  IN       UINT32 Radix,
-  IN       CHAR8* pstr
-  )
-{
-  CHAR8* tsptr;
-  CHAR8* rsptr;
-  CHAR8  ch1;
-  CHAR8  ch2;
-  UINT32 Reminder;
-  tsptr = pstr;
-  rsptr = pstr;
-//Create String
-  do {
-    Reminder = Value % Radix;
-    Value = Value / Radix;
-    if ( Reminder < 0xa ) {
-      *tsptr = Reminder + '0';
-    } else {
-      *tsptr = Reminder - 0xa + 'a';
-    }
-    tsptr++;
-  } while ( Value );
-//Reverse String
-  *tsptr = 0;
-  tsptr--;
-  while ( tsptr > rsptr ) {
-    ch1 = *tsptr;
-    ch2 = *rsptr;
-    *rsptr = ch1;
-    *tsptr = ch2;
-    tsptr--;
-    rsptr++;
-  }
-}
-
-VOID
-InitSerialOut (
-  )
-{
-  UINT8 Data;
-  UINT16   Divisor;
-  Data = 0x87;
-  WriteIO (COM_BASE_ADDRESS + 0x3, AccWidthUint8, &Data);
-  Divisor = 115200 / DIVISOR;
-  Data = Divisor & 0xFF;
-  WriteIO (COM_BASE_ADDRESS + 0x00, AccWidthUint8, &Data);
-  Data = Divisor >> 8;
-  WriteIO (COM_BASE_ADDRESS + 0x01, AccWidthUint8, &Data);
-  Data = 0x07;
-  WriteIO (COM_BASE_ADDRESS + 0x3, AccWidthUint8, &Data);
-}
-
-
-VOID
-SendStringPort (
-  IN       CHAR8* pstr
-  )
-{
-
-  while ( *pstr! = 0 ) {
-    SendBytePort (*pstr);
-    pstr++;
-  }
-}
-
-VOID
-SendBytePort (
-  IN       UINT8 Data
-  )
-{
-  INT8   Count;
-  UINT8 Status;
-  Count = 80;
-  do {
-    ReadIO ((COM_BASE_ADDRESS + 0x05), AccWidthUint8, &Status);
-    if ( Status == 0xff ) {
-      break;
-    }
-    // Loop  port is ready
-  } while ( (Status & 0x20) == 0 && (--Count) != 0 );
-  WriteIO (COM_BASE_ADDRESS + 0x00, AccWidthUint8, &Data);
-}
-#endif
diff --git a/src/vendorcode/amd/cimx/sb900/Dispatcher.c b/src/vendorcode/amd/cimx/sb900/Dispatcher.c
deleted file mode 100644
index ac1b517e64..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Dispatcher.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/**
- * @file
- *
- *  Function dispatcher.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
- *----------------------------------------------------------------------------------------
-*/
-
-
-//
-// Declaration of local functions
-//
-
-VOID  saveConfigPointer (IN AMDSBCFG* pConfig);
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U  R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * AmdSbDispatcher - Dispatch Southbridge function
- *
- *
- *
- * @param[in] pConfig   Southbridge configuration structure pointer.
- *
- */
-AGESA_STATUS
-AmdSbDispatcher (
-  IN       VOID *pConfig
-  )
-{
-  AGESA_STATUS      Status;
-  UINT64            tdValue;
-
-
-  Status = AGESA_UNSUPPORTED;
-  tdValue = 0x313141324E4448ull;
-
-//#if CIM_DEBUG
-//  InitSerialOut ();
-//#endif
-
-  Status = AGESA_UNSUPPORTED;
-  TRACE ((DMSG_SB_TRACE, "CIM - Hudson-2 Entry\n"));
-
-  saveConfigPointer (pConfig);
-
-  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
-    sbPowerOnInit ((AMDSBCFG*) pConfig);
-  }
-
-  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
-    sbBeforePciInit ((AMDSBCFG*)pConfig);
-  }
-
-  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) {
-    sbAfterPciInit ((AMDSBCFG*)pConfig);
-  }
-
-  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_MID_POST_INIT ) {
-    sbMidPostInit ((AMDSBCFG*)pConfig);
-  }
-
-  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) {
-    sbLatePost ((AMDSBCFG*)pConfig);
-  }
-
-  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) {
-    sbBeforePciRestoreInit ((AMDSBCFG*)pConfig);
-  }
-
-  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) {
-    sbAfterPciRestoreInit ((AMDSBCFG*)pConfig);
-  }
-
-  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) {
-    sbSmmService ((AMDSBCFG*)pConfig);
-  }
-
-  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) {
-    sbSmmAcpiOn ((AMDSBCFG*)pConfig);
-  }
-
-  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
-    sbECfancontrolservice ((AMDSBCFG*)pConfig);
-  }
-  TRACE ((DMSG_SB_TRACE, "CIMx - SB Exit\n"));
-  return Status;
-}
-
-/**
- * saveConfigPointer - Verify Southbridge CIMx module
- *
- *
- * @param[in] pConfig   Southbridge configuration structure pointer.
- *
- */
-VOID
-saveConfigPointer (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8   dbReg;
-  UINT8   i;
-  UINT32   ddValue;
-
-  ddValue =  (UINT32) (UINTN)pConfig;
-  dbReg = SB_ECMOS_REG08;
-
-  for ( i = 0; i <= 3; i++ ) {
-    WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
-    WriteIO (SB_IOMAP_REG73, AccWidthUint8, (UINT8*)&ddValue);
-    ddValue = (ddValue >> 8);
-    dbReg++;
-  }
-}
diff --git a/src/vendorcode/amd/cimx/sb900/Ec.c b/src/vendorcode/amd/cimx/sb900/Ec.c
deleted file mode 100644
index e830821ab7..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Ec.c
+++ /dev/null
@@ -1,128 +0,0 @@
-
-/**
- * @file
- *
- * Config Southbridge EC Controller
- *
- * Init EC features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-#ifndef NO_EC_SUPPORT
-
-/**
- * Config EC controller during power-on
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-ecPowerOnInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  //Enable config mode
-  EnterEcConfig ();
-
-  //Do settings for mailbox - logical device 0x09
-  RWEC8 (0x07, 0x00, 0x09);               //switch to device 9 (Mailbox)
-  RWEC8 (0x60, 0x00, (MailBoxPort >> 8));    //set MSB of Mailbox port
-  RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF));  //set LSB of Mailbox port
-  RWEC8 (0x30, 0x00, 0x01);               //;Enable Mailbox Registers Interface, bit0=1
-
-  if ( pConfig->BuildParameters.EcKbd == ENABLED) {
-    //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
-
-    //Disable LPC Decoding of port 60/64
-    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0);
-
-    //Enable logical device 0x07 (Keyboard controller)
-    RWEC8 (0x07, 0x00, 0x07);
-    RWEC8 (0x30, 0x00, 0x01);
-  }
-
-  if (isImcEnabled () && ( pConfig->BuildParameters.EcChannel0 == ENABLED)) {
-    //Logical device 0x03
-    RWEC8 (0x07, 0x00, 0x03);
-    RWEC8 (0x60, 0x00, 0x00);
-    RWEC8 (0x61, 0x00, 0x62);
-    RWEC8 (0x30, 0x00, 0x01);            //;Enable Device 3
-  }
-
-  //Enable EC (IMC) to generate SMI to BIOS
-  RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6);
-  ExitEcConfig ();
-}
-
-/**
- * Config EC controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-ecInitBeforePciEnum (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  AMDSBCFG*     pTmp;                                    // dummy code
-  pTmp = pConfig;
-}
-
-/**
- * Prepare EC controller to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-ecInitLatePost (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  AMDSBCFG*     pTmp;                                    // dummy code
-  pTmp = pConfig;
-}
-#endif
diff --git a/src/vendorcode/amd/cimx/sb900/EcFan.h b/src/vendorcode/amd/cimx/sb900/EcFan.h
deleted file mode 100644
index c3d0f361da..0000000000
--- a/src/vendorcode/amd/cimx/sb900/EcFan.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-
-void WriteECmsg (IN unsigned char  Address, IN unsigned char OpFlag, IN void* Value);
-void WaitForEcLDN9MailboxCmdAck (void);
-void ReadECmsg (IN unsigned char  Address, IN unsigned char OpFlag, OUT void* Value);
-
-// IMC Message Register Software Interface
-#define CPU_MISC_BUS_DEV_FUN  ((0x18 << 3) + 3)
-
-#define MSG_SYS_TO_IMC  0x80
-#define Fun_80  0x80
-#define Fun_81  0x81
-#define Fun_82  0x82
-#define Fun_83  0x83
-#define Fun_84  0x84
-#define Fun_85  0x85
-#define Fun_86  0x86
-#define Fun_87  0x87
-#define Fun_88  0x88
-#define Fun_89  0x89
-#define Fun_90  0x90
-#define MSG_IMC_TO_SYS  0x81
-#define MSG_REG0  0x82
-#define MSG_REG1  0x83
-#define MSG_REG2  0x84
-#define MSG_REG3  0x85
-#define MSG_REG4  0x86
-#define MSG_REG5  0x87
-#define MSG_REG6  0x88
-#define MSG_REG7  0x89
-#define MSG_REG8  0x8A
-#define MSG_REG9  0x8B
-#define MSG_REGA  0x8C
-#define MSG_REGB  0x8D
-#define MSG_REGC  0x8E
-#define MSG_REGD  0x8F
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/EcFanLib.c b/src/vendorcode/amd/cimx/sb900/EcFanLib.c
deleted file mode 100644
index 57feae17bd..0000000000
--- a/src/vendorcode/amd/cimx/sb900/EcFanLib.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/**
- * @file
- *
- * Southbridge EC IO access common routine
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-
-VOID
-ReadECmsg (
-  IN       UINT8 Address,
-  IN       UINT8 OpFlag,
-     OUT   VOID* Value
-  )
-{
- UINT8 i;
-
-  OpFlag = OpFlag & 0x7f;
-  if (OpFlag == 0x02) OpFlag = 0x03;
-  WriteIo8((UINT16) (0x3E), Address);  // EC_LDN9_MAILBOX_BASE_ADDRESS
-  i = ReadIo8((UINT16) (0x3F));   // EC_LDN9_MAILBOX_BASE_ADDRESS
-  *((UINT8*) (Value)) = i;
-}
-
-
-VOID
-WriteECmsg (
-  IN       UINT8 Address,
-  IN       UINT8 OpFlag,
-  IN       VOID* Value
-  )
-{
- UINT8 i;
-
-  OpFlag = OpFlag & 0x7f;
-  if (OpFlag == 0x02) OpFlag = 0x03;
-  WriteIo8(0x3E, Address);  // EC_LDN9_MAILBOX_BASE_ADDRESS
-  i = *(UINT8*)Value;
-  WriteIo8(0x3F, i);   // EC_LDN9_MAILBOX_BASE_ADDRESS
-}
-
-VOID
-WaitForEcLDN9MailboxCmdAck (
-  VOID
-  )
-{
-  UINT8 Msgdata;
-  UINT16 Delaytime;
-  Msgdata = 0;
-  for (Delaytime = 0; Delaytime <= 500; Delaytime++) {
-    ReadECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
-    if ( Msgdata == 0xfa) {
-      break;
-    }
-    cimSbStall (1000); // Wait for 1ms
-  }
-}
-
-/**
- * imcDisableSurebootTimer - IMC Disable Sureboot Timer.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-imcDisableSurebootTimer (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 Msgdata;
-
-  if (!(isImcEnabled ()) ) {
-    return; //IMC is not enabled
-  }
-  Msgdata = 0x00;
-  WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
-  Msgdata = 0x01;
-  WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
-  Msgdata = 0x00;
-  WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
-  Msgdata = 0x94;
-  WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
-  WaitForEcLDN9MailboxCmdAck ();
-}
-
-/**
- * imcDisarmSurebootTimer - IMC Disarm Sureboot Timer.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-imcDisarmSurebootTimer (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  imcDisableSurebootTimer (pConfig);
-  pConfig->imc.imcSureBootTimer = 0;
-}
-
-/**
- * imcEnableSurebootTimer - IMC Enable Sureboot Timer.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-imcEnableSurebootTimer (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 Msgdata;
-
-  imcDisableSurebootTimer (pConfig);
-
-  Msgdata = 0x00;
-  if (!(isImcEnabled ()) || (pConfig->imc.imcSureBootTimer == 0)) {
-    return; //IMC is not enabled
-  }
-  WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
-  Msgdata = 0x01;
-  WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
-  Msgdata = ( (pConfig->imc.imcSureBootTimer) << 6) -1;
-  WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
-  Msgdata = 0x94;
-  WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
-  WaitForEcLDN9MailboxCmdAck ();
-}
-
-/**
- * imcSleep - IMC Sleep.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-imcSleep (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 Msgdata;
-
-  if (!(isImcEnabled ()) ) {
-    return; //IMC is not enabled
-  }
-  Msgdata = 0x00;
-  WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
-  Msgdata = 0xB4;
-  WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
-  Msgdata = 0x00;
-  WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
-  Msgdata = 0x96;
-  WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
-  WaitForEcLDN9MailboxCmdAck ();
-}
-
-/**
- * imcWakeup - IMC Wakeup.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-imcWakeup (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 Msgdata;
-
-  if (!(isImcEnabled ()) ) {
-    return; //IMC is not enabled
-  }
-  Msgdata = 0x00;
-  WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
-  Msgdata = 0xB5;
-  WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
-  Msgdata = 0x00;
-  WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
-  Msgdata = 0x96;
-  WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
-  WaitForEcLDN9MailboxCmdAck ();
-}
-
-/**
- * imcIdle - IMC Idle.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-imcIdle (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 Msgdata;
-
-  if (!(isImcEnabled ()) ) {
-    return; //IMC is not enabled
-  }
-  Msgdata = 0x00;
-  WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
-  Msgdata = 0x01;
-  WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
-  Msgdata = 0x00;
-  WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
-  Msgdata = 0x98;
-  WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
-  WaitForEcLDN9MailboxCmdAck ();
-}
-
-VOID
-imcThermalZoneEnable (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8   Msgdata;
-  UINT8   ZoneNum;
-  BOOLEAN IsSendEcMsg;
-
-  if (!(isImcEnabled ()) ) {
-    return; //IMC is not enabled
-  }
-
-  for ( ZoneNum = 0; ZoneNum < 4; ZoneNum++ ) {
-    IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, 0, ZoneNum);
-    if (IsSendEcMsg) {
-      Msgdata = 0x00;
-      WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
-      Msgdata = ZoneNum;
-      WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
-      Msgdata = 0x80;
-      WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
-      WaitForEcLDN9MailboxCmdAck ();
-
-      Msgdata = 0x00;
-      WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
-      Msgdata = ZoneNum;
-      WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
-      ReadECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
-      Msgdata |= BIT0;
-      WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
-      Msgdata = 0x81;
-      WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
-      WaitForEcLDN9MailboxCmdAck ();
-    }
-  }
-}
-
diff --git a/src/vendorcode/amd/cimx/sb900/EcFanc.c b/src/vendorcode/amd/cimx/sb900/EcFanc.c
deleted file mode 100644
index 2cc8106b0e..0000000000
--- a/src/vendorcode/amd/cimx/sb900/EcFanc.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*;********************************************************************************
-;
-;Copyright (c) 2011, Advanced Micro Devices, Inc.
-;All rights reserved.
-;
-;Redistribution and use in source and binary forms, with or without
-;modification, are permitted provided that the following conditions are met:
-;    * Redistributions of source code must retain the above copyright
-;      notice, this list of conditions and the following disclaimer.
-;    * Redistributions in binary form must reproduce the above copyright
-;      notice, this list of conditions and the following disclaimer in the
-;      documentation and/or other materials provided with the distribution.
-;    * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;      its contributors may be used to endorse or promote products derived
-;      from this software without specific prior written permission.
-;
-;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-;ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-;DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-;(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-;LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-;ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-;(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-;SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-/**
- * Table for Function Number
- *
- *
- *
- *
- */
-UINT8 FunctionNumber[] =
-{
-  Fun_81,
-  Fun_83,
-  Fun_85,
-  Fun_89,
-};
-
-/**
- * Table for Max Thermal Zone
- *
- *
- *
- *
- */
-UINT8 MaxZone[] =
-{
-  4,
-  4,
-  4,
-  4,
-};
-
-/**
- * Table for Max Register
- *
- *
- *
- *
- */
-UINT8 MaxRegister[] =
-{
-  MSG_REG9,
-  MSG_REGB,
-  MSG_REG9,
-  MSG_REGA,
-};
-/*-------------------------------------------------------------------------------
-;Procedure:  IsZoneFuncEnable
-;
-;Description:  This routine will check every zone support function with BitMap from user define
-;
-;
-;Exit:  None
-;
-;Modified:  None
-;
-;-----------------------------------------------------------------------------
-*/
-BOOLEAN
-IsZoneFuncEnable (
-  IN     UINT16 Flag,
-  IN     UINT8  func,
-  IN     UINT8  Zone
-  )
-{
-  return (BOOLEAN) (((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone));
-}
-
-/*-------------------------------------------------------------------------------
-;Procedure:  sbECfancontrolservice
-;
-;Description:  This routine service EC fan policy
-;
-;
-;Exit:  None
-;
-;Modified:  None
-;
-;-----------------------------------------------------------------------------
-*/
-VOID
-sbECfancontrolservice (
-  IN     AMDSBCFG* pConfig
-  )
-{
-  UINT8 ZoneNum;
-  UINT8 FunNum;
-  UINT8 RegNum;
-  UINT8 * CurPoint;
-  UINT8 FunIndex;
-  BOOLEAN IsSendEcMsg;
-  if (!isImcEnabled ()) {
-    return; //IMC is not enabled
-  }
-
-  CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);
-  for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {
-    FunNum = FunctionNumber[FunIndex];
-    for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
-      IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
-      if (IsSendEcMsg) {
-        for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
-          WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
-          CurPoint += 1;
-        }
-        WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
-        WaitForEcLDN9MailboxCmdAck ();
-      } else {
-        CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
-      }
-    }
-  }
-  CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0;
-  for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {
-    FunNum = FunctionNumber[FunIndex];
-    for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
-      IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
-      if (IsSendEcMsg) {
-        for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
-          if (RegNum == MSG_REG2) {
-            *CurPoint &= 0xFE;
-          }
-          WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
-          CurPoint += 1;
-        }
-        WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
-        WaitForEcLDN9MailboxCmdAck ();
-      } else {
-        CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
-      }
-    }
-  }
-}
-
-/*-------------------------------------------------------------------------------
-;Procedure:  hwmImcInit
-;
-;Description:  This routine Init EC fan policy
-;
-;
-;Exit:  None
-;
-;Modified:  None
-;
-;-----------------------------------------------------------------------------
-*/
-VOID
-hwmImcInit (
-  IN     AMDSBCFG* pConfig
-  )
-{
-  imcWakeup ( pConfig);
-  if ( pConfig->hwm.hwmSbtsiAutoPoll == FALSE ) {
-    sbECfancontrolservice (pConfig);
-  }
-}
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/EcLib.c b/src/vendorcode/amd/cimx/sb900/EcLib.c
deleted file mode 100644
index 44e196b89d..0000000000
--- a/src/vendorcode/amd/cimx/sb900/EcLib.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/**
- * @file
- *
- * Southbridge EC IO access common routine
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-// #ifndef NO_EC_SUPPORT
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * EnterEcConfig - Force EC into Config mode
- *
- *
- *
- *
- */
-VOID
-EnterEcConfig (
-  )
-{
-  UINT16   dwEcIndexPort;
-
-  ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
-  dwEcIndexPort &= ~(BIT0);
-  RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * ExitEcConfig - Force EC exit Config mode
- *
- *
- *
- *
- */
-VOID
-ExitEcConfig (
-  )
-{
-  UINT16   dwEcIndexPort;
-
-  ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
-  dwEcIndexPort &= ~(BIT0);
-  RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * ReadEC8 - Read EC register data
- *
- *
- *
- * @param[in] Address  - EC Register Offset Value
- * @param[in] Value    - Read Data Buffer
- *
- */
-VOID
-ReadEC8 (
-  IN       UINT8 Address,
-  IN       UINT8* Value
-  )
-{
-  UINT16   dwEcIndexPort;
-
-  ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
-  dwEcIndexPort &= ~(BIT0);
-  WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
-  ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * WriteEC8 - Write date into EC register
- *
- *
- *
- * @param[in] Address  - EC Register Offset Value
- * @param[in] Value    - Write Data Buffer
- *
- */
-VOID
-WriteEC8 (
-  IN       UINT8 Address,
-  IN       UINT8* Value
-  )
-{
-  UINT16   dwEcIndexPort;
-
-  ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
-  dwEcIndexPort &= ~(BIT0);
-
-  WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
-  WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * RWEC8 - Read/Write EC register
- *
- *
- *
- * @param[in] Address    - EC Register Offset Value
- * @param[in] AndMask    - Data And Mask 8 bits
- * @param[in] OrMask     - Data OR Mask 8 bits
- *
- */
-VOID
-RWEC8 (
-  IN       UINT8 Address,
-  IN       UINT8 AndMask,
-  IN       UINT8 OrMask
-  )
-{
-  UINT8 Result;
-  ReadEC8 (Address, &Result);
-  Result = (Result & AndMask) | OrMask;
-  WriteEC8 (Address, &Result);
-}
-
-// #endif
-
diff --git a/src/vendorcode/amd/cimx/sb900/Gec.c b/src/vendorcode/amd/cimx/sb900/Gec.c
deleted file mode 100644
index cab95b5470..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Gec.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/**
- * @file
- *
- * Config Southbridge GEC controller
- *
- * Init GEC features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-
-/**
- * gecInitBeforePciEnum - Config GEC controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-gecInitBeforePciEnum (
-  IN       AMDSBCFG*   pConfig
-  )
-{
-  UINT8 cimSBGecDebugBus;
-  UINT8 cimSBGecPwr;
-
-  cimSBGecDebugBus = (UINT8) pConfig->SBGecDebugBus;
-  cimSBGecPwr = (UINT8) pConfig->SBGecPwr;
-#if  (SB_CIMx_PARAMETER == 0 )
-  cimSBGecDebugBus = cimSBGecDebugBusDefault;
-  cimSBGecPwr = cimSBGecPwrDefault;
-#endif
-  if ( pConfig->Cg2Pll == 1 ) {
-    pConfig->GecConfig = 1;
-  }
-  if ( pConfig->GecConfig == 0) {
-    // GEC Enabled
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, 0x00);
-
-    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG11, AccWidthUint8, 0, 0x00);
-    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG21, AccWidthUint8, 0, 0x01);
-    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG166, AccWidthUint8, 0, 0x01);
-    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG181, AccWidthUint8, 0, 0x01);
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF8, AccWidthUint8, ~(BIT5 + BIT6), (UINT8) ((cimSBGecPwr) << 5));
-
-    if (  cimSBGecDebugBus == 1) {
-      // GEC Debug Bus Enabled
-      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, BIT3);
-    } else {
-      // GEC Debug Bus Disabled
-      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, 0x00);
-    }
-  } else {
-    // GEC Disabled
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, BIT0);
-    //return;   //return if GEC controller is disabled.
-  }
-}
-
-/**
- * gecInitAfterPciEnum - Config GEC controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-gecInitAfterPciEnum (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  VOID* GecRomAddress;
-  VOID* GecShadowRomAddress;
-  UINT32 ddTemp;
-  if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) {
-    GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
-    GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
-    AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
-    ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp);
-    ddTemp = ddTemp & 0xFFFFFFF0;
-    RWMEM (ddTemp + 0x6804, AccWidthUint32, 0, BIT0 + BIT29);
-  }
-  TRACE ((DMSG_SB_TRACE, "Exiting gec Init after PCI emulation\n"));
-}
-
-/**
- * gecInitLatePost - Prepare GEC controller to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-gecInitLatePost (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  if ( !pConfig->GecConfig == 0) {
-    return;   //return if GEC controller is disabled.
-  }
-  TRACE ((DMSG_SB_TRACE, "Exiting Prepare GEC controller to boot to OS\n"));
-}
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/Gpp.c b/src/vendorcode/amd/cimx/sb900/Gpp.c
deleted file mode 100644
index 5bc6e18b4b..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Gpp.c
+++ /dev/null
@@ -1,1109 +0,0 @@
-
-/**
- * @file
- *
- * Config Southbridge GPP controller
- *
- * Init GPP features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*     * Redistributions of source code must retain the above copyright
-*       notice, this list of conditions and the following disclaimer.
-*     * Redistributions in binary form must reproduce the above copyright
-*       notice, this list of conditions and the following disclaimer in the
-*       documentation and/or other materials provided with the distribution.
-*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-*       its contributors may be used to endorse or promote products derived
-*       from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-****************************************************************************
-*/
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-
-/**
- * PCIE_CAP_ID - PCIe Cap ID
- *
- */
-#define  PCIE_CAP_ID             0x10
-
-//
-// Declaration of local functions
-//
-UINT8
-sbFindPciCap (
-  IN       UINT32  pciAddress,
-  IN       UINT8  targetCapId
-  );
-
-VOID
-sbGppSetAspm (
-  IN       UINT32    pciAddress,
-  IN       UINT8     LxState
-  );
-
-VOID
-sbGppSetEPAspm (
-  IN       UINT32    pciAddress,
-  IN       UINT8     LxState
-  );
-
-VOID
-sbGppValidateAspm (
-  IN       UINT32    pciAddress,
-  IN       UINT8     *LxState
-  );
-
-VOID
-sbGppForceGen2 (
-  IN       AMDSBCFG        *pConfig,
-  IN       CONST UINT8     ActivePorts
-  );
-
-VOID
-sbGppForceGen1 (
-  IN       AMDSBCFG      *pConfig,
-  IN       CONST UINT8   ActivePorts
-  );
-
-VOID
-PreInitGppLink (
-  IN       AMDSBCFG* pConfig
-  );
-
-UINT8
-GppPortPollingLtssm (
-  IN       AMDSBCFG*      pConfig,
-  IN       UINT8          ActivePorts,
-  IN       BOOLEAN        IsGen2
-  );
-
-UINT8
-CheckGppLinkStatus (
-  IN       AMDSBCFG* pConfig
-  );
-
-VOID
-AfterGppLinkInit (
-  IN       AMDSBCFG* pConfig
-  );
-
-VOID
-sbGppDynamicPowerSaving (
-  IN       AMDSBCFG* pConfig
-  );
-
-VOID
-sbGppAerInitialization (
-  IN       AMDSBCFG* pConfig
-  );
-
-VOID
-sbGppRasInitialization (
-  IN     AMDSBCFG*   pConfig
-  );
-
-//
-// Declaration of external functions
-//
-
-
-/**
- * sbFindPciCap - Find PCI Cap
- *
- *
- * @param[in] pciAddress     PCI Address.
- * @param[in] targetCapId    Target Cap ID.
- *
- */
-UINT8
-sbFindPciCap (
-  IN       UINT32  pciAddress,
-  IN       UINT8  targetCapId
-  )
-{
-  UINT8       NextCapPtr;
-  UINT8       CapId;
-
-  NextCapPtr = 0x34;
-  while (NextCapPtr != 0) {
-    ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &NextCapPtr);
-    if (NextCapPtr == 0xff) {
-      return 0;
-    }
-    if (NextCapPtr != 0) {
-      ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &CapId);
-      if (CapId == targetCapId) {
-        break;
-      } else {
-        NextCapPtr++;
-      }
-    }
-  }
-  return NextCapPtr;
-}
-
-/**
- * sbGppSetAspm - Set GPP ASPM
- *
- *
- * @param[in] pciAddress PCI Address.
- * @param[in] LxState    Lane State.
- *
- */
-VOID
-sbGppSetAspm (
-  IN       UINT32    pciAddress,
-  IN       UINT8     LxState
-  )
-{
-  UINT8      pcieCapOffset;
-  UINT8      value8;
-
-  pcieCapOffset = sbFindPciCap (pciAddress, PCIE_CAP_ID);
-  if (pcieCapOffset) {
-    // Read link capabilities register (0x0C[11:10] - ASPM support)
-    ReadPCI (pciAddress + pcieCapOffset + 0x0D, AccWidthUint8, &value8);
-    if (value8 & BIT2) {
-      value8 = (value8 >> 2) & (BIT1 + BIT0);
-      // Set ASPM state in link control register
-      RWPCI (pciAddress + pcieCapOffset + 0x10, AccWidthUint8, 0xffffffff, LxState & value8);
-    }
-  }
-}
-
-/**
- * sbGppSetEPAspm - Set EP GPP ASPM
- *
- *
- * @param[in] pciAddress PCI Address.
- * @param[in] LxState    Lane State.
- *
- */
-VOID
-sbGppSetEPAspm (
-  IN       UINT32    pciAddress,
-  IN       UINT8     LxState
-  )
-{
-  UINT8      value8;
-  UINT8      maxFuncs;
-  UINT32     devBDF;
-
-  maxFuncs = 1;
-  ReadPCI (pciAddress + 0x0E, AccWidthUint8, &value8);
-
-  if (value8 & BIT7) {
-    maxFuncs = 8;              // multi-function device
-  }
-  while (maxFuncs != 0) {
-    devBDF = pciAddress + (UINT32) ((maxFuncs - 1) << 16);
-    sbGppSetAspm (devBDF, LxState);
-    maxFuncs--;
-  }
-}
-
-/**
- * sbGppValidateAspm - Validate endpoint support for GPP ASPM
- *
- *
- * @param[in] pciAddress PCI Address.
- * @param[in] LxState    Lane State.
- *
- */
-VOID
-sbGppValidateAspm (
-  IN       UINT32    pciAddress,
-  IN       UINT8     *LxState
-  )
-{
-  UINT8      pcieCapOffset;
-  UINT8      value8;
-  UINT8      maxFuncs;
-  UINT32     devBDF;
-
-  maxFuncs = 1;
-  ReadPCI (pciAddress + 0x0E, AccWidthUint8, &value8);
-
-  if (value8 & BIT7) {
-    maxFuncs = 8;              // multi-function device
-  }
-  while (maxFuncs != 0) {
-    devBDF = pciAddress + (UINT32) ((maxFuncs - 1) << 16);
-    pcieCapOffset = sbFindPciCap (devBDF, PCIE_CAP_ID);
-    if (pcieCapOffset) {
-      // Read link capabilities register (0x0C[11:10] - ASPM support)
-      ReadPCI (devBDF + pcieCapOffset + 0x0D, AccWidthUint8, &value8);
-      if (value8 & BIT2) {
-        value8 = (value8 >> 2) & (BIT1 + BIT0);
-        // Set ASPM state as what's endpoint support
-        *LxState &= value8;
-      }
-    }
-    maxFuncs--;
-  }
-}
-
-
-/**
- * sbGppForceGen2 - Set GPP to Gen2
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- * @param[in] ActivePorts Activate Ports.
- *
- */
-VOID
-sbGppForceGen2 (
-  IN       AMDSBCFG        *pConfig,
-  IN       CONST UINT8     ActivePorts
-  )
-{
-  UINT32       portId;
-
-  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
-    if (ActivePorts & (1 << portId)) {
-      rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29 + BIT0);
-      rwAlink ((SB_ABCFG_REG340 + portId * 4) | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT21);
-      rwAlink (SB_RCINDXP_REGA2 | portId << 24, ~BIT13, 0);
-      rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0);
-      RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x02);
-
-      (&pConfig->PORTCONFIG[portId].PortCfg)->PortIsGen2 = 2;
-    }
-  }
-}
-
-/**
- * sbGppForceGen1 - Set GPP to Gen1
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- * @param[in] ActivePorts Activate Ports.
- *
- */
-VOID
-sbGppForceGen1 (
-  IN       AMDSBCFG      *pConfig,
-  IN       CONST UINT8   ActivePorts
-  )
-{
-  UINT32       portId;
-
-  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
-    if (ActivePorts & (1 << portId) && pConfig->GppHardwareDowngrade != portId + 1) {
-      rwAlink ((SB_ABCFG_REG340 + portId * 4) | (UINT32) (ABCFG << 29), ~BIT21, 0);
-      rwAlink (SB_RCINDXP_REGA4 | portId << 24, ~BIT0, BIT29);
-      rwAlink (SB_RCINDXP_REGA2 | portId << 24, 0xFFFFFFFF, BIT13);
-      rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0);
-      RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x01);
-
-      (&pConfig->PORTCONFIG[portId].PortCfg)->PortIsGen2 = 1;
-    }
-  }
-}
-
-
-/**
- * PreInitGppLink - Enable GPP link training.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-PreInitGppLink (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 portMask[5] = {
-    0x01,
-    0x00,
-    0x03,
-    0x07,
-    0x0F
-  };
-  UINT8  cfgMode;
-  UINT8  portId;
-  UINT32 reg32Value;
-  UINT16 tmp16Value;
-
-//  PCIE_GPP_ENABLE (abcfg:0xC0):
-//
-//     GPP_LINK_CONFIG ([3:0])  PortA   PortB   PortC   PortD    Description
-//    ----------------------------------------------------------------------------------
-//                       0000    0-3                             x4 Config
-//                       0001                                    N/A
-//                       0010    0-1     2-3      0              2:2 Config
-//                       0011    0-1      2       3              2:1:1 Config
-//                       0100     0       1       2       3      1:1:1:1 Config
-//
-//  For A12 and above:
-//                  ABCFG:0xC0[12] - Port A hold training (default 1)
-//                  ABCFG:0xC0[13] - Port B hold training (default 1)
-//                  ABCFG:0xC0[14] - Port C hold training (default 1)
-//                  ABCFG:0xC0[15] - Port D hold training (default 1)
-//
-//
-  //
-  // Set port enable bit fields based on current GPP link configuration mode
-  //
-  cfgMode = (UINT8) pConfig->GppLinkConfig;
-  if ( cfgMode > GPP_CFGMODE_X1111 || cfgMode == 1 ) {
-    cfgMode = GPP_CFGMODE_X4000;
-    pConfig->GppLinkConfig = GPP_CFGMODE_X4000;
-  }
-  reg32Value = (UINT32) portMask[cfgMode];
-
-  // Mask out non-applicable ports according to the target link configuration mode
-  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
-    pConfig->PORTCONFIG[portId].PortCfg.PortPresent &= (reg32Value >> portId) & BIT0;
-  }
-
-  //
-  // Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
-  //
-  tmp16Value = (UINT16) (~reg32Value << 12);
-  reg32Value = (UINT32) (tmp16Value + (reg32Value << 4) + cfgMode);
-  writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), reg32Value);
-
-  reg32Value = readAlink (0xC0 | (UINT32) (RCINDXC << 29));
-  writeAlink (0xC0 | (UINT32) (RCINDXC << 29), reg32Value | 0x400);  // Set STRAP_F0_MSI_EN
-
-  // A-Link L1 Entry Delay Shortening
-  // AXINDP_Reg 0xA0[7:4] = 0x3
-  rwAlink (SB_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30);
-  rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19);
-  rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28);
-
-  // RPR5.22 GPP L1 Entry Delay Shortening
-  // RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request.
-  // This is done to reduce number of NAK received with L1 enabled.
-  // ENH254401: Program L0S/L1 activity timer to enable L0S/L1 on GPP
-  // RCINDP_Reg 0xA0[11:8] = 0x9
-  // RCINDP_Reg 0xA0[15:12] = 0x6
-  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
-    rwAlink (SB_RCINDXP_REGA0 | portId << 24, 0xFFFF000F, 0x6910);
-    //OBS220313: Hard System Hang running MeatGrinder Test on multiple blocks
-    //RPR 5.13 GPP Error Reporting Configuration
-    rwAlink (SB_RCINDXP_REG6A | portId << 24, ~(BIT1), 0);
-  }
-
-  if (pConfig->S3Resume) {
-    SBGPPPORTCONFIG  *portCfg;
-
-    for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
-      portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
-      if (portCfg->PortHotPlug == TRUE) {
-        portCfg->PortDetected = FALSE;
-      } else {
-        if (portCfg->PortIsGen2 == 1) {
-          sbGppForceGen1 (pConfig, (UINT8) (1 << portId));
-        } else {
-          sbGppForceGen2 (pConfig, (UINT8) (1 << portId));
-        }
-      }
-    }
-  }
-
-  // Obtain original Gen2 strap value (LC_GEN2_EN_STRAP)
-  pConfig->GppGen2Strap = (UINT8) (readAlink (SB_RCINDXP_REGA4 | 0 << 24) & BIT0);
-}
-
-
-/**
- * GppPortPollingLtssm - Loop polling the LTSSM for each GPP port marked in PortMap
- *
- *
- * Return:     FailedPortMap   = A bitmap of ports which failed to train
- *
- * @param[in]    pConfig      Southbridge configuration structure pointer.
- * @param[in]    ActivePorts  A bitmap of ports which should be polled
- * @param[in]    IsGen2       TRUE if the polling is in Gen2 mode
- *
- */
-UINT8
-GppPortPollingLtssm (
-  IN       AMDSBCFG*      pConfig,
-  IN       UINT8          ActivePorts,
-  IN       BOOLEAN        IsGen2
-  )
-{
-  UINT32            retryCounter;
-  UINT8             PortId;
-  UINT8             FailedPorts;
-  SBGPPPORTCONFIG  *portCfg;
-  UINT32            abIndex;
-  UINT32            Data32;
-  UINT8             EmptyPorts;
-
-  FailedPorts = 0;
-  retryCounter = MAX_LT_POLLINGS;
-  EmptyPorts = ActivePorts;
-
-  while (retryCounter-- && ActivePorts) {
-    for (PortId = 0; PortId < MAX_GPP_PORTS; PortId++) {
-      if (ActivePorts & (1 << PortId)) {
-        portCfg = &pConfig->PORTCONFIG[PortId].PortCfg;
-        abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (PortId << 24);
-        Data32 = readAlink (abIndex) & 0x3F3F3F3F;
-
-        if ((UINT8) (Data32) > 0x04) {
-          EmptyPorts &= ~(1 << PortId);
-        }
-
-        if ((UINT8) (Data32) == 0x10) {
-          ActivePorts &= ~(1 << PortId);
-          portCfg->PortDetected = TRUE;
-          break;
-        }
-        if (IsGen2) {
-          UINT8      i;
-
-          for (i = 0; i < 4; i++) {
-            if ((UINT8) (Data32) == 0x29 || (UINT8) (Data32) == 0x2A ) {
-              ActivePorts &= ~(1 << PortId);
-              FailedPorts |= (1 << PortId);
-              break;
-            }
-            Data32 >>= 8;
-          }
-        }
-      }
-    }
-    if (EmptyPorts && retryCounter < (MAX_LT_POLLINGS - 200)) {
-      ActivePorts &= ~EmptyPorts;
-    }
-    SbStall (1000);
-  }
-  FailedPorts |= ActivePorts;
-  return FailedPorts;
-}
-
-
-/**
- * CheckGppLinkStatus - loop polling the link status for each GPP port
- *
- *
- * Return:     ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-UINT8
-CheckGppLinkStatus (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32            portId;
-  UINT8             portScanMap;
-  UINT8             GppHwDowngrade;
-  SBGPPPORTCONFIG  *portCfg;
-  UINT8             FailedPorts;
-
-
-  portScanMap = 0;
-  FailedPorts = 0;
-
-  // Obtain a list of ports to be checked
-  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
-    portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
-    if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) {
-      portScanMap |= 1 << portId;
-    }
-  }
-  GppHwDowngrade = (UINT8)pConfig->GppHardwareDowngrade;
-  if (GppHwDowngrade != 0) {
-    // Skip polling and always assume this port to be present
-    portScanMap &= ~(1 << (GppHwDowngrade - 1));
-  }
-
-  //GPP Gen2 Speed Change
-  // if ((GPP Gen2 == enabled) and (RCINDP_Reg 0xA4[0] == 0x1)) {
-  //   PCIe_Cfg 0x88[3:0]  = 0x2
-  //   RCINDP_Reg 0xA2[13] = 0x0
-  //   RCINDP_Reg 0xC0[15] = 0x0
-  //   RCINDP_Reg 0xA4[29] = 0x1
-  // } else {
-  //   PCIe_Cfg 0x88[3:0]  = 0x1
-  //   RCINDP_Reg 0xA4[0]  = 0x0
-  //   RCINDP_Reg 0xA2[13] = 0x1
-  //   RCINDP_Reg 0xC0[15] = 0x0
-  //   RCINDP_Reg 0xA4[29] = 0x1
-  // }
-  SbStall (5000);
-  if (pConfig->GppGen2 && pConfig->GppGen2Strap) {
-    sbGppForceGen2 (pConfig, portScanMap);
-    FailedPorts = GppPortPollingLtssm (pConfig, portScanMap, TRUE);
-
-    if (FailedPorts) {
-      sbGppForceGen1 (pConfig, FailedPorts);
-      FailedPorts = GppPortPollingLtssm (pConfig, FailedPorts, FALSE);
-    }
-  } else {
-    sbGppForceGen1 (pConfig, portScanMap);
-    FailedPorts = GppPortPollingLtssm (pConfig, portScanMap, FALSE);
-  }
-  return FailedPorts;
-}
-
-
-/**
- * AfterGppLinkInit
- *       - Search for display device behind each GPP port
- *       - If the port is empty AND not hotplug-capable:
- *           * Turn off link training
- *           * (optional) Power down the port
- *           * Hide the configuration space (Turn off the port)
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-AfterGppLinkInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32           portId;
-  SBGPPPORTCONFIG  *portCfg;
-  UINT32           regBusNumber;
-  UINT32           abValue;
-  UINT32           abIndex;
-  UINT8            bValue;
-  UINT8            cimGppGen2;
-
-  cimGppGen2 = pConfig->GppGen2;
-#if  SB_CIMx_PARAMETER == 0
-  cimGppGen2 = cimGppGen2Default;
-#endif
-
-  pConfig->GppFoundGfxDev = 0;
-  abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
-  //RPR 5.9 Link Bandwidth Notification Capability Enable
-  //RCINDC:0xC1[0] = 1
-  rwAlink (SB_RCINDXC_REGC1, 0xFFFFFFFF, BIT0);
-
-  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
-    // Program requester ID for every port
-    abIndex = SB_RCINDXP_REG21 | (UINT32) (RCINDXP << 29) | (portId << 24);
-    writeAlink (abIndex, (SB_GPP_DEV << 3) + portId);
-
-    //RPR 5.9 Link Bandwidth Notification Capability Enable
-    //PCIe Cfg 0x68[10] = 0
-    //PCIe Cfg 0x68[11] = 0
-    RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x68), AccWidthUint16, ~(BIT10 + BIT11), 0);
-
-    portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
-    // Check if there is GFX device behind each GPP port
-    if ( portCfg->PortDetected == TRUE ) {
-      regBusNumber = (SBTEMP_BUS << 16) + (SBTEMP_BUS << 8);
-      WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, &regBusNumber);
-      // *** Stall ();
-      ReadPCI (PCI_ADDRESS (SBTEMP_BUS, 0, 0, 0x0B), AccWidthUint8, &bValue);
-      if ( bValue == 3 ) {
-        pConfig->GppFoundGfxDev |= (1 << portId);
-      }
-      regBusNumber = 0;
-      WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, &regBusNumber);
-    } else if ( portCfg->PortPresent == FALSE || portCfg->PortHotPlug == FALSE ) {
-      // Mask off non-applicable ports
-      abValue &= ~(1 << (portId + 4));
-    }
-
-    if ( portCfg->PortHotPlug == TRUE ) {
-      // RPR5.12 Hot Plug: PCIe Native Support
-      // RCINDP_Reg 0x10[3] = 0x1
-      // PCIe_Cfg 0x5A[8] = 0x1
-      // PCIe_Cfg 0x6C[6] = 0x1
-      // RCINDP_Reg 0x20[19] = 0x0
-      rwAlink ((SB_RCINDXP_REG10 | (UINT32) (RCINDXP << 29) | (portId << 24)), 0xFFFFFFFF, BIT3);
-      RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x5b), AccWidthUint8, 0xff, BIT0);
-      RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x6c), AccWidthUint8, 0xff, BIT6);
-      rwAlink ((SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24)), ~BIT19, 0);
-    }
-  }
-  if ( pConfig->GppUnhidePorts == FALSE ) {
-    if ((abValue & 0xF0) == 0) {
-      abValue = BIT8;         // if all ports are empty set GPP_RESET
-    } else if ((abValue & 0xE0) != 0 && (abValue & 0x10) == 0) {
-      abValue |= BIT4;        // PortA should always be visible whenever other ports are exist
-    }
-
-    // Update GPP_Portx_Enable (abcfg:0xC0[7:5])
-    writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), abValue);
-  }
-
-  //
-  // Common initialization for open GPP ports
-  //
-  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
-    ReadPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue);
-    if (bValue != 0xff) {
-      // Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0])
-      bValue &= 0xf0;
-      bValue |= 0x06;
-      WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue);
-
-        // Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1
-      abIndex = SB_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (portId << 24);
-      abValue = readAlink (abIndex) | BIT19;
-      writeAlink (abIndex, abValue);
-
-        // Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0
-      abIndex = SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24);
-      abValue = readAlink (abIndex) & ~BIT19;
-      writeAlink (abIndex, abValue);
-
-        // Set Immediate Ack PM_Active_State_Request_L1 (0xA0:[23]) = 0
-      abIndex = SB_RCINDXP_REGA0 | (UINT32) (RCINDXP << 29) | (portId << 24);
-      abValue = readAlink (abIndex) & ~BIT23;
-      if ( pConfig->L1ImmediateAck == 0) {
-        abValue |= BIT23;
-      }
-      writeAlink (abIndex, abValue);
-    }
-  }
-}
-
-
-/**
- * sbPcieGppLateInit - Late PCIE initialization for Hudson-2 GPP component
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbPcieGppLateInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8            portId;
-  UINT8            busNum;
-  UINT8            aspmValue;
-  UINT8            PortaspmValue;
-  UINT8            reg8Value;
-  UINT8            cimGppPhyPllPowerDown;
-  SBGPPPORTCONFIG  *portCfg;
-  UINT32           reg32Value;
-
-  // Disable hidden register decode and serial number capability
-  reg32Value = readAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29));
-  writeAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29), reg32Value & ~(BIT26 + BIT10));
-
-  if (readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)) & BIT8) {
-    return;
-  }
-
-  //
-  // Configure ASPM
-  //
-  //  writeAlink (0xC0 | (UINT32) (RCINDXC << 29), 0x400);  // Set STRAP_F0_MSI_EN
-  aspmValue = (UINT8)pConfig->GppPortAspm;
-  cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown;
-#if  SB_CIMx_PARAMETER == 0
-  aspmValue = cimGppPortAspmDefault;
-  cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault;
-#endif
-
-  reg8Value = 0x01;
-  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
-    // write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under Vista
-    // when native PCIE is enabled but MSI is not available
-    // SB02029: Hudson-2 BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg
-    portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
-    if (portCfg->PortHotPlug) {
-      RWPCI (PCI_ADDRESS (0, 21, portId, 0x04), AccWidthUint8, 0xFE, 0x00);  //clear IO enable to fix possible hotplug hang
-    }
-    WritePCI (PCI_ADDRESS (0, 21, portId, 0x3d), AccWidthUint8, &reg8Value);
-    ReadPCI (PCI_ADDRESS (0, 21, portId, 0x19), AccWidthUint8, &busNum);
-    if (busNum != 0xFF) {
-      ReadPCI (PCI_ADDRESS (busNum, 0, 0, 0x00), AccWidthUint32, &reg32Value);
-      if (reg32Value != 0xffffffff) {
-        PortaspmValue = aspmValue;
-        // Vlidate if EP support ASPM
-        sbGppValidateAspm (PCI_ADDRESS (busNum, 0, 0, 0), &PortaspmValue);
-        // Set ASPM on EP side
-        sbGppSetEPAspm (PCI_ADDRESS (busNum, 0, 0, 0), PortaspmValue);
-        // Set ASPM on port side
-        sbGppSetAspm (PCI_ADDRESS (0, 21, portId, 0), PortaspmValue);
-      }
-    }
-    rwAlink ((SB_RCINDXP_REG02 | (UINT32) (RCINDXP << 29) | (portId << 24) ), ~(BIT15), (BIT15));
-  }
-  rwAlink ((SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29)), ~(BIT0), (BIT0));
-
-  //
-  // Configure Lock HWInit registers
-  //
-  reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
-  if (reg32Value & 0xF0) {
-    reg32Value = readAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29));
-    writeAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), reg32Value | BIT0);  // Set HWINIT_WR_LOCK
-
-    if ( cimGppPhyPllPowerDown == TRUE ) {
-      //
-      // RPR 5.4 Power Saving Feature for GPP Lanes
-      //
-      UINT32  abValue;
-
-      // Set PCIE_P_CNTL in Alink PCIEIND space
-      abValue = readAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29));
-      abValue |= BIT12 + BIT3 + BIT0;
-      abValue &= ~(BIT9 + BIT4);
-      writeAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), abValue);
-      rwAlink (SB_RCINDXC_REG02, ~(BIT8), (BIT8));
-      rwAlink (SB_RCINDXC_REG02, ~(BIT3), (BIT3));
-    }
-  }
-
-  // Restore strap0 via override
-  if (pConfig->PcieAER) {
-    rwAlink (SB_ABCFG_REG310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7);
-    rwAlink (RC_INDXC_REGC0, 0xFFFFFFFF, BIT9);
-  }
-}
-
-
-/**
- * sbGppDynamicPowerSaving - RPR 5.19 GPP Dynamic Power Saving
- *
- *
- * @param[in] pConfig
- *
- */
-VOID
-sbGppDynamicPowerSaving (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  SBGPPPORTCONFIG  *portCfg;
-  UINT8            cimGppLaneReversal;
-  UINT8            cimAlinkPhyPllPowerDown;
-  UINT8            cimGppPhyPllPowerDown;
-  UINT32           Data32;
-  UINT32           HoldData32;
-  UINT32           abValue;
-
-  if (!pConfig->GppDynamicPowerSaving || pConfig->sdbEnable) {
-    return;
-  }
-
-  cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown;
-  cimGppLaneReversal =  (UINT8) pConfig->GppLaneReversal;
-  cimGppPhyPllPowerDown =  (UINT8) pConfig->GppPhyPllPowerDown;
-#if  SB_CIMx_PARAMETER == 0
-  cimGppLaneReversal = cimGppLaneReversalDefault;
-  cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault;
-  cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault;
-#endif
-  if (pConfig->GppHardwareDowngrade) {
-    portCfg = &pConfig->PORTCONFIG[pConfig->GppHardwareDowngrade - 1].PortCfg;
-    portCfg->PortDetected = TRUE;
-  }
-
-  Data32 = 0;
-  HoldData32 = 0;
-  switch ( pConfig->GppLinkConfig ) {
-  case GPP_CFGMODE_X4000:
-    portCfg = &pConfig->PORTCONFIG[0].PortCfg;
-    if ( portCfg->PortDetected == FALSE ) {
-      Data32 |= 0x0f0f;
-      HoldData32 |= 0x1000;
-    }
-    break;
-  case GPP_CFGMODE_X2200:
-    portCfg = &pConfig->PORTCONFIG[0].PortCfg;
-    if ( portCfg->PortDetected == FALSE ) {
-      Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303;
-      HoldData32 |= 0x1000;
-    }
-    portCfg = &pConfig->PORTCONFIG[1].PortCfg;
-    if ( portCfg->PortDetected == FALSE ) {
-      Data32 |= ( cimGppLaneReversal )? 0x0303:0x0c0c;
-      HoldData32 |= 0x2000;
-    }
-    break;
-  case GPP_CFGMODE_X2110:
-    portCfg = &pConfig->PORTCONFIG[0].PortCfg;
-    if ( portCfg->PortDetected == FALSE ) {
-      Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303;
-      HoldData32 |= 0x1000;
-    }
-    portCfg = &pConfig->PORTCONFIG[1].PortCfg;
-    if ( portCfg->PortDetected == FALSE ) {
-      Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404;
-      HoldData32 |= 0x2000;
-    }
-    portCfg = &pConfig->PORTCONFIG[2].PortCfg;
-    if ( portCfg->PortDetected == FALSE ) {
-      Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808;
-      HoldData32 |= 0x4000;
-    }
-    break;
-  case GPP_CFGMODE_X1111:
-    portCfg = &pConfig->PORTCONFIG[0].PortCfg;
-    if ( portCfg->PortDetected == FALSE ) {
-      Data32 |= ( cimGppLaneReversal )? 0x0808:0x0101;
-      HoldData32 |= 0x1000;
-    }
-    portCfg = &pConfig->PORTCONFIG[1].PortCfg;
-    if ( portCfg->PortDetected == FALSE ) {
-      Data32 |= ( cimGppLaneReversal )? 0x0404:0x0202;
-      HoldData32 |= 0x2000;
-    }
-    portCfg = &pConfig->PORTCONFIG[2].PortCfg;
-    if ( portCfg->PortDetected == FALSE ) {
-      Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404;
-      HoldData32 |= 0x4000;
-    }
-    portCfg = &pConfig->PORTCONFIG[3].PortCfg;
-    if ( portCfg->PortDetected == FALSE ) {
-      Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808;
-      HoldData32 |= 0x8000;
-    }
-    break;
-  default:
-    break;
-  }
-
-  // RPR 5.11 Power Saving With GPP Disable
-  // ABCFG 0xC0[8] = 0x0
-  // ABCFG 0xC0[15:12] = 0xF
-  // Enable "Power Saving Feature for A-Link Express Lanes"
-  // Enable "Power Saving Feature for GPP Lanes"
-  // ABCFG 0x90[19] = 1
-  // ABCFG 0x90[6] = 1
-  // RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF
-  // ABCFG 0xC0[7:4] = 0x0
-  if ( cimAlinkPhyPllPowerDown && cimGppPhyPllPowerDown ) {
-    abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
-    writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), (( abValue | HoldData32 ) & (~ BIT8 )));
-    rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));
-    rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19));
-    rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, ((Data32 & 0x0F) == 0x0F) ? Data32 | 0x0CFF0000 : Data32);
-    rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));
-  }
-}
-
-
-/**
- * sbGppAerInitialization - Initializing AER
- *
- *
- * @param[in] pConfig
- *
- */
-VOID
-sbGppAerInitialization (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8    PortId;
-  UINT32   ValueDd;
-
-  if (pConfig->PcieAER) {
-    // GPP strap configuration
-    rwAlink (SB_ABCFG_REG310 | (UINT32) (ABCFG << 29), ~(BIT7 + BIT4), BIT28 + BIT27 + BIT26 + BIT1);
-    rwAlink (SB_ABCFG_REG314 | (UINT32) (ABCFG << 29), ~(UINT32) (0xfff << 15), 0);
-
-    for (PortId = 0; PortId < MAX_GPP_PORTS; PortId++) {
-      ReadPCI (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x00), AccWidthUint32, &ValueDd);
-      if (ValueDd != 0xffffffff) {
-        rwAlink ((SB_RCINDXP_REG6A | (UINT32) (RCINDXP << 29) | (PortId << 24)), ~BIT1, 0);
-        rwAlink ((SB_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (PortId << 24)), 0xFFFFE000, 0);
-      }
-    }
-
-    rwAlink (SB_RCINDXC_REG10, ~(BIT18 + BIT21 + BIT22), 0);
-
-    // AB strap configuration
-    rwAlink (SB_ABCFG_REGF0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT15 + BIT14);
-    rwAlink (SB_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT3);
-
-    // Enable GPP function0 error reporting
-    rwAlink (SB_ABCFG_REG310 | (UINT32) (ABCFG << 29), ~BIT7, BIT7);
-    rwAlink (SB_RCINDXC_REGC0, ~BIT9, BIT9);
-  } else {
-    //OBS220313: Hard System Hang running MeatGrinder Test on multiple blocks
-    //RPR 5.13 GPP Error Reporting Configuration
-    rwAlink (SB_ABCFG_REGF0 | (UINT32) (ABCFG << 29), ~(BIT1), 0);
-    //rwAlink (SB_ABCFG_REG310 | (UINT32) (ABCFG << 29), ~BIT7, 0);
-    //rwAlink (SB_RCINDXC_REGC0, ~BIT8, 0);
-  }
-  //RPR 5.13 GPP Error Reporting Configuration
-  rwAlink (SB_ABCFG_REGB8 | (UINT32) (ABCFG << 29), ~(BIT8 + BIT24 + BIT25 + BIT26 + BIT28), BIT8 + BIT24 + BIT26 + BIT28);
-}
-
-/**
- * sbGppRasInitialization - Initializing RAS
- *
- *
- * @param[in] pConfig
- *
- */
-VOID
-sbGppRasInitialization (
-  IN     AMDSBCFG*   pConfig
-  )
-{
-  if (pConfig->PcieRAS) {
-    rwAlink (SB_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT0);
-  }
-}
-
-
-//
-//-----------------------------------------------------------------------------------
-// Early Hudson-2 GPP initialization sequence:
-//
-// 1) Set port enable bit fields by current GPP link configuration mode
-// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
-// 3) Loop polling for the link status of all ports
-// 4) Misc operations after link training:
-//      - (optional) Detect GFX device
-//      - Hide empty GPP configuration spaces (Disable empty GPP ports)
-//      - (optional) Power down unused GPP ports
-//      - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0])
-// 5) GPP init completed
-//
-//
-// *) Gen2 vs Gen1
-//                                   Gen2 mode     Gen1 mode
-//  ---------------------------------------------------------------
-//    STRAP_PHY_PLL_CLKF[6:0]          7'h32         7'h19
-//    STRAP_BIF_GEN2_EN                  1             0
-//
-//    PCIE_PHY_PLL clock locks @       5GHz
-//
-//
-
-/**
- * GPP early programming and link training. On exit all populated EPs should be fully operational.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbPcieGppEarlyInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32           reg32Value;
-  UINT8            cimNbSbGen2;
-  UINT8            cimGppMemWrImprove;
-  UINT8            cimGppLaneReversal;
-  UINT8            cimAlinkPhyPllPowerDown;
-  UINT32           abValue;
-
-  cimNbSbGen2 = pConfig->NbSbGen2;
-  cimGppMemWrImprove = pConfig->GppMemWrImprove;
-  cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal;
-  cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown;
-#if  SB_CIMx_PARAMETER == 0
-  cimNbSbGen2 = cimNbSbGen2Default;
-  cimGppMemWrImprove = cimGppMemWrImproveDefault;
-  cimGppLaneReversal = cimGppLaneReversalDefault;
-  cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault;
-#endif
-
-  outPort80 (0x90);
-  //
-  // Configure NB-SB link PCIE PHY PLL power down for L1
-  //
-  if ( cimAlinkPhyPllPowerDown == TRUE ) {
-    // Set PCIE_P_CNTL in Alink PCIEIND space
-    writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40);
-    abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29));
-    abValue |= BIT12 + BIT3 + BIT0;
-    abValue &= ~(BIT9 + BIT4);
-    writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue);
-    rwAlink (SB_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~(BIT8), (BIT8));
-    rwAlink (SB_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~(BIT3), (BIT3));
-  }
-
-  // AXINDC_Reg 0xA4[18] = 0x1
-  writeAlink (SB_AX_INDXP_REG38 | (UINT32) (AXINDP << 29), 0xA4);
-  abValue = readAlink (SB_AX_DATAP_REG3C | (UINT32) (AXINDP << 29));
-  abValue |= BIT18;
-  writeAlink (SB_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), abValue);
-
-
-  //
-  // Set ABCFG 0x031C[0] = 1 to enable lane reversal
-  //
-  reg32Value = readAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29));
-  if ( cimGppLaneReversal ) {
-    writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | BIT0);
-  } else {
-    writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | 0x00);
-  }
-  //
-  // Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function
-  //
-  reg32Value = readAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29));
-  writeAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), reg32Value | BIT20);
-
-
-  //
-  // Initialize and configure GPP
-  //
-  if (pConfig->GppFunctionEnable) {
-    sbGppTogglePcieReset (pConfig);
-
-    // PreInit - Enable GPP link training
-    PreInitGppLink (pConfig);
-
-    //
-    // GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1
-    // GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4
-    //
-    if ( cimGppMemWrImprove == TRUE ) {
-      rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~BIT26, (BIT26));
-      rwAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12));
-    }
-
-    if (CheckGppLinkStatus (pConfig) && !pConfig->S3Resume) {
-      // Toggle GPP reset (Note this affects all Hudson-2 GPP ports)
-      sbGppTogglePcieReset (pConfig);
-    }
-
-    // Misc operations after link training
-    AfterGppLinkInit (pConfig);
-
-
-    sbGppAerInitialization (pConfig);
-    sbGppRasInitialization (pConfig);
-  }
-  sbGppDynamicPowerSaving (pConfig);
-  outPort80 (0x9F);
-}
-
diff --git a/src/vendorcode/amd/cimx/sb900/GppHp.c b/src/vendorcode/amd/cimx/sb900/GppHp.c
deleted file mode 100644
index d87b904fd1..0000000000
--- a/src/vendorcode/amd/cimx/sb900/GppHp.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- * @file
- *
- * Config Southbridge GPP controller
- *
- * Init GPP features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*     * Redistributions of source code must retain the above copyright
-*       notice, this list of conditions and the following disclaimer.
-*     * Redistributions in binary form must reproduce the above copyright
-*       notice, this list of conditions and the following disclaimer in the
-*       documentation and/or other materials provided with the distribution.
-*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-*       its contributors may be used to endorse or promote products derived
-*       from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-****************************************************************************
-*/
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-
-//
-// Declaration of external functions
-//
-VOID  sbGppDynamicPowerSaving (IN AMDSBCFG* pConfig );
-VOID  sbGppForceGen1 (IN AMDSBCFG* pConfig, IN CONST UINT8 ActivePorts);
-VOID  sbGppForceGen2 (IN AMDSBCFG* pConfig, IN CONST UINT8 ActivePorts);
-UINT8 GppPortPollingLtssm (IN AMDSBCFG* pConfig, IN UINT8 ActivePorts, IN BOOLEAN IsGen2);
-
-
-/**
- * GPP hot plug handler
- *
- *
- * @param[in] pConfig   Southbridge configuration structure pointer.
- * @param[in] HpPort    The hot plug port number.
- *
- */
-static VOID
-sbGppHotPlugSmiProcess (
-  IN       AMDSBCFG*     pConfig,
-  IN       UINT32        HpPort
-  )
-{
-  UINT8         FailedPort;
-
-  // First restore GPP pads if needed
-  if (pConfig->GppDynamicPowerSaving && pConfig->AlinkPhyPllPowerDown && pConfig->GppPhyPllPowerDown) {
-    rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), 0);
-    rwAlink (RC_INDXC_REG65, ~(UINT32) (0x101 << HpPort), 0);
-    SbStall (1000);
-  }
-
-  FailedPort = (UINT8) (1 << HpPort);
-  if (pConfig->GppGen2 && pConfig->GppGen2Strap) {
-    if (GppPortPollingLtssm (pConfig, FailedPort, TRUE)) {
-      sbGppForceGen1 (pConfig, FailedPort);
-      FailedPort = GppPortPollingLtssm (pConfig, FailedPort, FALSE);
-    }
-  } else {
-    sbGppForceGen1 (pConfig, FailedPort);
-    FailedPort = GppPortPollingLtssm (pConfig, FailedPort, FALSE);
-  }
-}
-
-
-/**
- * GPP hot-unplug handler
- *
- *
- * @param[in] pConfig   Southbridge configuration structure pointer.
- * @param[in] HpPort    The hot plug port number.
- *
- */
-static VOID
-sbGppHotUnplugSmiProcess (
-  IN       AMDSBCFG*     pConfig,
-  IN       UINT32        HpPort
-  )
-{
-  pConfig->PORTCONFIG[HpPort].PortCfg.PortDetected = FALSE;
-
-  if (pConfig->GppGen2 && pConfig->GppGen2Strap) {
-    sbGppForceGen2 (pConfig, (UINT8) (1 << HpPort));
-  }
-
-  // 5.19.1 GPP Power Saving with Hot Unplug
-  if (pConfig->GppDynamicPowerSaving && pConfig->AlinkPhyPllPowerDown && pConfig->GppPhyPllPowerDown) {
-    rwAlink (SB_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), BIT17);
-    rwAlink (SB_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT8), BIT8);
-    rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), (1 << (12 + HpPort)));
-    rwAlink (SB_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), 0);
-
-    // Finally re-configure GPP pads if needed
-    sbGppDynamicPowerSaving (pConfig);
-  }
-}
-
-
-/**
- * SMI handler for GPP hot-plug
- *
- *
- * @param[in] pConfig     Southbridge configuration structure pointer.
- * @param[in] IsPlugged   Is a card currently plugged in the GPP port?
- *
- */
-VOID
-sbGppHotplugSmiCallback (
-  IN       AMDSBCFG* pConfig,
-  IN       BOOLEAN   IsPlugged
-  )
-{
-  UINT32           portNum;
-  UINT32           HpPort;
-
-  if (!pConfig->GppFunctionEnable) {
-    return;
-  }
-
-  HpPort = 0xff;
-  for (portNum = 0; portNum < MAX_GPP_PORTS; portNum++) {
-    if (pConfig->PORTCONFIG[portNum].PortCfg.PortHotPlug == TRUE) {
-      HpPort = portNum;
-      break;
-    }
-  }
-  if (HpPort == 0xff) {
-    return;
-  }
-
-  if (IsPlugged) {
-    outPort80 (0x9C);
-    sbGppHotPlugSmiProcess (pConfig, HpPort);
-  } else {
-    outPort80 (0x9D);
-    sbGppHotUnplugSmiProcess (pConfig, HpPort);
-  }
-}
-
diff --git a/src/vendorcode/amd/cimx/sb900/Hudson-2.h b/src/vendorcode/amd/cimx/sb900/Hudson-2.h
deleted file mode 100644
index f13f1f72ce..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Hudson-2.h
+++ /dev/null
@@ -1,2068 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#pragma pack (push, 1)
-
-#define CIMX_SB_REVISION       "1.0.0.2"
-#define CIMX_SB_ID             "HDN2A13"
-#define SBCIMx_Version         0x1002
-
-
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page SB_POWERON_INIT_Page SB_POWERON_INIT
- *  @section SB_POWERON_INIT Interface Call
- *  Initialize structure referenced by AMDSBCFG to default recommended value.
- *  @subsection SB_POWERON_INIT_CallIn Call Prototype
- *  @par
- *     sbPowerOnInit ((AMDSBCFG*) pConfig) (Followed PH Interface)
- *  @subsection SB_BEFORE_PCI_INIT_CallID Service ID
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SB_POWERON_INIT   --> 0x00010001 </TD></TR>
- *  </TABLE>
- *  @subsection SB_POWERON_INIT_CallOut Prepare for Callout
- *  @par
- *     Not Applicable (Not necessary for the current implementation)
- *  @subsection SB_POWERON_INIT_Config Prepare for Configuration Data.
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::BiosSize </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::LegacyFree </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::EcKbd </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::WatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::GecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::CpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *  </TABLE>
- *
- */
-#define SB_POWERON_INIT             0x00010001
-#define OUTDEBUG_PORT               0x00010002
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page SB_BEFORE_PCI_INIT_Page SB_BEFORE_PCI_INIT
- *  @section SB_BEFORE_PCI_INIT Interface Call
- *  Initialize structure referenced by AMDSBCFG to default recommended value.
- *  @subsection SB_BEFORE_PCI_INIT_CallIn Call Prototype
- *  @par
- *     sbBeforePciInit ((AMDSBCFG*)pConfig) (Followed PH Interface)
- *  @subsection SB_BEFORE_PCI_INIT_CallID Service ID
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_INIT  --> 0x00010010 </TD></TR>
- *  </TABLE>
- *  @subsection SB_BEFORE_PCI_INIT_CallOut Prepare for Callout
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR>
- *     <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR>
- *  </TABLE>
- *  @subsection SB_BEFORE_PCI_INIT_Config Prepare for Configuration Data.
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *  </TABLE>
- *
- */
-#define SB_BEFORE_PCI_INIT          0x00010010
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page SB_AFTER_PCI_INIT_Page SB_AFTER_PCI_INIT
- *  @section SB_AFTER_PCI_INIT Interface Call
- *  Initialize structure referenced by AMDSBCFG to default recommended value.
- *  @subsection SB_AFTER_PCI_INIT_CallIn Call Prototype
- *  @par
- *     sbAfterPciInit ((AMDSBCFG*)pConfig)     (Followed PH Interface)
- *  @subsection SB_AFTER_PCI_INIT_CallID Service ID
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SB_AFTER_PCI_INIT --> 0x00010020 </TD></TR>
- *  </TABLE>
- *  @subsection SB_AFTER_PCI_INIT_CallOut Prepare for Callout
- *  @par
- *    Not Applicable (Not necessary for the current implementation)
- *  @subsection SB_AFTER_PCI_INIT_Config Prepare for Configuration Data.
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *  </TABLE>
- *
- */
-#define SB_AFTER_PCI_INIT           0x00010020
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page SB_MID_POST_INIT_Page SB_MID_POST_INIT
- *  @section SB_MID_POST_INIT Interface Call
- *  Initialize structure referenced by AMDSBCFG to default recommended value.
- *  @subsection SB_MID_POST_INIT_CallIn Call Prototype
- *  @par
- *     sbMidPostInit ((AMDSBCFG*)pConfig)     (Followed PH Interface)
- *  @subsection SB_MID_POST_INIT_CallID Service ID
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SB_MID_POST_INIT  --> 0x00010021 </TD></TR>
- *  </TABLE>
- *  @subsection SB_MID_POST_INIT_CallOut Prepare for Callout
- *  @par
- *    Not Applicable (Not necessary for the current implementation)
- *  @subsection SB_MID_POST_INIT_Config Prepare for Configuration Data.
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *  </TABLE>
- *
- */
-#define SB_MID_POST_INIT           0x00010021
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page SB_LATE_POST_INIT_Page SB_LATE_POST_INIT
- *  @section SB_LATE_POST_INIT Interface Call
- *  Initialize structure referenced by AMDSBCFG to default recommended value.
- *  @subsection SB_LATE_POST_INIT_CallIn Call Prototype
- *  @par
- *     sbLatePost ((AMDSBCFG*)pConfig)     (Followed PH Interface)
- *  @subsection SB_LATE_POST_INIT_CallID Service ID
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SB_LATE_POST_INIT  --> 0x00010030 </TD></TR>
- *  </TABLE>
- *  @subsection SB_LATE_POST_INIT_CallOut Prepare for Callout
- *  @par
- *    Not Applicable (Not necessary for the current implementation)
- *  @subsection SB_LATE_POST_INIT_Config Prepare for Configuration Data.
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *  </TABLE>
- *
- */
-#define SB_LATE_POST_INIT           0x00010030
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page SB_BEFORE_PCI_RESTORE_INIT_Page SB_BEFORE_PCI_RESTORE_INIT
- *  @section SB_BEFORE_PCI_RESTORE_INIT Interface Call
- *  Initialize structure referenced by AMDSBCFG to default recommended value.
- *  @subsection SB_BEFORE_PCI_RESTORE_INIT_CallIn Call Prototype
- *  @par
- *     sbBeforePciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface)
- *  @subsection SB_BEFORE_PCI_RESTORE_INIT_CallID Service ID
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_RESTORE_INIT  --> 0x00010040 </TD></TR>
- *  </TABLE>
- *  @subsection SB_BEFORE_PCI_RESTORE_INIT_CallOut Prepare for Callout
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR>
- *     <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR>
- *  </TABLE>
- *  @subsection SB_BEFORE_PCI_RESTORE_INIT_Config Prepare for Configuration Data.
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *  </TABLE>
- *
- */
-#define SB_BEFORE_PCI_RESTORE_INIT  0x00010040
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page SB_AFTER_PCI_RESTORE_INIT_Page SB_AFTER_PCI_RESTORE_INIT
- *  @section SB_AFTER_PCI_RESTORE_INIT Interface Call
- *  Initialize structure referenced by AMDSBCFG to default recommended value.
- *  @subsection SB_AFTER_PCI_RESTORE_INIT_CallIn Call Prototype
- *  @par
- *     sbAfterPciRestoreInit ((AMDSBCFG*)pConfig)     (Followed PH Interface)
- *  @subsection SB_AFTER_PCI_RESTORE_INIT_CallID Service ID
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SB_AFTER_PCI_RESTORE_INIT  --> 0x00010050 </TD></TR>
- *  </TABLE>
- *  @subsection SB_AFTER_PCI_RESTORE_INIT_CallOut Prepare for Callout
- *  @par
- *    Not Applicable (Not necessary for the current implementation)
- *  @subsection SB_AFTER_PCI_RESTORE_INIT_Config Prepare for Configuration Data.
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *     <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
- *  </TABLE>
- *
- */
-#define SB_AFTER_PCI_RESTORE_INIT   0x00010050
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page SB_SMM_SERVICE_Page SB_SMM_SERVICE
- *  @section SB_SMM_SERVICE Interface Call
- *  Initialize structure referenced by AMDSBCFG to default recommended value.
- *  @subsection SB_SMM_SERVICE_CallIn Call Prototype
- *  @par
- *     sbSmmService ((AMDSBCFG*)pConfig)     (Followed PH Interface)
- *  @subsection SB_SMM_SERVICE_CallID Service ID
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SB_SMM_SERVICE  --> 0x00010060 </TD></TR>
- *  </TABLE>
- *  @subsection SB_SMM_SERVICE_CallOut Prepare for Callout
- *  @par
- *    Not Applicable (Not necessary for the current implementation)
- *  @subsection SB_SMM_SERVICE_Config Prepare for Configuration Data.
- *  @par
- *     Not necessary on current implementation
- *
- */
-#define SB_SMM_SERVICE              0x00010060
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page SB_SMM_ACPION_Page SB_SMM_ACPION
- *  @section SB_SMM_ACPION Interface Call
- *  Initialize structure referenced by AMDSBCFG to default recommended value.
- *  @subsection SB_SMM_ACPION_CallIn Call Prototype
- *  @par
- *     sbSmmAcpiOn ((AMDSBCFG*)pConfig)     (Followed PH Interface)
- *  @subsection SB_SMM_ACPION_CallID Service ID
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> SB_SMM_ACPION  --> 0x00010061 </TD></TR>
- *  </TABLE>
- *  @subsection SB_SMM_ACPION_CallOut Prepare for Callout
- *  @par
- *    Not Applicable (Not necessary for the current implementation)
- *  @subsection SB_SMM_ACPION_Config Prepare for Configuration Data.
- *  @par
- *     Not necessary on current implementation
- *
- */
-#define SB_SMM_ACPION               0x00010061
-
-#define SB_EC_FANCONTROL            0x00010070
-
-#ifndef OEM_CALLBACK_BASE
-  #define OEM_CALLBACK_BASE         0x00010100
-#endif
-
-//0x00 - 0x0F callback functions are reserved for bootblock
-#define SATA_PHY_PROGRAMMING        OEM_CALLBACK_BASE + 0x10
-#define PULL_UP_PULL_DOWN_SETTINGS  OEM_CALLBACK_BASE + 0x20
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
- *  @section CB_SBGPP_RESET_ASSERT Interface Call
- *  Initialize structure referenced by AMDSBCFG to default recommended value.
- *  @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT  --> 0x00010130 </TD></TR>
- *  </TABLE>
- *  @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data.
- *  @par
- *     Not necessary on current implementation
- *
- */
-#define CB_SBGPP_RESET_ASSERT       OEM_CALLBACK_BASE + 0x30
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
- *  @section CB_SBGPP_RESET_DEASSERT  Interface Call
- *  Initialize structure referenced by AMDSBCFG to default recommended value.
- *  @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID
- *  @par
- *  <TABLE border="0">
- *     <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT   --> 0x00010131 </TD></TR>
- *  </TABLE>
- *  @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data.
- *  @par
- *     Not necessary on current implementation
- *
- */
-#define CB_SBGPP_RESET_DEASSERT     OEM_CALLBACK_BASE + 0x31
-
-#define CFG_ADDR_PORT               0xCF8
-#define CFG_DATA_PORT               0xCFC
-
-#define ALINK_ACCESS_INDEX          0x0CD8
-#define ALINK_ACCESS_DATA           ALINK_ACCESS_INDEX + 4
-
-/*------------------------------------------------------------------
-; I/O Base Address - Should be set by host BIOS
-;------------------------------------------------------------------ */
-#define DELAY_PORT                  0x0E0
-
-/*------------------------------------------------------------------
-; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display
-;------------------------------------------------------------------ */
-// ASIC VendorID and DeviceIDs
-#define AMD_SB_VID                  0x1022
-#define SB_DEVICE_ID                0x780B
-#define SB_SATA_VID                 AMD_SB_VID      // Dev 17 Func 0
-#define SB_SATA_DID                 0x7800
-#define SB_SATA_AHCI_DID            0x7801
-#define SB_SATA_RAID_DID            0x7802
-#define SB_SATA_RAID5_DID           0x7803
-#define SB_SATA_AMDAHCI_DID         0x7804
-#define SB_USB_OHCI_VID             AMD_SB_VID      // Dev 18 Func 0, Dev 19 Func 0
-#define SB_USB_OHCI_DID             0x7807
-#define SB_USB_EHCI_VID             AMD_SB_VID      // Dev 18 Func 2, Dev 19 Func 2
-#define SB_USB_EHCI_DID             0x7808
-#define SB_USB_XHCI_VID             AMD_SB_VID      // Dev 10 Func 0, Dev 10 Func 1
-#define SB_USB_XHCI_DID             0x7812
-#define SB_SMBUS_VID                AMD_SB_VID      // Dev 20 Func 0
-#define SB_SMBUS_DID                0x780B
-#define SB_IDE_VID                  AMD_SB_VID      // Dev 20 Func 1
-#define SB_IDE_DID                  0x780C
-#define SB_AZALIA_VID               AMD_SB_VID      // Dev 20 Func 2
-#define SB_AZALIA_DID               0x780D
-#define SB_LPC_VID                  AMD_SB_VID      // Dev 20 Func 3
-#define SB_LPC_DID                  0x780E
-#define SB_PCIB_VID                 AMD_SB_VID      // Dev 20 Func 4
-#define SB_PCIB_DID                 0x780F
-#define SB_USB_OHCIF_VID            AMD_SB_VID      // dev 20 Func 5
-#define SB_USB_OHCIF_DID            0x7809
-#define SB_NIC_VID                  0x14E4          // Dev 20 Func 6
-#define SB_NIC_DID                  0x1699
-#define SB_SD_VID                   AMD_SB_VID      // Dev 20 Func 7
-#define SB_SD_DID                   0x7806
-
-//FCH Variant
-#define FCH_Variant_EFUSE_LOCATION     0x1E    // EFUSE bit 240-247
-
-#define FCH_M2                            0x01
-#define FCH_M3                            0x03
-#define FCH_M3T                           0x07
-#define FCH_D2                            0x0F
-#define FCH_D3                            0x1F
-#define FCH_D4                            0x3F
-
-//Misc
-#define AMD_SB_A11                        0x11
-#define AMD_SB_A12                        0x12
-#define AMD_SB_A13                        0x13
-#define ACPI_SMI_CMD_PORT                 0xB0
-#define ACPI_SMI_DATA_PORT                0xB1
-#define R_SB_ACPI_PM1_STATUS              0x00
-#define R_SB_ACPI_PM1_ENABLE              0x02
-#define R_SB_ACPI_PM_CONTROL              0x04
-#define R_SB_ACPI_EVENT_STATUS            0x20
-#define R_SB_ACPI_EVENT_ENABLE            0x24
-#define R_SB_PM_ACPI_PMA_CNT_BLK_LO       0x2C
-
-//#define SATA_BUS_DEV_FUN_FPGA            0x228
-#define SATA_BUS_DEV_FUN            ((0x11 << 3) + 0)
-#define SB_SATA1_BUS        0
-#define SB_SATA1_DEV        17
-#define SB_SATA1_FUNC       0
-
-#define FC_BUS_DEV_FUN              ((0x11 << 3) + 1)
-#define SB_XHCI_BUS        0
-#define SB_XHCI_DEV        16
-#define SB_XHCI_FUNC       0
-#define USB_XHCI_BUS_DEV_FUN        ((SB_XHCI_DEV << 3) + SB_XHCI_FUNC)
-#define SB_XHCI1_BUS        0
-#define SB_XHCI1_DEV        16
-#define SB_XHCI1_FUNC       1
-#define USB_XHCI1_BUS_DEV_FUN       ((SB_XHCI1_DEV << 3) + SB_XHCI1_FUNC)
-#define USB1_OHCI_BUS_DEV_FUN       ((0x12 << 3) + 0)    // PORT 0-4
-#define SB_OHCI1_BUS        0
-#define SB_OHCI1_DEV        18
-#define SB_OHCI1_FUNC       0
-#define USB2_OHCI_BUS_DEV_FUN       ((0x13 << 3) + 0)    // PORT 5-9
-#define SB_OHCI2_BUS        0
-#define SB_OHCI2_DEV        19
-#define SB_OHCI2_FUNC       0
-#define USB3_OHCI_BUS_DEV_FUN       ((0x16 << 3) + 0)    // PORT 10-13
-#define SB_OHCI3_BUS        0
-#define SB_OHCI3_DEV        22
-#define SB_OHCI3_FUNC       0
-#define USB1_EHCI_BUS_DEV_FUN       ((0x12 << 3) + 2)    // PORT 0-4
-#define SB_EHCI1_BUS        0
-#define SB_EHCI1_DEV        18
-#define SB_EHCI1_FUNC       2
-#define USB2_EHCI_BUS_DEV_FUN       ((0x13 << 3) + 2)    // PORT 5-9
-#define SB_EHCI2_BUS        0
-#define SB_EHCI2_DEV        19
-#define SB_EHCI2_FUNC       2
-#define USB3_EHCI_BUS_DEV_FUN       ((0x16 << 3) + 2)  // PORT 10-13
-#define SB_EHCI3_BUS        0
-#define SB_EHCI3_DEV        22
-#define SB_EHCI3_FUNC       2
-#define SMBUS_BUS_DEV_FUN           ((0x14 << 3) + 0)
-#define SB_ISA_BUS          0
-#define SB_ISA_DEV          20
-#define SB_ISA_FUNC         0
-#define IDE_BUS_DEV_FUN             ((0x14 << 3) + 1)
-#define SB_IDE_BUS          0
-#define SB_IDE_DEV          20
-#define SB_IDE_FUNC         1
-#define AZALIA_BUS_DEV_FUN          ((0x14 << 3) + 2)
-#define SB_AZALIA_BUS       0
-#define SB_AZALIA_DEV       20
-#define SB_AZALIA_FUNC      2
-#define LPC_BUS_DEV_FUN             ((0x14 << 3) + 3)
-#define SB_LPC_BUS          0
-#define SB_LPC_DEV          20
-#define SB_LPC_FUNC         3
-#define PCIB_BUS_DEV_FUN            ((0x14 << 3) + 4)    // P2P in SB700
-#define SB_PCI_BUS          0
-#define SB_PCI_DEV          20
-#define SB_PCI_FUNC         4
-#define USB4_OHCI_BUS_DEV_FUN       ((0x14 << 3) + 5)    // PORT FL0 - FL1
-#define SB_OHCI4_BUS        0
-#define SB_OHCI4_DEV        20
-#define SB_OHCI4_FUNC       5
-//Gigabyte Ethernet Controller
-#define GEC_BUS_DEV_FUN             ((0x14 << 3) + 6)
-#define SB_GBEC_BUS         0
-#define SB_GBEC_DEV         20
-#define SB_GBEC_FUNC        6
-
-#define SD_BUS_DEV_FUN            ((0x14 << 3) + 7)    // SD in SB900
-#define SD_PCI_BUS          0
-#define SD_PCI_DEV          20
-#define SD_PCI_FUNC         7
-#define SD_PCI_REG00        0x00
-#define SD_PCI_REG2C        0x2C
-#define SD_PCI_REGA4        0xA4
-#define SD_PCI_REGB0        0xB0
-
-
-#define SB_GPP_BUS          0
-#define SB_GPP_DEV          21
-#define SB_GPP_FUNC         0
-#define GPP0_BUS_DEV_FUN            ((0x15 << 3) + 0)    // GPP P2P bridge PORT0
-#define GPP1_BUS_DEV_FUN            ((0x15 << 3) + 1)    // GPP P2P bridge PORT1
-#define GPP2_BUS_DEV_FUN            ((0x15 << 3) + 2)    // GPP P2P bridge PORT2
-#define GPP3_BUS_DEV_FUN            ((0x15 << 3) + 3)    // GPP P2P bridge PORT3
-
-#define ACPI_MMIO_BASE  0xFED80000
-#define SB_CFG_BASE     0x000   // DWORD
-#define GPIO_BASE       0x100   // BYTE
-#define SMI_BASE        0x200   // DWORD
-#define PMIO_BASE       0x300   // DWORD
-#define PMIO2_BASE      0x400   // BYTE
-#define BIOS_RAM_BASE   0x500   // BYTE
-#define CMOS_RAM_BASE   0x600   // BYTE
-#define CMOS_BASE       0x700   // BYTE
-#define ASF_BASE        0x900   // DWORD
-#define SMBUS_BASE      0xA00   // DWORD
-#define WATCHDOG_BASE   0xB00   // ??
-#define HPET_BASE       0xC00   // DWORD
-#define IOMUX_BASE      0xD00   // BYTE
-#define MISC_BASE       0xE00
-#define SERIAL_DEBUG_BASE  0x1000
-#define GFX_DAC_BASE       0x1400
-#define CEC_BASE           0x1800
-#define XHCI_BASE          0x1C00
-
-
-// RegSpace field (AB_INDEX[31:29]
-#define AXINDC         0               // AXINDC
-#define AXINDP         2               // AXINDP
-#define ABCFG          6               // ABCFG
-#define AXCFG          4               // AXCFG
-#define RCINDXC        1               // PCIEIND
-#define RCINDXP        3               // PCIEIND_P
-
-#define SBTEMP_BUS       8
-#define GPP_DEV_NUM    21              //?? Code style different
-#define MAX_GPP_PORTS  4
-#ifndef TRUE
-  #define TRUE         1
-#endif
-#ifndef FALSE
-  #define FALSE        0
-#endif
-//
-// ABCFG Registers
-//
-#define PCIE_FORCE_GEN1_EFUSE_LOCATION     0x14    // EFUSE bit 160
-
-#define SB_ABCFG_REG00     0x00  // VENDOR ID
-#define SB_ABCFG_REG08     0x08  // REVISION ID
-#define SB_ABCFG_REG40     0x40  // BL_EVENTCNT0LO
-#define SB_ABCFG_REG44     0x44  // BL_EVENTCNT1LO
-#define SB_ABCFG_REG48     0x48  // BL_EVENTCNTSEL
-#define SB_ABCFG_REG4A     0x4A  // BL_EVENTCNT0HI
-#define SB_ABCFG_REG4B     0x4B  // BL_EVENTCNT1HI
-#define SB_ABCFG_REG4C     0x4C  // BL_EVENTCNTCTL
-#define SB_ABCFG_REG50     0x50  // MISCCTL_50
-#define SB_ABCFG_REG54     0x54  // MISCCTL_54
-#define SB_ABCFG_REG58     0x58  // BL RAB CONTROL
-
-#define SB_ABCFG_REG60     0x60  // LINKWIDTH_CTL
-#define SB_ABCFG_REG64     0x64  // LINKWIDTH_UP_INTERVAL
-#define SB_ABCFG_REG68     0x68  // LINKWIDTH_DN_INVERVAL
-#define SB_ABCFG_REG6C     0x6C  // LINKWIDTH_UPSTREAM_DWORDS
-#define SB_ABCFG_REG70     0x70  // LINKWIDTH_DOWNSTREAM_DWORDS
-#define SB_ABCFG_REG74     0x74  // LINKWIDTH_THRESHOLD_INCREASE
-#define SB_ABCFG_REG78     0x78  // LINKWIDTH_THRESHOLD_DECREASE
-
-#define SB_ABCFG_REG80     0x80  // BL DMA PREFETCH CONTROL
-#define SB_ABCFG_REG88     0x88  //
-#define SB_ABCFG_REG8C     0x8C  //
-#define SB_ABCFG_REG90     0x90  // BIF CONTROL 0
-#define SB_ABCFG_REG94     0x94  // MSI CONTROL
-#define SB_ABCFG_REG98     0x98  // BIF CONTROL 1
-#define SB_ABCFG_REG9C     0x9C  // MISCCTL_9C
-#define SB_ABCFG_REGA0     0xA0  // BIF PHY CONTROL ENABLE
-#define SB_ABCFG_REGA4     0xA4  // BIF PHY CONTROL A4
-#define SB_ABCFG_REGA8     0xA8  // BIF PHY CONTROL A8
-#define SB_ABCFG_REGB0     0xB0  // HYPERFLASH-PCIE PORT MAPPING
-#define SB_ABCFG_REGB4     0xB4  //
-#define SB_ABCFG_REGB8     0xB8  //
-#define SB_ABCFG_REGC0     0xC0  // PCIE_GPP_ENABLE
-#define SB_ABCFG_REGC4     0xC4  // PCIE_P2P_INT_MAP
-#define SB_ABCFG_REGD0     0xD0  // MCTP_VDM_TX_FIFO_DATA
-#define SB_ABCFG_REGD4     0xD4  // MCTP_VMD_TX_CONTROL
-#define SB_ABCFG_REGE0     0xE0  // MCTP_VDM_RX_FIFO_DATA
-#define SB_ABCFG_REGE4     0xE4  // MCTP_VDM_RX_FIFO_STATUS
-#define SB_ABCFG_REGEC     0xEC  // MCTP_VDM_CONTROL
-#define SB_ABCFG_REGF0     0xF0  // GPP_UPSTREAM_CONTROL
-#define SB_ABCFG_REGF4     0xF4  // GPP_SYSTEM_ERROR_CONTROL
-#define SB_ABCFG_REGFC     0xFC  // SB_TRAP_CONTROL
-#define SB_ABCFG_REG100    0x100 // SB_TRAP0_ADDRL
-#define SB_ABCFG_REG104    0x104 // SB_TRAP0_ADDRH
-#define SB_ABCFG_REG108    0x108 // SB_TRAP0_CMD
-#define SB_ABCFG_REG10C    0x10C // SB_TRAP1_DATA
-#define SB_ABCFG_REG110    0x110 // SB_TRAP1_ADDRL
-#define SB_ABCFG_REG114    0x114 // SB_TRAP1_ADDRH
-#define SB_ABCFG_REG118    0x118 // SB_TRAP1_CMD
-#define SB_ABCFG_REG11C    0x11C // SB_TRAP1_DATA
-#define SB_ABCFG_REG120    0x120 // SB_TRAP2_ADDRL
-#define SB_ABCFG_REG124    0x124 // SB_TRAP2_ADDRH
-#define SB_ABCFG_REG128    0x128 // SB_TRAP2_CMD
-#define SB_ABCFG_REG12C    0x12C // SB_TRAP2_DATA
-#define SB_ABCFG_REG130    0x130 // SB_TRAP3_ADDRL
-#define SB_ABCFG_REG134    0x134 // SB_TRAP3_ADDRH
-#define SB_ABCFG_REG138    0x138 // SB_TRAP3_CMD
-#define SB_ABCFG_REG13C    0x13C // SB_TRAP3_DATA
-#define SB_ABCFG_REG300    0x300 // MCTP_VDM_RX_SMI_CONTROL
-#define SB_ABCFG_REG310    0x310 // BIF_GPP_STRAP_SYSTEM_0
-#define SB_ABCFG_REG314    0x314 // BIF_GPP_STRAP_SYSTEM_1
-#define SB_ABCFG_REG31C    0x31C // BIF_GPP_STRAP_LINK_CONTROL_0
-#define SB_ABCFG_REG320    0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A
-#define SB_ABCFG_REG324    0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B
-#define SB_ABCFG_REG328    0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C
-#define SB_ABCFG_REG32C    0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D
-#define SB_ABCFG_REG330    0x330 // BIF_GPP_STRAP_BIF_0
-#define SB_ABCFG_REG334    0x334 // BIF_GPP_STRAP_BIF_1
-#define SB_ABCFG_REG338    0x338 // BIF_GPP_STRAP_BIF_2
-#define SB_ABCFG_REG340    0x340 // BIF_GPP_STRAP_BIF_LANE_A
-#define SB_ABCFG_REG344    0x344 // BIF_GPP_STRAP_BIF_LANE_B
-#define SB_ABCFG_REG348    0x348 // BIF_GPP_STRAP_BIF_LANE_C
-#define SB_ABCFG_REG34C    0x34C // BIF_GPP_STRAP_BIF_LANE_D
-#define SB_ABCFG_REG350    0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0
-#define SB_ABCFG_REG354    0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1
-#define SB_ABCFG_REG404    0x404 // GPP0_SHADOW_COMMAND
-#define SB_ABCFG_REG418    0x418 // GPP0_SHADOW_BUS_NUMBER
-#define SB_ABCFG_REG41C    0x41C // GPP0_SHADOW_IO_LIMIT_BASE
-#define SB_ABCFG_REG420    0x420 // GPP0_SHADOW_MEM_LIMIT_BASE
-#define SB_ABCFG_REG424    0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE
-#define SB_ABCFG_REG428    0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER
-#define SB_ABCFG_REG42C    0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER
-#define SB_ABCFG_REG430    0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER
-#define SB_ABCFG_REG43C    0x43C // GPP0_SHADOW_BRIDGE_CONTROL
-#define SB_ABCFG_REG444    0x444 // GPP1_SHADOW_COMMAND
-#define SB_ABCFG_REG458    0x458 // GPP1_SHADOW_BUS_NUMBER
-#define SB_ABCFG_REG45C    0x45C // GPP1_SHADOW_IO_LIMIT_BASE
-#define SB_ABCFG_REG460    0x460 // GPP1_SHADOW_MEM_LIMIT_BASE
-#define SB_ABCFG_REG464    0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE
-#define SB_ABCFG_REG468    0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER
-#define SB_ABCFG_REG46C    0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER
-#define SB_ABCFG_REG470    0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER
-#define SB_ABCFG_REG47C    0x47C // GPP1_SHADOW_BRIDGE_CONTROL
-#define SB_ABCFG_REG484    0x484 // GPP2_SHADOW_COMMAND
-#define SB_ABCFG_REG498    0x498 // GPP2_SHADOW_BUS_NUMBER
-#define SB_ABCFG_REG49C    0x49C // GPP2_SHADOW_IO_LIMIT_BASE
-#define SB_ABCFG_REG4A0    0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE
-#define SB_ABCFG_REG4A4    0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE
-#define SB_ABCFG_REG4A8    0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER
-#define SB_ABCFG_REG4AC    0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER
-#define SB_ABCFG_REG4B0    0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER
-#define SB_ABCFG_REG4BC    0x4BC // GPP2_SHADOW_BRIDGE_CONTROL
-#define SB_ABCFG_REG4C4    0x4C4 // GPP3_SHADOW_COMMAND
-#define SB_ABCFG_REG4D8    0x4D8 // GPP3_SHADOW_BUS_NUMBER
-#define SB_ABCFG_REG4DC    0x4DC // GPP3_SHADOW_IO_LIMIT_BASE
-#define SB_ABCFG_REG4E0    0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE
-#define SB_ABCFG_REG4E4    0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE
-#define SB_ABCFG_REG4E8    0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER
-#define SB_ABCFG_REG4EC    0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER
-#define SB_ABCFG_REG4F0    0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER
-#define SB_ABCFG_REG4FC    0x4FC // GPP3_SHADOW_BRIDGE_CONTROL
-#define SB_ABCFG_REG10040  0x10040  // AL_EVENTCNT0LO
-#define SB_ABCFG_REG10044  0x10044  // AL_EVENTCNT1LO
-#define SB_ABCFG_REG10048  0x10048  // AL_EVENTCNTSEL
-#define SB_ABCFG_REG1004A  0x1004A  // AL_EVENTCNT0HI
-#define SB_ABCFG_REG1004B  0x1004B  // AL_EVENTCNT1HI
-#define SB_ABCFG_REG1004C  0x1004C  // AL_EVENTCNTCTL
-#define SB_ABCFG_REG10050  0x10050  // MISCCTL_10050
-#define SB_ABCFG_REG10054  0x10054  // AL_ARB_CTL
-#define SB_ABCFG_REG10056  0x10056  // AL_CLK_CTL
-#define SB_ABCFG_REG10058  0x10058  // AL RAB CONTROL
-#define SB_ABCFG_REG1005C  0x1005C  // AL MLT CONTROL
-#define SB_ABCFG_REG10060  0x10060  // AL DMA PREFETCH ENABLE
-#define SB_ABCFG_REG10064  0x10064  // AL DMA PREFETCH FLUSH CONTROL
-#define SB_ABCFG_REG10068  0x10068  // AL PREFETCH LIMIT
-#define SB_ABCFG_REG1006C  0x1006C  // AL DMA PREFETCH CONTROL
-#define SB_ABCFG_REG10070  0x10070  // MISCCTL_10070
-#define SB_ABCFG_REG10080  0x10080  // CLKMUXSTATUS
-#define SB_ABCFG_REG10090  0x10090  // BIF CONTROL 0
-#define SB_ABCFG_REG1009C  0x1009C  // MISCCTL_1009C
-
-//
-// RCINDX_P Registers
-//
-#define SB_RCINDXP_REG01   0x01 | RCINDXP << 29 // PCIEP_SCRATCH
-#define SB_RCINDXP_REG02   0x02 | RCINDXP << 29 //
-#define SB_RCINDXP_REG10   0x10 | RCINDXP << 29 //
-#define SB_RCINDXP_REG20   0x20 | RCINDXP << 29 // PCIE_TX_CNTL
-#define SB_RCINDXP_REG21   0x21 | RCINDXP << 29 // PCIE_TX_REQUESTER_ID
-#define SB_RCINDXP_REG50   0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS
-#define SB_RCINDXP_REG6A   0x6A | RCINDXP << 29 //
-#define SB_RCINDXP_REG70   0x70 | RCINDXP << 29 // PCIE_RX_CNTL
-#define SB_RCINDXP_REGA0   0xA0 | RCINDXP << 29 // PCIE_LC_CNTL
-#define SB_RCINDXP_REGA1   0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL
-#define SB_RCINDXP_REGA2   0xA2 | RCINDXP << 29 //
-#define SB_RCINDXP_REGA4   0xA4 | RCINDXP << 29 //
-#define SB_RCINDXP_REGA5   0xA5 | RCINDXP << 29 // PCIE_LC_STATE0
-#define SB_RCINDXP_REGC0   0xC0 | RCINDXP << 29 //
-
-//
-// RCINDX_C Registers
-//
-#define SB_RCINDXC_REG02   0x02 | RCINDXC << 29  // PCIE_HW_DEBUG
-#define SB_RCINDXC_REG10   0x10 | RCINDXC << 29  // PCIE_CNTL
-#define SB_RCINDXC_REGC0   0xC0 | RCINDXC << 29  //
-#define SB_RCINDXC_REGC1   0xC1 | RCINDXC << 29  //
-
-//
-// AXINDC Registers
-//
-#define SB_AX_INDXC_REG02  0x02 // PCIEP_HW_DEBUG
-#define SB_AX_INDXC_REG10  0x10
-#define SB_AX_INDXC_REG30  0x30
-#define SB_AX_DATAC_REG34  0x34
-#define SB_AX_INDXP_REG38  0x38
-#define SB_AX_DATAP_REG3C  0x3C
-#define SB_AX_INDXC_REG40  0x40 | AXINDC << 29
-#define SB_AX_INDXC_REGA4  0xA4 | AXINDC << 29
-
-#define SB_AX_INDXP_REG02  0x02 | AXINDP << 29
-#define SB_AX_INDXP_REGA0  0xA0 | AXINDP << 29
-#define SB_AX_INDXP_REGA4  0xA4 | AXINDP << 29
-#define SB_AX_INDXP_REGB1  0xB1 | AXINDP << 29
-
-#define SB_AX_CFG_REG68  0x68 | AXCFG << 29
-#define SB_AX_CFG_REG6A  0x6A | AXCFG << 29
-#define SB_AX_CFG_REG88  0x88 | AXCFG << 29
-
-#define SB_AB_REG04         0x04
-#define SB_AB_REG40         0x40
-
-#define RC_INDXC_REG40     0x40 | RCINDXC << 29
-#define RC_INDXC_REG65     0x65 | RCINDXC << 29
-#define RC_INDXC_REGC0     0xC0 | RCINDXC << 29
-
-//
-//  SATA Device 0x7800 (IDE)
-//              0x7801 (AHCI)
-//              0x7802 (AHCI/RAID Promise with RAID driver)
-//              0x7803 (RAID5)
-//  Device 17 (0x11) Func 0
-//
-//Sata Controller Mode
-#define NATIVE_IDE_MODE        0
-#define RAID_MODE              1
-#define AHCI_MODE              2
-#define LEGACY_IDE_MODE        3
-#define IDE_TO_AHCI_MODE       4
-#define AHCI_MODE_7804         5
-#define IDE_TO_AHCI_MODE_7804  6
-
-//Sata Port Configuration
-#define SIX_PORTS       0
-#define FOUR_PORTS      1
-
-#define SATA_EFUSE_LOCATION     0x10    // EFUSE bit 133
-#define SATA_FIS_BASE_EFUSE_LOC 0x15    // EFUSE bit 169
-#define SATA_EFUSE_BIT          0x20    //
-#define SB_SATA_REG00           0x000   // Vendor ID - R- 16 bits
-#define SB_SATA_REG02           0x002   // Device ID - RW -16 bits
-#define SB_SATA_REG04           0x004   // PCI Command - RW - 16 bits
-#define SB_SATA_REG06           0x006   // PCI Status - RW - 16 bits
-#define SB_SATA_REG08           0x008   // Revision ID/PCI Class Code - R - 32 bits - Offset: 08
-#define SB_SATA_REG0C           0x00C   // Cache Line Size - R/W - 8bits
-#define SB_SATA_REG0D           0x00D   // Latency Timer - RW - 8 bits
-#define SB_SATA_REG0E           0x00E   // Header Type - R - 8 bits
-#define SB_SATA_REG0F           0x00F   // BIST - R - 8 bits
-#define SB_SATA_REG10           0x010   // Base Address Register 0 - RW - 32 bits
-#define SB_SATA_REG14           0x014   // Base Address Register 1 - RW- 32 bits
-#define SB_SATA_REG18           0x018   // Base Address Register 2 - RW - 32 bits
-#define SB_SATA_REG1C           0x01C   // Base Address Register 3 - RW - 32 bits
-#define SB_SATA_REG20           0x020   // Base Address Register 4 - RW - 32 bits
-#define SB_SATA_REG24           0x024   // Base Address Register 5 - RW - 32 bits
-#define SB_SATA_REG2C           0x02C   // Subsystem Vendor ID - R - 16 bits
-#define SB_SATA_REG2D           0x02D   // Subsystem ID - R - 16 bits
-#define SB_SATA_REG30           0x030   // Expansion ROM Base Address - 32 bits
-#define SB_SATA_REG34           0x034   // Capabilities Pointer - R - 32 bits
-#define SB_SATA_REG3C           0x03C   // Interrupt Line - RW - 8 bits
-#define SB_SATA_REG3D           0x03D   // Interrupt Pin - R - 8 bits
-#define SB_SATA_REG3E           0x03E   // Min Grant - R - 8 bits
-#define SB_SATA_REG3F           0x03F   // Max Latency - R - 8 bits
-#define SB_SATA_REG40           0x040   // Configuration - RW - 32 bits
-#define SB_SATA_REG44           0x044   // Software Data Register - RW - 32 bits
-#define SB_SATA_REG48           0x048
-#define SB_SATA_REG4C           0x04C
-#define SB_SATA_REG50           0x050   // Message Capability - R - 16 bits
-#define SB_SATA_REG52           0x052   // Message Control - R/W - 16 bits
-#define SB_SATA_REG54           0x054   // Message Address - R/W - 32 bits
-#define SB_SATA_REG58           0x058   // Message Data - R/W - 16 bits
-#define SB_SATA_REG5C           0x05C   // RAMBIST Control Register - R/W - 8 bits
-#define SB_SATA_REG5D           0x05D   // RAMBIST Status0 Register - R - 8 bits
-#define SB_SATA_REG5E           0x05E   // RAMBIST Status1 Register - R - 8 bits
-#define SB_SATA_REG60           0x060   // Power Management Capabilities - R - 32 bits
-#define SB_SATA_REG64           0x064   // Power Management Control + Status - RW - 32 bits
-#define SB_SATA_REG68           0x068   // MSI Program - R/W - 8 bits
-#define SB_SATA_REG69           0x069   // PCI Burst Timer - R/W - 8 bits
-#define SB_SATA_REG70           0x070   // PCI Bus Master - IDE0 - RW - 32 bits
-#define SB_SATA_REG74           0x074   // PRD Table Address - IDE0 - RW - 32 bits
-#define SB_SATA_REG78           0x078   // PCI Bus Master - IDE1 - RW - 32 bits
-#define SB_SATA_REG7C           0x07C   // PRD Table Address - IDE1 - RW - 32 bits
-#define SB_SATA_REG80           0x080   // Data Transfer Mode - IDE0 - RW - 32 bits
-#define SB_SATA_REG84           0x084   // Data Transfer Mode - IDE1 - RW - 32 bits
-#define SB_SATA_REG86           0x086   // PY Global Control
-#define SB_SATA_REG87           0x087
-#define SB_SATA_REG88           0x088   // PHY Port0 Control - Port0 PY fine tune (0:23)
-#define SB_SATA_REG8A           0x08A
-#define SB_SATA_REG8C           0x08C   // PHY Port1 Control - Port0 PY fine tune (0:23)
-#define SB_SATA_REG8E           0x08E
-#define SB_SATA_REG90           0x090   // PHY Port2 Control - Port0 PY fine tune (0:23)
-#define SB_SATA_REG92           0x092
-#define SB_SATA_REG94           0x094   // PHY Port3 Control - Port0 PY fine tune (0:23)
-#define SB_SATA_REG96           0x096
-#define SB_SATA_REG98           0x098   // EEPROM Memory Address - Command + Status - RW - 32 bits
-#define SB_SATA_REG9C           0x09C   // EEPROM Memory Data - RW - 32 bits
-#define SB_SATA_REGA0           0x0A0   //
-#define SB_SATA_REGA4           0x0A4   //
-#define SB_SATA_REGA5           0x0A5   //;
-#define SB_SATA_REGA8           0x0A8   //
-#define SB_SATA_REGAD           0x0AD   //;
-#define SB_SATA_REGB0           0x0B0   // IDE1 Task File Configuration + Status - RW - 32 bits
-#define SB_SATA_REGB5           0x0B5   //;
-#define SB_SATA_REGBD           0x0BD   //;
-#define SB_SATA_REGC0           0x0C0   // BA5 Indirect Address - RW - 32 bits
-#define SB_SATA_REGC4           0x0C4   // BA5 Indirect Access - RW - 32 bits
-
-#define SB_SATA_BAR5_REG00      0x000   // PCI Bus Master - IDE0 - RW - 32 bits
-#define SB_SATA_BAR5_REG04      0x004   // PRD Table Address - IDE0 - RW - 32 bits
-#define SB_SATA_BAR5_REG08      0x008   // PCI Bus Master - IDE1 - RW - 32 bits
-#define SB_SATA_BAR5_REG0C      0x00C   // PRD Table Address - IDE1 - RW - 32 bits
-#define SB_SATA_BAR5_REG10      0x010   // PCI Bus Master2 - IDE0 - RW - 32 bits
-#define SB_SATA_BAR5_REG1C      0x01C
-#define SB_SATA_BAR5_REG18      0x018   // PCI Bus Master2 - IDE1 - RW - 32 bits
-#define SB_SATA_BAR5_REG20      0x020   // PRD Address - IDE0 - RW - 32 bits
-#define SB_SATA_BAR5_REG24      0x024   // PCI Bus Master Byte Count - IDE0- RW - 32 bits
-#define SB_SATA_BAR5_REG28      0x028   // PRD Address - IDE1 - RW - 32 bits
-#define SB_SATA_BAR5_REG2C      0x02C   // PCI Bus Master Byte Count - IDE1 - RW - 32 bits
-#define SB_SATA_BAR5_REG40      0x040   // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits
-#define SB_SATA_BAR5_REG44      0x044   // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits
-#define SB_SATA_BAR5_REG48      0x048   // System Configuration Status - Command - RW - 32 bits
-#define SB_SATA_BAR5_REG4C      0x04C   // System Software Data Register - RW - 32 bits
-#define SB_SATA_BAR5_REG50      0x050   // FLAS Memory Address - Command + Status - RW - 32 bits
-#define SB_SATA_BAR5_REG54      0x054   // FLAS Memory Data - RW - 32 bits
-#define SB_SATA_BAR5_REG58      0x058   // EEPROM Memory Address - Command + Status - RW - 32 bits
-#define SB_SATA_BAR5_REG5C      0x05C   // EEPROM Memory Data - RW - 32 bits
-#define SB_SATA_BAR5_REG60      0x060   // FIFO Port - IDE0 - RW - 32 bits
-#define SB_SATA_BAR5_REG68      0x068   // FIFO Pointers1- IDE0 - RW - 32 bits
-#define SB_SATA_BAR5_REG6C      0x06C   // FIFO Pointers2- IDE0 - RW - 32 bits
-#define SB_SATA_BAR5_REG70      0x070   // FIFO Port - IDE1- RW - 32 bits
-#define SB_SATA_BAR5_REG78      0x078   // FIFO Pointers1- IDE1- RW - 32 bits
-#define SB_SATA_BAR5_REG7C      0x07C   // FIFO Pointers2- IDE1- RW - 32 bits
-#define SB_SATA_BAR5_REG80      0x080   // IDE0 Task File Register 0- RW - 32 bits
-#define SB_SATA_BAR5_REG84      0x084   // IDE0 Task File Register 1- RW - 32 bits
-#define SB_SATA_BAR5_REG88      0x088   // IDE0 Task File Register 2- RW - 32 bits
-#define SB_SATA_BAR5_REG8C      0x08C   // IDE0 Read Data - RW - 32 bits
-#define SB_SATA_BAR5_REG90      0x090   // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits
-#define SB_SATA_BAR5_REG94      0x094   // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits
-#define SB_SATA_BAR5_REG9C      0x09C   // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits
-#define SB_SATA_BAR5_REGA0      0x0A0   // IDE0 Task File Configuration + Status - RW - 32 bits
-#define SB_SATA_BAR5_REGB4      0x0B4   // Data Transfer Mode -IDE0 - RW - 32 bits
-#define SB_SATA_BAR5_REGC0      0x0C0   // IDE1 Task File Register 0 - RW - 32 bits
-#define SB_SATA_BAR5_REGC4      0x0C4   // IDE1 Task File Register 1 - RW - 32 bits
-#define SB_SATA_BAR5_REGC8      0x0C8   // IDE1 Task File Register 2 - RW - 32 bits
-#define SB_SATA_BAR5_REGCC      0x0CC   //  Read/Write Data - RW - 32 bits
-#define SB_SATA_BAR5_REGD0      0x0D0   // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits
-#define SB_SATA_BAR5_REGD4      0x0D4   // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits
-#define SB_SATA_BAR5_REGDC      0x0DC   // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits
-#define SB_SATA_BAR5_REGE0      0x0E0   // IDE1 Task File Configuration + Status - RW - 32 bits
-#define SB_SATA_BAR5_REGF4      0x0F4   // Data Transfer Mode - IDE1 - RW - 32 bits
-#define SB_SATA_BAR5_REGF8      0x0F8   // PORT Configuration
-#define SB_SATA_BAR5_REGFC      0x0FC
-#define SB_SATA_BAR5_REG100     0x0100  // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180
-#define SB_SATA_BAR5_REG104     0x0104  // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel
-#define SB_SATA_BAR5_REG108     0x0108  // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel
-#define SB_SATA_BAR5_REG10C     0x010C  // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel
-#define SB_SATA_BAR5_REG144     0x0144  // Serial ATA PY Configuration - RW - 32 bits
-#define SB_SATA_BAR5_REG148     0x0148  // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)]
-#define SB_SATA_BAR5_REG14C     0x014C  // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)]
-#define SB_SATA_BAR5_REG120     0x0120  //
-#define SB_SATA_BAR5_REG128     0x0128  // Port Serial ATA Status
-#define SB_SATA_BAR5_REG12C     0x012C  // Port Serial ATA Control
-#define SB_SATA_BAR5_REG130     0x0130
-#define SB_SATA_BAR5_REG1B0     0x01B0
-#define SB_SATA_BAR5_REG230     0x0230
-#define SB_SATA_BAR5_REG2B0     0x02B0
-#define SB_SATA_BAR5_REG330     0x0330
-#define SB_SATA_BAR5_REG3B0     0x03B0
-#define SB_SATA_BAR5_REG430     0x0430
-#define SB_SATA_BAR5_REG4B0     0x04B0
-//
-//  USB XHCI Device 0x7812
-//  Device 16 (0x10) Func 0/1
-//
-#define XHCI_EFUSE_LOCATION     0x18        // EFUSE bit 192, 193
-#define SB_XHCI_REG48           0x48        // Port Force Reset - RW (800)
-#define SB_XHCI_REG4C           0x4C        // MSI - RW   (800)
-//
-//  USB OHCI Device 0x7807
-//  Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0
-//  Device 20 (0x14) Func 5 (FL) 0x7809
-//
-#define SB_OHCI_REG00           0x00        // Device/Vendor ID - R (0x43971002)
-#define SB_OHCI_REG04           0x04        // Command - RW
-#define SB_OHCI_REG06           0x06        // Status - R
-#define SB_OHCI_REG08           0x08        // Revision ID/Class Code - R
-#define SB_OHCI_REG0C           0x0C        // Miscellaneous - RW
-#define SB_OHCI_REG10           0x10        // Bar_OCI - RW
-#define SB_OHCI_REG2C           0x2C        // Subsystem Vendor ID/ Subsystem ID - RW
-#define SB_OHCI_REG34           0x34        // Capability Pointer - R
-#define SB_OHCI_REG3C           0x3C        // Interrupt Line - RW
-#define SB_OHCI_REG3D           0x3D        // Interrupt Line - RW
-#define SB_OHCI_REG40           0x40        // Config Timers - RW
-#define SB_OHCI_REG42           0x42        // Port Disable Control - RW (800)
-#define SB_OHCI_REG46           0x46        // USB PHY Battery Charger - RW (800)
-#define SB_OHCI_REG48           0x48        // Port Force Reset - RW (800)
-#define SB_OHCI_REG4C           0x4C        // MSI - RW   (800)
-#define SB_OHCI_REG50           0x50        // Misc Control - RW
-#define SB_OHCI_REG51           0x51
-#define SB_OHCI_REG52           0x52
-#define SB_OHCI_REG58           0x58        // Over Current Control - RW
-#define SB_OHCI_REG5C           0x5C        // Over Current Control - RW  (800)??
-#define SB_OHCI_REG60           0x60        // Serial Bus Release Number - R (800)??
-#define SB_OHCI_REG68           0x68        // Over Current PME Enable - RW
-#define SB_OHCI_REG74           0x74        // Target Timeout Control - RW (800)
-#define SB_OHCI_REG78           0x78        //
-#define SB_OHCI_REG80           0x80        //
-#define SB_OHCI_REGD0           0x0D0       // MSI Control - RW
-#define SB_OHCI_REGD4           0x0D4       // MSI Address - RW
-#define SB_OHCI_REGD8           0x0D8       // MSI Data - RW
-#define SB_OHCI_REGE4           0x0E4       // HT MSI Support
-#define SB_OHCI_REGF0           0x0F0       // Function Level Reset Capability
-#define SB_OHCI_REGF4           0x0F4       // Function Level Reset Control
-
-#define SB_OHCI_BAR_REG00       0x00        // cRevision - R
-#define SB_OHCI_BAR_REG04       0x04        // cControl
-#define SB_OHCI_BAR_REG08       0x08        // cCommandStatus
-#define SB_OHCI_BAR_REG0C       0x0C        // cInterruptStatus  RW
-#define SB_OHCI_BAR_REG10       0x10        // cInterruptEnable
-#define SB_OHCI_BAR_REG14       0x14        // cInterruptDisable
-#define SB_OHCI_BAR_REG18       0x18        // HcCCA
-#define SB_OHCI_BAR_REG1C       0x1C        // cPeriodCurrentED
-#define SB_OHCI_BAR_REG20       0x20        // HcControleadED
-#define SB_OHCI_BAR_REG24       0x24        // cControlCurrentED  RW
-#define SB_OHCI_BAR_REG28       0x28        // HcBulkeadED
-#define SB_OHCI_BAR_REG2C       0x2C        // cBulkCurrentED- RW
-#define SB_OHCI_BAR_REG30       0x30        // HcDoneead
-#define SB_OHCI_BAR_REG34       0x34        // cFmInterval
-#define SB_OHCI_BAR_REG38       0x38        // cFmRemaining
-#define SB_OHCI_BAR_REG3C       0x3C        // cFmNumber
-#define SB_OHCI_BAR_REG40       0x40        // cPeriodicStart
-#define SB_OHCI_BAR_REG44       0x44        // HcLSThresold
-#define SB_OHCI_BAR_REG48       0x48        // HcRDescriptorA
-#define SB_OHCI_BAR_REG4C       0x4C        // HcRDescriptorB
-#define SB_OHCI_BAR_REG50       0x50        // HcRStatus
-#define SB_OHCI_BAR_REG54       0x54        // HcRhPortStatus (800)
-#define SB_OHCI_BAR_REG58       0x58        // HcRhPortStatus NPD (800)
-#define SB_OHCI_BAR_REGF0       0xF0        // OHCI Loop Back feature Support (800)
-
-//
-//  USB EHCI Device 0x7808
-//  Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2
-//
-#define SB_EHCI_REG00           0x00        // DEVICE/VENDOR ID - R
-#define SB_EHCI_REG04           0x04        // Command - RW
-#define SB_EHCI_REG06           0x06        // Status - R
-#define SB_EHCI_REG08           0x08        // Revision ID/Class Code - R
-#define SB_EHCI_REG0C           0x0C        // Miscellaneous - RW
-#define SB_EHCI_REG10           0x10        // BAR - RW
-#define SB_EHCI_REG2C           0x2C        // Subsystem ID/Subsystem Vendor ID - RW
-#define SB_EHCI_REG34           0x34        // Capability Pointer - R
-#define SB_EHCI_REG3C           0x3C        // Interrupt Line - RW
-#define SB_EHCI_REG3D           0x3D        // Interrupt Line - RW ??
-#define SB_EHCI_REG40           0x40        // Config Timers - RW ??
-#define SB_EHCI_REG4C           0x4C        // MSI - RW
-#define SB_EHCI_REG50           0x50        // EHCI Misc Control - RW
-#define SB_EHCI_REG54           0x54        // EHCI Misc Control - RW
-#define SB_EHCI_REG60           0x60        // SBRN - R
-#define SB_EHCI_REG61           0x61        // FLADJ - RW
-#define SB_EHCI_REG62           0x62        // PORTWAKECAP - RW
-#define SB_EHCI_REGC0           0x0C0       // PME control - RW (800)
-#define SB_EHCI_REGC4           0x0C4       // PME Data /Status - RW (800)
-#define SB_EHCI_REGD0           0x0D0       // MSI Control - RW
-#define SB_EHCI_REGD4           0x0D4       // MSI Address - RW
-#define SB_EHCI_REGD8           0x0D8       // MSI Data - RW
-#define SB_EHCI_REGE4           0x0E4       // EHCI Debug Port Support - RW (800)
-#define SB_EHCI_REGF0           0x0F0       // Function Level Reset Capability - R (800)
-#define SB_EHCI_REGF4           0x0F4       // Function Level Reset Capability - R (800)
-
-#define SB_EHCI_BAR_REG00       0x00        // CAPLENGT - R
-#define SB_EHCI_BAR_REG02       0x002       // CIVERSION- R
-#define SB_EHCI_BAR_REG04       0x004       // CSPARAMS - R
-#define SB_EHCI_BAR_REG08       0x008       // CCPARAMS - R
-#define SB_EHCI_BAR_REG0C       0x00C       // CSP-PORTROUTE - R
-
-#define SB_EHCI_BAR_REG20       0x020       // USBCMD - RW - 32 bits
-#define SB_EHCI_BAR_REG24       0x024       // USBSTS - RW - 32 bits
-#define SB_EHCI_BAR_REG28       0x028       // USBINTR -RW - 32 bits
-#define SB_EHCI_BAR_REG2C       0x02C       // FRINDEX -RW - 32 bits
-#define SB_EHCI_BAR_REG30       0x030       // CTRLDSSEGMENT -RW - 32 bits
-#define SB_EHCI_BAR_REG34       0x034       // PERIODICLISTBASE -RW - 32 bits
-#define SB_EHCI_BAR_REG38       0x038       // ASYNCLISTADDR -RW - 32 bits
-#define SB_EHCI_BAR_REG60       0x060       // CONFIGFLAG -RW - 32 bits
-#define SB_EHCI_BAR_REG64       0x064       // PORTSC (1-N_PORTS) -RW - 32 bits
-#define SB_EHCI_BAR_REGA0       0x0A0       // DebugPort MISC Control - RW - 32 bits (800)
-#define SB_EHCI_BAR_REGA4       0x0A4       // Packet Buffer Threshold Values - RW - 32 bits
-#define SB_EHCI_BAR_REGA8       0x0A8       // USB PHY Status 0 - R
-#define SB_EHCI_BAR_REGAC       0x0AC       // USB PHY Status 1 - R
-#define SB_EHCI_BAR_REGB0       0x0B0       // USB PHY Status 2 - R
-#define SB_EHCI_BAR_REGB4       0x0B4       // UTMI Control - RW (800)
-#define SB_EHCI_BAR_REGB8       0x0B8       // Loopback Test
-#define SB_EHCI_BAR_REGBC       0x0BC       // EHCI MISC Control
-#define SB_EHCI_BAR_REGC0       0x0C0       // USB PHY Calibration
-#define SB_EHCI_BAR_REGC4       0x0C4       // USB Common PHY Control
-#define SB_EHCI_BAR_REGC8       0x0C8       // EHCI Debug Purpose
-#define SB_EHCI_BAR_REGCC       0x0CC       // Ehci Spare 1 (800) **
-#define SB_EHCI_BAR_REG100      0x100       // USB debug port
-
-//
-//  Hudson-2 SB CFG device  0x780B
-//  Device 20 (0x14) Func 0
-//
-#define SB_CFG_REG00            0x000       // VendorID - R
-#define SB_CFG_REG02            0x002       // DeviceID - R
-#define SB_CFG_REG04            0x004       // Command- RW
-#define SB_CFG_REG05            0x005       // Command- RW
-#define SB_CFG_REG06            0x006       // STATUS- RW
-#define SB_CFG_REG08            0x008       // Revision ID/Class Code- R
-#define SB_CFG_REG0A            0x00A       //
-#define SB_CFG_REG0B            0x00B       //
-#define SB_CFG_REG0C            0x00C       // Cache Line Size- R
-#define SB_CFG_REG0D            0x00D       // Latency Timer- R
-#define SB_CFG_REG0E            0x00E       // Header Type- R
-#define SB_CFG_REG0F            0x00F       // BIST- R
-#define SB_CFG_REG10            0x010       // Base Address 0- R
-#define SB_CFG_REG11            0x011       //;
-#define SB_CFG_REG12            0x012       //;
-#define SB_CFG_REG13            0x013       //;
-#define SB_CFG_REG14            0x014       // Base Address 1- R
-#define SB_CFG_REG18            0x018       // Base Address 2- R
-#define SB_CFG_REG1C            0x01C       // Base Address 3- R
-#define SB_CFG_REG20            0x020       // Base Address 4- R
-#define SB_CFG_REG24            0x024       // Base Address 5- R
-#define SB_CFG_REG28            0x028       // Cardbus CIS Pointer- R
-#define SB_CFG_REG2C            0x02C       // Subsystem Vendor ID- W
-#define SB_CFG_REG2E            0x02E       // Subsystem ID- W
-#define SB_CFG_REG30            0x030       // Expansion ROM Base Address - R
-#define SB_CFG_REG34            0x034       // Capability Pointer - R  (800) default changed as 0x00
-#define SB_CFG_REG3C            0x03C       // Interrupt Line - R
-#define SB_CFG_REG3D            0x03D       // Interrupt Pin - R
-#define SB_CFG_REG3E            0x03E       // Min_Gnt - R
-#define SB_CFG_REG3F            0x03F       // Max_Lat - R
-#define SB_CFG_REG90            0x090       // Smbus Base Address - R
-#define SB_CFG_REG9C            0x09C       // SBResourceMMIO_BASE
-
-//
-//  Hudson-2 SATA IDE device
-//  Device 20 (0x14) Func 1
-//
-
-#define SB_IDE_REG00            0x00        // Vendor ID
-#define SB_IDE_REG02            0x02        // Device ID
-#define SB_IDE_REG04            0x04        // Command
-#define SB_IDE_REG06            0x06        // Status
-#define SB_IDE_REG08            0x08        // Revision ID/Class Code
-#define SB_IDE_REG09            0x09        // Class Code
-#define SB_IDE_REG2C            0x2C        // Subsystem ID and Subsystem Vendor ID
-#define SB_IDE_REG40            0x40        // Configuration - RW - 32 bits
-#define SB_IDE_REG34            0x34
-#define SB_IDE_REG62            0x62        // IDE Internal Control
-#define SB_IDE_REG63            0x63        // IDE Internal Control
-//
-//  Hudson-2 AZALIA device  0x780D
-//  Device 20 (0x14) Func 2
-//
-#define ATI_AZALIA_ExtBlk_Addr          0x0F8
-#define ATI_AZALIA_ExtBlk_DATA          0x0FC
-
-#define SB_AZ_REG00             0x00        // Vendor ID - R
-#define SB_AZ_REG02             0x02        // Device ID - R/W
-#define SB_AZ_REG04             0x04        // PCI Command
-#define SB_AZ_REG06             0x06        // PCI Status - R/W
-#define SB_AZ_REG08             0x08        // Revision ID
-#define SB_AZ_REG09             0x09        // Programming Interface
-#define SB_AZ_REG0A             0x0A        // Sub Class Code
-#define SB_AZ_REG0B             0x0B        // Base Class Code
-#define SB_AZ_REG0C             0x0C        // Cache Line Size - R/W
-#define SB_AZ_REG0D             0x0D        // Latency Timer
-#define SB_AZ_REG0E             0x0E        // Header Type
-#define SB_AZ_REG0F             0x0F        // BIST
-#define SB_AZ_REG10             0x10        // Lower Base Address Register
-#define SB_AZ_REG14             0x14        // Upper Base Address Register
-#define SB_AZ_REG2C             0x2C        // Subsystem Vendor ID
-#define SB_AZ_REG2D             0x2D        // Subsystem ID
-#define SB_AZ_REG34             0x34        // Capabilities Pointer
-#define SB_AZ_REG3C             0x3C        // Interrupt Line
-#define SB_AZ_REG3D             0x3D        // Interrupt Pin
-#define SB_AZ_REG3E             0x3E        // Minimum Grant
-#define SB_AZ_REG3F             0x3F        // Maximum Latency
-#define SB_AZ_REG40             0x40        // Misc Control 1
-#define SB_AZ_REG42             0x42        // Misc Control 2 Register
-#define SB_AZ_REG43             0x43        // Misc Control 3 Register
-#define SB_AZ_REG44             0x44        // Interrupt Pin Control Register
-#define SB_AZ_REG46             0x46        // Debug Control Register
-#define SB_AZ_REG4C             0x4C
-#define SB_AZ_REG50             0x50        // Power Management Capability ID
-#define SB_AZ_REG52             0x52        // Power Management Capabilities
-#define SB_AZ_REG54             0x54        // Power Management Control/Status
-#define SB_AZ_REG60             0x60        // MSI Capability ID
-#define SB_AZ_REG62             0x62        // MSI Message Control
-#define SB_AZ_REG64             0x64        // MSI Message Lower Address
-#define SB_AZ_REG68             0x68        // MSI Message Upper Address
-#define SB_AZ_REG6C             0x6C        // MSI Message Data
-
-#define SB_AZ_BAR_REG00         0x00        // Global Capabilities - R
-#define SB_AZ_BAR_REG02         0x02        // Minor Version - R
-#define SB_AZ_BAR_REG03         0x03        // Major Version - R
-#define SB_AZ_BAR_REG04         0x04        // Output Payload Capability - R
-#define SB_AZ_BAR_REG06         0x06        // Input Payload Capability - R
-#define SB_AZ_BAR_REG08         0x08        // Global Control - R/W
-#define SB_AZ_BAR_REG0C         0x0C        // Wake Enable - R/W
-#define SB_AZ_BAR_REG0E         0x0E        // State Change Status - R/W
-#define SB_AZ_BAR_REG10         0x10        // Global Status - R/W
-#define SB_AZ_BAR_REG18         0x18        // Output Stream Payload Capability - R
-#define SB_AZ_BAR_REG1A         0x1A        // Input Stream Payload Capability - R
-#define SB_AZ_BAR_REG20         0x20        // Interrupt Control - R/W
-#define SB_AZ_BAR_REG24         0x24        // Interrupt Status - R/W
-#define SB_AZ_BAR_REG30         0x30        // Wall Clock Counter - R
-#define SB_AZ_BAR_REG38         0x38        // Stream Synchronization - R/W
-#define SB_AZ_BAR_REG40         0x40        // CORB Lower Base Address - R/W
-#define SB_AZ_BAR_REG44         0x44        // CORB Upper Base Address - RW
-#define SB_AZ_BAR_REG48         0x48        // CORB Write Pointer - R/W
-#define SB_AZ_BAR_REG4A         0x4A        // CORB Read Pointer - R/W
-#define SB_AZ_BAR_REG4C         0x4C        // CORB Control - R/W
-#define SB_AZ_BAR_REG4D         0x4D        // CORB Status - R/W
-#define SB_AZ_BAR_REG4E         0x4E        // CORB Size - R/W
-#define SB_AZ_BAR_REG50         0x50        // RIRB Lower Base Address - RW
-#define SB_AZ_BAR_REG54         0x54        // RIRB Upper Address - RW
-#define SB_AZ_BAR_REG58         0x58        // RIRB Write Pointer - RW
-#define SB_AZ_BAR_REG5A         0x5A        // RIRB Response Interrupt Count - R/W
-#define SB_AZ_BAR_REG5C         0x5C        // RIRB Control - R/W
-#define SB_AZ_BAR_REG5D         0x5D        // RIRB Status - R/W
-#define SB_AZ_BAR_REG5E         0x5E        // RIRB Size - R/W
-#define SB_AZ_BAR_REG60         0x60        // Immediate Command Output Interface - R/W
-#define SB_AZ_BAR_REG64         0x64        // Immediate Command Input Interface - R/W
-#define SB_AZ_BAR_REG68         0x68        // Immediate Command Input Interface - R/W
-#define SB_AZ_BAR_REG70         0x70        // DMA Position Lower Base Address - R/W
-#define SB_AZ_BAR_REG74         0x74        // DMA Position Upper Base Address - R/W
-#define SB_AZ_BAR_REG2030       0x2030      // Wall Clock Counter Alias - R
-
-//
-//  Hudson-2 LPC Device  0x780E
-//  Device 20 (0x14) Func 3
-//
-#define SB_LPC_REG00            0x00        // VID- R
-#define SB_LPC_REG02            0x02        // DID- R
-#define SB_LPC_REG04            0x04        // CMD- RW
-#define SB_LPC_REG06            0x06        // STATUS- RW
-#define SB_LPC_REG08            0x08        // Revision  ID/Class Code - R
-#define SB_LPC_REG0C            0x0C        // Cache Line Size - R
-#define SB_LPC_REG0D            0x0D        // Latency Timer - R
-#define SB_LPC_REG0E            0x0E        // Header Type - R
-#define SB_LPC_REG0F            0x0F        // BIST- R
-#define SB_LPC_REG10            0x10        // Base Address Reg 0- RW*
-#define SB_LPC_REG2C            0x2C        // Subsystem ID & Subsystem Vendor ID - Wo/Ro
-#define SB_LPC_REG34            0x34        // Capabilities Pointer - Ro
-#define SB_LPC_REG40            0x40        // PCI Control - RW
-#define SB_LPC_REG44            0x44        // IO Port Decode Enable Register 1- RW
-#define SB_LPC_REG45            0x45        // IO Port Decode Enable Register 2- RW
-#define SB_LPC_REG46            0x46        // IO Port Decode Enable Register 3- RW
-#define SB_LPC_REG47            0x47        // IO Port Decode Enable Register 4- RW
-#define SB_LPC_REG48            0x48        // IO/Mem Port Decode Enable Register 5- RW
-#define SB_LPC_REG49            0x49        // LPC Sync Timeout Count - RW
-#define SB_LPC_REG4A            0x4A        // IO/Mem Port Decode Enable Register 6- RW
-#define SB_LPC_REG4C            0x4C        // Memory Range Register - RW
-#define SB_LPC_REG50            0x50        // Rom Protect 0 - RW
-#define SB_LPC_REG54            0x54        // Rom Protect 1 - RW
-#define SB_LPC_REG58            0x58        // Rom Protect 2 - RW
-#define SB_LPC_REG5C            0x5C        // Rom Protect 3 - RW
-#define SB_LPC_REG60            0x60        // PCI Memory Start Address of LPC Target Cycles -
-#define SB_LPC_REG62            0x62        // PCI Memory End Address of LPC Target Cycles -
-#define SB_LPC_REG64            0x64        // PCI IO base Address of Wide Generic Port - RW
-#define SB_LPC_REG65            0x65
-#define SB_LPC_REG66            0x66
-#define SB_LPC_REG67            0x67
-#define SB_LPC_REG68            0x68        // LPC ROM Address Range 1 (Start Address) - RW
-#define SB_LPC_REG69            0x69
-#define SB_LPC_REG6A            0x6A        // LPC ROM Address Range 1 (End Address) - RW
-#define SB_LPC_REG6B            0x6B
-#define SB_LPC_REG6C            0x6C        // LPC ROM Address Range 2 (Start Address)- RW
-#define SB_LPC_REG6D            0x6D
-#define SB_LPC_REG6E            0x6E        // LPC ROM Address Range 2 (End Address) - RW
-#define SB_LPC_REG6F            0x6F
-#define SB_LPC_REG70            0x70        // Firmware ub Select - RW*
-#define SB_LPC_REG71            0x71
-#define SB_LPC_REG72            0x72
-#define SB_LPC_REG73            0x73
-#define SB_LPC_REG74            0x74        // Alternative Wide IO Range Enable- W/R
-#define SB_LPC_REG78            0x78        // Miscellaneous Control Bits- W/R
-#define SB_LPC_REG7C            0x7C        // TPM (trusted plant form module) reg- W/R
-#define SB_LPC_REG9C            0x9C
-#define SB_LPC_REG80            0x80        // MSI Capability Register- R
-#define SB_LPC_REGA0            0x0A0       // SPI base address
-#define SB_LPC_REGA1            0x0A1       // SPI base address
-#define SB_LPC_REGA2            0x0A2       // SPI base address
-#define SB_LPC_REGA3            0x0A3       // SPI base address
-#define SB_LPC_REGA4            0x0A4
-#define SB_LPC_REGBA            0x0BA       // EcControl
-#define SB_LPC_REGBB            0x0BB       // HostControl
-#define SB_LPC_REGCC            0x0CC       // AutoRomCfg
-#define SB_LPC_REGD0            0x0D0       // SB_LPC_REGD0
-
-//
-//  Hudson-2 PCIB  0x780F
-//  Device 20 (0x14) Func 4
-//
-#define SB_PCIB_REG04            0x04       // Command
-#define SB_PCIB_REG0D            0x0D       // Primary Master Latency Timer
-#define SB_PCIB_REG1B            0x1B       // Secondary Latency Timer
-#define SB_PCIB_REG1C            0x1C       // IO Base
-#define SB_PCIB_REG1D            0x1D       // IO Limit
-#define SB_PCIB_REG40            0x40       // CPCTRL
-#define SB_PCIB_REG42            0x42       // CLKCTRL
-#define SB_PCIB_REG48            0x48       //
-#define SB_PCIB_REG4A            0x4A       // PCICLK Enable Bits
-#define SB_PCIB_REG4B            0x4B       // Misc Control
-#define SB_PCIB_REG4C            0x4C       // AutoClockRun Control
-#define SB_PCIB_REG50            0x50       // Dual Address Cycle Enable and PCIB_CLK_Stop Override
-#define SB_PCIB_REG65            0x65       // Misc Control
-#define SB_PCIB_REG66            0x66       // Misc Control
-//
-//  Hudson-2 GEC 0x14E4 0x1699
-//  Device 20 (0x14) Func 6
-//
-#define SB_GEC_REG10             0x10       // GEC BAR
-//
-//  Hudson-2 SB MMIO Base (SMI)
-//    offset : 0x200
-//
-#define SB_SMI_REG00            0x00         // EventStatus
-#define SB_SMI_REG04            0x04         // EventEnable
-#define SB_SMI_REG08            0x08         // SciTrig
-#define SB_SMI_REG0C            0x0C         // SciLevl
-#define SB_SMI_REG10            0x10         // SmiSciStatus
-#define SB_SMI_REG14            0x14         // SmiSciEn
-#define SB_SMI_REG18            0x18         // ForceSciEn
-#define SB_SMI_REG1C            0x1C         // SciRwData
-#define SB_SMI_REG20            0x20         // SciS0En
-#define SB_SMI_REG3C            0x3C         // DataErrStatus
-#define SB_SMI_Gevent0          0x40         // SciMap0
-#define SB_SMI_Gevent1          0x41         // SciMap1
-#define SB_SMI_Gevent2          0x42         // SciMap2
-#define SB_SMI_Gevent3          0x43         // SciMap3
-#define SB_SMI_Gevent4          0x44         // SciMap4
-#define SB_SMI_Gevent5          0x45         // SciMap5
-#define SB_SMI_Gevent6          0x46         // SciMap6
-#define SB_SMI_Gevent7          0x47         // SciMap7
-#define SB_SMI_Gevent8          0x48         // SciMap8
-#define SB_SMI_Gevent9          0x49         // SciMap9
-#define SB_SMI_Gevent10         0x4A         // SciMap10
-#define SB_SMI_Gevent11         0x4B         // SciMap11
-#define SB_SMI_Gevent12         0x4C         // SciMap12
-#define SB_SMI_Gevent13         0x4D         // SciMap13
-#define SB_SMI_Gevent14         0x4E         // SciMap14
-#define SB_SMI_Gevent15         0x4F         // SciMap15
-#define SB_SMI_Gevent16         0x50         // SciMap16
-#define SB_SMI_Gevent17         0x51         // SciMap17
-#define SB_SMI_Gevent18         0x52         // SciMap18
-#define SB_SMI_Gevent19         0x53         // SciMap19
-#define SB_SMI_Gevent20         0x54         // SciMap20
-#define SB_SMI_Gevent21         0x55         // SciMap21
-#define SB_SMI_Gevent22         0x56         // SciMap22
-#define SB_SMI_Gevent23         0x57         // SciMap23
-#define SB_SMI_Usbwakup0        0x58         // SciMap24
-#define SB_SMI_Usbwakup1        0x59         // SciMap25
-#define SB_SMI_Usbwakup2        0x5A         // SciMap26
-#define SB_SMI_Usbwakup3        0x5B         // SciMap27
-#define SB_SMI_SBGppPme0        0x5C         // SciMap28
-#define SB_SMI_SBGppPme1        0x5D         // SciMap29
-#define SB_SMI_SBGppPme2        0x5E         // SciMap30
-#define SB_SMI_SBGppPme3        0x5F         // SciMap31
-#define SB_SMI_SBGppHp0         0x60         // SciMap32
-#define SB_SMI_Reserved0        0x61         // SciMap33
-#define SB_SMI_Reserved1        0x62         // SciMap34
-#define SB_SMI_Reserved2        0x63         // SciMap35
-#define SB_SMI_AzaliaPme        0x64         // SciMap36
-#define SB_SMI_SataGevent0      0x65         // SciMap37
-#define SB_SMI_SataGevent1      0x66         // SciMap38
-#define SB_SMI_GecPme           0x67         // SciMap39
-#define SB_SMI_IMCGevent0       0x68         // SciMap40
-#define SB_SMI_IMCGevent1       0x69         // SciMap41
-#define SB_SMI_CIRPme           0x6A         // SciMap42
-#define SB_SMI_Reserved3        0x6B         // SciMap43
-#define SB_SMI_FanThGevent      0x6C         // SciMap44    //FanThermalGevent
-#define SB_SMI_ASFMasterIntr    0x6D         // SciMap45
-#define SB_SMI_ASFSlaveIntr     0x6E         // SciMap46
-#define SB_SMI_SMBUS0           0x6F         // SciMap47
-#define SB_SMI_TWARN            0x70         // SciMap48
-#define SB_SMI_TMI              0x71         // SciMap49    // TrafficMonitorIntr
-#define SB_SMI_iLLB             0x72         // SciMap50
-#define SB_SMI_PowerButton      0x73         // SciMap51
-#define SB_SMI_ProcHot          0x74         // SciMap52
-#define SB_SMI_APUHwAssertion   0x75         // SciMap53
-#define SB_SMI_APUSciAssertion  0x76         // SciMap54
-#define SB_SMI_RAS              0x77         // SciMap55
-#define SB_SMI_xHC0Pme          0x78         // SciMap56
-#define SB_SMI_xHC1Pme          0x79         // SciMap57
-
-// Empty from 0x72-0x7F
-//#Define SB_SMI_REG7C            0x7F         // SciMap63  ***
-
-#define SB_SMI_REG80            0x80         //  SmiStatus0
-#define SB_SMI_REG84            0x84         // SmiStatus1
-#define SB_SMI_REG88            0x88         // SmiStatus2
-#define SB_SMI_REG8C            0x8C         // SmiStatus3
-#define SB_SMI_REG90            0x90         // SmiStatus4
-#define SB_SMI_REG94            0x94         // SmiPointer
-#define SB_SMI_REG96            0x96         // SmiTimer
-#define SB_SMI_REG98            0x98         // SmiTrig
-#define SB_SMI_REG9C            0x9C         // SmiTrig
-#define SB_SMI_REGA0            0xA0
-#define SB_SMI_REGA1            0xA1
-#define SB_SMI_REGA2            0xA2
-#define SB_SMI_REGA3            0xA3
-#define SB_SMI_REGA4            0xA4
-#define SB_SMI_REGA5            0xA5
-#define SB_SMI_REGA6            0xA6
-#define SB_SMI_REGA7            0xA7
-#define SB_SMI_REGA8            0xA8
-#define SB_SMI_REGA9            0xA9
-#define SB_SMI_REGAA            0xAA
-#define SB_SMI_REGAB            0xAB
-#define SB_SMI_REGAC            0xAC
-#define SB_SMI_REGAD            0xAD
-#define SB_SMI_REGAE            0xAE
-#define SB_SMI_REGAF            0xAF
-#define SB_SMI_REGB0            0xB0
-#define SB_SMI_REGB1            0xB1
-#define SB_SMI_REGB2            0xB2
-#define SB_SMI_REGB3            0xB3
-#define SB_SMI_REGB4            0xB4
-#define SB_SMI_REGB5            0xB5
-#define SB_SMI_REGB6            0xB6
-#define SB_SMI_REGB7            0xB7
-#define SB_SMI_REGB8            0xB8
-#define SB_SMI_REGB9            0xB9
-#define SB_SMI_REGBA            0xBA
-#define SB_SMI_REGBB            0xBB
-#define SB_SMI_REGBC            0xBC
-#define SB_SMI_REGBD            0xBD
-#define SB_SMI_REGBE            0xBE
-#define SB_SMI_REGBF            0xBF
-#define SB_SMI_REGC0            0xC0
-#define SB_SMI_REGC1            0xC1
-#define SB_SMI_REGC2            0xC2
-#define SB_SMI_REGC3            0xC3
-#define SB_SMI_REGC4            0xC4
-#define SB_SMI_REGC5            0xC5
-#define SB_SMI_REGC6            0xC6
-#define SB_SMI_REGC7            0xC7
-#define SB_SMI_REGC8            0xC8
-#define SB_SMI_REGCA            0xCA         //  IoTrapping1
-#define SB_SMI_REGCC            0xCC         //  IoTrapping2
-#define SB_SMI_REGCE            0xCE         //  IoTrapping3
-#define SB_SMI_REGD0            0xD0         //  MemTrapping0
-#define SB_SMI_REGD4            0xD4         //  MemRdOvrData0
-#define SB_SMI_REGD8            0xD8         //  MemTrapping1
-#define SB_SMI_REGDC            0xDC         //  MemRdOvrData1
-#define SB_SMI_REGE0            0xE0         //  MemTrapping2
-#define SB_SMI_REGE4            0xE4         //  MemRdOvrData2
-#define SB_SMI_REGE8            0xE8         //  MemTrapping3
-#define SB_SMI_REGEC            0xEC         //  MemRdOvrData3
-#define SB_SMI_REGF0            0xF0         //  CfgTrapping0
-#define SB_SMI_REGF4            0xF4         //  CfgTrapping1
-#define SB_SMI_REGF8            0xF8         //  CfgTrapping2
-#define SB_SMI_REGFC            0xFC         //  CfgTrapping3
-
-//
-//  Hudson-2 SB MMIO Base (PMIO)
-//    offset : 0x300
-//
-#define SB_PMIOA_REG00          0x00        // ISA Decode
-#define SB_PMIOA_REG04          0x04        // ISA Control
-#define SB_PMIOA_REG08          0x08        // PCI Control
-#define SB_PMIOA_REG0C          0x0C        // StpClkSmaf
-#define SB_PMIOA_REG10          0x10        // RetryDetect
-#define SB_PMIOA_REG14          0x14        // StuckDetect
-#define SB_PMIOA_REG20          0x20        // BiosRamEn
-#define SB_PMIOA_REG24          0x24        //  AcpiMmioEn
-#define SB_PMIOA_REG28          0x28         // AsfEn
-#define SB_PMIOA_REG2C          0x2C         // Smbus0En
-#define SB_PMIOA_REG2E          0x2E         // Smbus0Sel
-#define SB_PMIOA_REG34          0x34         // IoApicEn
-#define SB_PMIOA_REG3C          0x3C         // SmartVoltEn
-#define SB_PMIOA_REG40          0x40         // SmartVolt2En
-#define SB_PMIOA_REG44          0x44         // BootTimerEn
-#define SB_PMIOA_REG48          0x48         // WatchDogTimerEn
-#define SB_PMIOA_REG4C          0x4C         // WatchDogTimerConfig
-#define SB_PMIOA_REG50          0x50         // HPETEn
-#define SB_PMIOA_REG54          0x54         // SerialIrqConfig
-#define SB_PMIOA_REG56          0x56         // RtcControl
-#define SB_PMIOA_REG57          0x57         //
-#define SB_PMIOA_REG58          0x58         // VRT_T1
-#define SB_PMIOA_REG59          0x59         // VRT_T2
-#define SB_PMIOA_REG5A          0x5A         // IntruderControl
-#define SB_PMIOA_REG5B          0x5B         // RtcShadow
-#define SB_PMIOA_REG5C          0x5C
-#define SB_PMIOA_REG5D          0x5D
-#define SB_PMIOA_REG5E          0x5E         // RtcExtIndex
-#define SB_PMIOA_REG5F          0x5F         // RtcExtData
-#define SB_PMIOA_REG60          0x60         // AcpiPm1EvtBlk
-#define SB_PMIOA_REG62          0x62         // AcpiPm1CntBlk
-#define SB_PMIOA_REG64          0x64         // AcpiPmTmrBlk
-#define SB_PMIOA_REG66          0x66         // P_CNTBlk
-#define SB_PMIOA_REG68          0x68         // AcpiGpe0Blk
-#define SB_PMIOA_REG6A          0x6A         // AcpiSmiCmd
-#define SB_PMIOA_REG6C          0x6C         // AcpiPm2CntBlk
-#define SB_PMIOA_REG6E          0x6E         // AcpiPmaCntBlk
-#define SB_PMIOA_REG74          0x74         // AcpiConfig
-#define SB_PMIOA_REG78          0x78         // WakeIoAddr
-#define SB_PMIOA_REG7A          0x7A         // HaltCountEn
-#define SB_PMIOA_REG7C          0x7C         // C1eWrPortAdr
-#define SB_PMIOA_REG7E          0x7E         // CStateEn
-#define SB_PMIOA_REG80          0x80         // BreakEvent
-#define SB_PMIOA_REG84          0x84         // AutoArbEn
-#define SB_PMIOA_REG88          0x88         // CStateControl
-#define SB_PMIOA_REG89          0x89         //
-#define SB_PMIOA_REG8C          0x8C         // StpClkHoldTime
-#define SB_PMIOA_REG8E          0x8E         // PopUpEndTime
-#define SB_PMIOA_REG90          0x90         // C4Control
-#define SB_PMIOA_REG94          0x94         // CStateTiming0
-#define SB_PMIOA_REG96          0x96         //
-#define SB_PMIOA_REG97          0x97         //
-#define SB_PMIOA_REG98          0x98         // CStateTiming1
-#define SB_PMIOA_REG99          0x99         //
-#define SB_PMIOA_REG9B          0x9B         //
-#define SB_PMIOA_REG9C          0x9C         // C2Count
-#define SB_PMIOA_REG9D          0x9D         // C3Count
-#define SB_PMIOA_REG9E          0x9E         // C4Count
-#define SB_PMIOA_REGA0          0xA0         // MessageCState
-#define SB_PMIOA_REGA4          0xA4         //
-#define SB_PMIOA_REGA8          0xA8         // TrafficMonitorIdleTime
-#define SB_PMIOA_REGAA          0xAA         // TrafficMonitorIntTime
-#define SB_PMIOA_REGAC          0xAC         // TrafficMonitorTrafficCount
-#define SB_PMIOA_REGAE          0xAE         // TrafficMonitorIntrCount
-#define SB_PMIOA_REGB0          0xB0         // TrafficMonitorTimeTick
-#define SB_PMIOA_REGB4          0xB4         // FidVidControl
-#define SB_PMIOA_REGB6          0xB6         // TPRESET1
-#define SB_PMIOA_REGB7          0xB7         // Tpreset1b
-#define SB_PMIOA_REGB8          0xB8         // TPRESET2
-#define SB_PMIOA_REGB9          0xB9         // Test0
-#define SB_PMIOA_REGBA          0xBA         // S_StateControl
-#define SB_PMIOA_REGBB          0xBB         //
-#define SB_PMIOA_REGBC          0xBC         // ThrottlingControl
-#define SB_PMIOA_REGBE          0xBE         // ResetControl
-#define SB_PMIOA_REGBF          0xBF         // ResetControl
-#define SB_PMIOA_REGC0          0xC0         // S5Status
-#define SB_PMIOA_REGC2          0xC2         // ResetStatus
-#define SB_PMIOA_REGC4          0xC4         // ResetCommand
-#define SB_PMIOA_REGC5          0xC5         // CF9Shadow
-#define SB_PMIOA_REGC6          0xC6         // HTControl
-#define SB_PMIOA_REGC8          0xC8         // Misc
-#define SB_PMIOA_REGCC          0xCC         // IoDrvSth
-#define SB_PMIOA_REGD0          0xD0         // CLKRunEn
-#define SB_PMIOA_REGD2          0xD2         // PmioDebug
-#define SB_PMIOA_REGD3          0xD3         // SD
-#define SB_PMIOA_REGD6          0xD6         // IMCGating
-#define SB_PMIOA_REGD8          0xD8         // MiscIndex
-#define SB_PMIOA_REGD9          0xD9         // MiscData
-#define SB_PMIOA_REGDA          0xDA         // SataConfig
-#define SB_PMIOA_REGDC          0xDC         // HyperFlashConfig
-#define SB_PMIOA_REGDE          0xDE         // ABConfig
-#define SB_PMIOA_REGE0          0xE0         // ABRegBar
-#define SB_PMIOA_REGE6          0xE6         // FcEn
-#define SB_PMIOA_REGE7          0xE7
-#define SB_PMIOA_REGEA          0xEA         // PcibConfig
-#define SB_PMIOA_REGEB          0xEB         // AzEn
-#define SB_PMIOA_REGEC          0xEC         // LpcGating
-#define SB_PMIOA_REGED          0xED         // UsbGating
-#define SB_PMIOA_REGEE          0xEE         // UsbCntrl
-#define SB_PMIOA_REGEF          0xEF         // UsbEnable
-#define SB_PMIOA_REGF0          0xF0         // UsbControl
-#define SB_PMIOA_REGF3          0xF3         // UsbDebug
-#define SB_PMIOA_REGF6          0xF6         // GecEn
-#define SB_PMIOA_REGF8          0xF8         // GecConfig
-#define SB_PMIOA_REGFC          0xFC         // TraceMemoryEn
-
-//
-//  Hudson-2 SB MMIO Base (PMIO2)
-//    offset : 0x400
-//
-#define SB_PMIO2_REG00          0x00        // Fan0InputControl
-#define SB_PMIO2_REG01          0x01        // Fan0Control
-#define SB_PMIO2_REG02          0x02        // Fan0Freq
-#define SB_PMIO2_REG03          0x03        // LowDuty0
-#define SB_PMIO2_REG04          0x04        // MidDuty0
-
-#define SB_PMIO2_REG10          0x00        // Fan1InputControl
-#define SB_PMIO2_REG11          0x01        // Fan1Control
-#define SB_PMIO2_REG12          0x02        // Fan1Freq
-#define SB_PMIO2_REG13          0x03        // LowDuty1
-#define SB_PMIO2_REG14          0x04        // MidDuty1
-
-#define SB_PMIO2_REG63          0x63        // SampleFreqDiv
-#define SB_PMIO2_REG69          0x69        // Fan0 Speed
-#define SB_PMIO2_REG95          0x95        // Temperature
-#define SB_PMIO2_REGB8          0xB8        // Voltage
-#define SB_PMIO2_REGEA          0xEA        // Hwm_Calibration
-
-#define SB_PMIO2_REG92          0x92        //
-#define SB_PMIO2_REGF8          0xF8        // VoltageSamleSel
-#define SB_PMIO2_REGF9          0xF9        // TempSampleSel
-
-#define SB_PMIO2_REG          0xFC         // TraceMemoryEn
-
-
-//
-//  Hudson-2 SB MMIO Base (GPIO/IoMux)
-//    offset : 0x100/0xD00
-//
-/*
-GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226.
-*/
-#define SB_GPIO_REG00           0x00
-#define SB_GPIO_REG06           0x06
-#define SB_GPIO_REG09           0x09
-#define SB_GPIO_REG10           0x0A
-#define SB_GPIO_REG17           0x11
-#define SB_GPIO_REG21           0x15
-#define SB_GPIO_REG28           0x1C
-#define SB_GPIO_REG32           0x20
-#define SB_GPIO_REG33           0x21
-#define SB_GPIO_REG34           0x22
-#define SB_GPIO_REG35           0x23
-#define SB_GPIO_REG36           0x24
-#define SB_GPIO_REG37           0x25
-#define SB_GPIO_REG38           0x26
-#define SB_GPIO_REG39           0x27
-#define SB_GPIO_REG40           0x28
-#define SB_GPIO_REG41           0x29
-#define SB_GPIO_REG42           0x2A
-#define SB_GPIO_REG43           0x2B
-#define SB_GPIO_REG44           0x2C
-#define SB_GPIO_REG45           0x2D
-#define SB_GPIO_REG46           0x2E
-#define SB_GPIO_REG47           0x2F
-#define SB_GPIO_REG48           0x30
-#define SB_GPIO_REG49           0x31
-#define SB_GPIO_REG50           0x32
-#define SB_GPIO_REG51           0x33
-#define SB_GPIO_REG52           0x34
-#define SB_GPIO_REG53           0x35
-#define SB_GPIO_REG54           0x36
-#define SB_GPIO_REG55           0x37
-#define SB_GPIO_REG56           0x38
-#define SB_GPIO_REG57           0x39
-#define SB_GPIO_REG58           0x3A
-#define SB_GPIO_REG59           0x3B
-#define SB_GPIO_REG60           0x3C
-#define SB_GPIO_REG61           0x3D
-#define SB_GPIO_REG62           0x3E
-#define SB_GPIO_REG63           0x3F
-#define SB_GPIO_REG64           0x40
-#define SB_GPIO_REG65           0x41
-#define SB_GPIO_REG66           0x42
-#define SB_GPIO_REG67           0x43
-
-#define SB_GEVENT_REG00         0x60
-#define SB_GEVENT_REG01         0x61
-#define SB_GEVENT_REG02         0x62
-#define SB_GEVENT_REG03         0x63
-#define SB_GEVENT_REG04         0x64
-#define SB_GEVENT_REG05         0x65
-#define SB_GEVENT_REG06         0x66
-#define SB_GEVENT_REG07         0x67
-#define SB_GEVENT_REG08         0x68
-#define SB_GEVENT_REG09         0x69
-#define SB_GEVENT_REG10         0x6A
-#define SB_GEVENT_REG11         0x6B
-#define SB_GEVENT_REG12         0x6C
-#define SB_GEVENT_REG13         0x6D
-#define SB_GEVENT_REG14         0x6E
-#define SB_GEVENT_REG15         0x6F
-#define SB_GEVENT_REG16         0x70
-#define SB_GEVENT_REG17         0x71
-#define SB_GEVENT_REG18         0x72
-#define SB_GEVENT_REG19         0x73
-#define SB_GEVENT_REG20         0x74
-#define SB_GEVENT_REG21         0x75
-#define SB_GEVENT_REG22         0x76
-#define SB_GEVENT_REG23         0x77
-// S5-DOMAIN GPIO
-#define SB_GPIO_REG160          0xA0
-#define SB_GPIO_REG161          0xA1
-#define SB_GPIO_REG162          0xA2
-#define SB_GPIO_REG163          0xA3
-#define SB_GPIO_REG164          0xA4
-#define SB_GPIO_REG165          0xA5
-#define SB_GPIO_REG166          0xA6
-#define SB_GPIO_REG167          0xA7
-#define SB_GPIO_REG168          0xA8
-#define SB_GPIO_REG169          0xA9
-#define SB_GPIO_REG170          0xAA
-#define SB_GPIO_REG171          0xAB
-#define SB_GPIO_REG172          0xAC
-#define SB_GPIO_REG173          0xAD
-#define SB_GPIO_REG174          0xAE
-#define SB_GPIO_REG175          0xAF
-#define SB_GPIO_REG176          0xB0
-#define SB_GPIO_REG177          0xB1
-#define SB_GPIO_REG178          0xB2
-#define SB_GPIO_REG179          0xB3
-#define SB_GPIO_REG180          0xB4
-#define SB_GPIO_REG181          0xB5
-#define SB_GPIO_REG182          0xB6
-#define SB_GPIO_REG183          0xB7
-#define SB_GPIO_REG184          0xB8
-#define SB_GPIO_REG185          0xB9
-#define SB_GPIO_REG186          0xBA
-#define SB_GPIO_REG187          0xBB
-#define SB_GPIO_REG188          0xBC
-#define SB_GPIO_REG189          0xBD
-#define SB_GPIO_REG190          0xBE
-#define SB_GPIO_REG191          0xBF
-#define SB_GPIO_REG192          0xC0
-#define SB_GPIO_REG193          0xC1
-#define SB_GPIO_REG194          0xC2
-#define SB_GPIO_REG195          0xC3
-#define SB_GPIO_REG196          0xC4
-#define SB_GPIO_REG197          0xC5
-#define SB_GPIO_REG198          0xC6
-#define SB_GPIO_REG199          0xC7
-#define SB_GPIO_REG200          0xC8
-#define SB_GPIO_REG201          0xC9
-#define SB_GPIO_REG202          0xCA
-#define SB_GPIO_REG203          0xCB
-#define SB_GPIO_REG204          0xCC
-#define SB_GPIO_REG205          0xCD
-#define SB_GPIO_REG206          0xCE
-#define SB_GPIO_REG207          0xCF
-#define SB_GPIO_REG208          0xD0
-#define SB_GPIO_REG209          0xD1
-#define SB_GPIO_REG210          0xD2
-#define SB_GPIO_REG211          0xD3
-#define SB_GPIO_REG212          0xD4
-#define SB_GPIO_REG213          0xD5
-#define SB_GPIO_REG214          0xD6
-#define SB_GPIO_REG215          0xD7
-#define SB_GPIO_REG216          0xD8
-#define SB_GPIO_REG217          0xD9
-#define SB_GPIO_REG218          0xDA
-#define SB_GPIO_REG219          0xDB
-#define SB_GPIO_REG220          0xDC
-#define SB_GPIO_REG221          0xDD
-#define SB_GPIO_REG222          0xDE
-#define SB_GPIO_REG223          0xDF
-#define SB_GPIO_REG224          0xF0
-#define SB_GPIO_REG225          0xF1
-#define SB_GPIO_REG226          0xF2
-#define SB_GPIO_REG227          0xF3
-#define SB_GPIO_REG228          0xF4
-
-//
-//  Hudson-2 SB MMIO Base (SMBUS)
-//    offset : 0xA00
-//
-#define SB_SMBUS_REG12           0x12        //   I2CbusConfig
-
-//
-//  Hudson-2 SB MMIO Base (MISC)
-//    offset : 0xE00
-//
-#define SB_MISC_REG00           0x00        //  ClkCntrl0
-/*
-SB_MISC_REG00                   EQU     000h
-  ClkCntrl0                   EQU     0FFFFFFFFh
-*/
-#define SB_MISC_REG04           0x04        //  ClkCntrl1
-/*
-SB_MISC_REG04                   EQU     004h
-  ClkCntrl1                   EQU     0FFFFFFFFh
-*/
-#define SB_MISC_REG08           0x08        //  ClkCntrl2
-/*
-SB_MISC_REG08                   EQU     008h
-  ClkCntrl2                   EQU     0FFFFFFFFh
-*/
-#define SB_MISC_REG0C           0x0C        //  ClkCntrl3
-/*
-SB_MISC_REG0C                   EQU     00Ch
-  ClkCntrl3                   EQU     0FFFFFFFFh
-*/
-#define SB_MISC_REG10           0x10        //  ClkCntrl4
-/*
-SB_MISC_REG10                   EQU     010h
-  ClkCntrl4                   EQU     0FFFFFFFFh
-*/
-#define SB_MISC_REG14           0x14        //   ClkCntrl5
-/*
-SB_MISC_REG14                   EQU     014h
-  ClkCntrl5                   EQU     0FFFFFFFFh
-*/
-#define SB_MISC_REG18           0x18        //   ClkCntrl6
-/*
-SB_MISC_REG18                   EQU     018h
-  ClkCntrl6                   EQU     0FFFFFFFFh
-*/
-#define SB_MISC_REG30           0x30         // OscFreqCounter
-/*
-SB_MISC_REG30                   EQU     030h
-  OscCounter                  EQU     0FFFFFFFFh                  ; The 32bit register shows the number of OSC clock per second.
-*/
-#define SB_MISC_REG34           0x34         //  HpetClkPeriod
-/*
-SB_MISC_REG34                   EQU     034h
-  HpetClkPeriod               EQU     0FFFFFFFFh                  ; default - 0x429B17Eh (14.31818M).
-*/
-#define SB_MISC_REG40           0x40         //  MiscCntrl      for clock only
-#define SB_MISC_REG41           0x41         //  MiscCntr2
-#define SB_MISC_REG42           0x42         //  MiscCntr3
-#define SB_MISC_REG50           0x50         //
-#define SB_MISC_REGB6           0xB6         //
-/*
-SB_MISC_REG40                   EQU     040h
-*/
-
-#define SB_MISC_REG80           0x80        /**< SB_MISC_REG80
-                                   *   @par
-                                   *   StrapStatus [15.0] - Hudson-2 chip Strap Status
-                                   *    @li <b>0001</b> - Not USED FWH
-                                   *    @li <b>0002</b> - Not USED LPC ROM
-                                   *    @li <b>0004</b> - EC enabled
-                                   *    @li <b>0008</b> - Reserved
-                                   *    @li <b>0010</b> - Internal Clock mode
-                                   */
-
-#define  ChipSysNotUseFWHRom    0x0001                            // EcPwm3 pad
-#define  ChipSysNotUseLpcRom    0x0002                            // Inverted version from EcPwm2 pad (default - 1)
-                                                                  // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type.
-#define  ChipSysEcEnable        0x0004                            // Enable Embedded Controller (EC)
-#define  ChipSysBootFailTmrEn   0x0008                            // Enable Watchdog function
-#define  ChipSysIntClkGen       0x0010                            // Select 25Mhz crystal clock or 100Mhz PCI-E clock **
-
-#define SB_MISC_REG84           0x84         //  StrapOverride
-/*
-SB_MISC_REG84                   EQU     084h
-  Override FWHDisableStrap    EQU     BIT0                        ; Override FWHDiableStrap value from external pin.
-  Override UseLpcRomStrap     EQU     BIT1                        ; Override UseLpcRomStrap value from external pin.
-  Override EcEnableStrap      EQU     BIT2                        ; Override EcEnableStrap value from external pin.
-  Override BootFailTmrEnStrap EQU     BIT3                        ; Override BootFailTmrEnStrap value from external pin.
-  Override DefaultModeStrap   EQU     BIT5                        ; Override DefaultModeStrap value from external pin.
-  Override I2CRomStrap        EQU     BIT7                        ; Override I2CRomStrap value from external pin.
-  Override ILAAutorunEnBStrap EQU     BIT8                        ; Override ILAAutorunEnBStrap value from external pin.
-  Override FcPllBypStrap      EQU     BIT9                        ; Override FcPllBypStrap value from external pin.
-  Override PciPllBypStrap     EQU     BIT10                       ; Override PciPllBypStrap value from external pin.
-  Override ShortResetStrap    EQU     BIT11                       ; Override ShortResetStrap value from external pin.
-  Override FastBif2ClkStrap   EQU     BIT13                       ; Override FastBif2ClkStrap value from external pin'
-  PciRomBootStrap             EQU     BIT15                       ; Override PCI Rom Boot Strap value from external pin ?? Not match 0x80 reg ??
-  BlinkSlowModestrap          EQU     BIT16                       ; Override Blink Slow mode (100Mhz) from external pin'
-  ClkGenStrap                 EQU     BIT17                       ; Override CLKGEN from external pin.
-  BIF_GEN2_COMPL_Strap        EQU     BIT18                       ; Override BIF_ GEN2_COMPLIANCE strap from external pin.
-  StrapOverrideEn             EQU     BIT31                       ; Enable override strapping feature.
-*/
-#define SB_MISC_REGC0           0xC0        //  CPU_Pstate0
-/*
-SB_MISC_REGC0                   EQU     0C0h
-  Core0_PState                EQU     BIT0+BIT1+BIT2              ; 000: P0  001: P1  010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
-  Core1_PState                EQU     BIT4+BIT5+BIT6
-  Core2_PState                EQU     BIT8+BIT9+BIT10
-  Core3_PState                EQU     BIT12+BIT13+BIT14
-  Core4_PState                EQU     BIT16++BIT17+BIT18
-  Core5_PState                EQU     BIT20+BIT21+BIT22
-  Core6_PState                EQU     BIT24+BIT25+BIT26
-  Core7_PState                EQU     BIT28+BIT29+BIT30
-*/
-#define SB_MISC_REGC4           0xC4         //  CPU_Pstate1
-/*
-SB_MISC_REGC4                   EQU     0C4h
-  Core8_PState                EQU     BIT0+BIT1+BIT2              ; 000: P0  001: P1  010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
-  Core9_PState                EQU     BIT4+BIT5+BIT6
-  Core10_PState               EQU     BIT8+BIT9+BIT10
-  Core11_PState               EQU     BIT12+BIT13+BIT14
-  Core12_PState               EQU     BIT16++BIT17+BIT18
-  Core13_PState               EQU     BIT20+BIT21+BIT22
-  Core14_PState               EQU     BIT24+BIT25+BIT26
-  Core15_PState               EQU     BIT28+BIT29+BIT30
-*/
-#define SB_MISC_REGD0           0xD0         //  CPU_Cstate0
-/*
-SB_MISC_REGD0                   EQU     0D0h
-  Core0_CState                EQU     BIT0+BIT1+BIT2              ; 000: C0  001: C1  010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
-  Core1_CState                EQU     BIT4+BIT5+BIT6
-  Core2_CState                EQU     BIT8+BIT9+BIT10
-  Core3_CState                EQU     BIT12+BIT13+BIT14
-  Core4_CState                EQU     BIT16++BIT17+BIT18
-  Core5_CState                EQU     BIT20+BIT21+BIT22
-  Core6_CState                EQU     BIT24+BIT25+BIT26
-  Core7_CState                EQU     BIT28+BIT29+BIT30
-*/
-#define SB_MISC_REGD4           0xD4         //  CPU_Cstate1
-/*
-SB_MISC_REGD4                   EQU     0D4h
-  Core8_CState                EQU     BIT0+BIT1+BIT2              ; 000: C0  001: C1  010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
-  Core9_CState                EQU     BIT4+BIT5+BIT6
-  Core10_CState               EQU     BIT8+BIT9+BIT10
-  Core11_CState               EQU     BIT12+BIT13+BIT14
-  Core12_CState               EQU     BIT16++BIT17+BIT18
-  Core13_CState               EQU     BIT20+BIT21+BIT22
-  Core14_CState               EQU     BIT24+BIT25+BIT26
-  Core15_CState               EQU     BIT28+BIT29+BIT30
-*/
-#define SB_MISC_REGF0           0xF0         //  SataPortSts    ?? EC touch only
-/*
-SB_MISC_REGF0                   EQU     0F0h
-  Port0Sts                    EQU     BIT0                        ; The selected status of Port 0.
-  Port1Sts                    EQU     BIT1                        ; The selected status of Port 1
-  Port2Sts                    EQU     BIT2                        ; The selected status of Port 2.
-  Port3Sts                    EQU     BIT3                        ; The selected status of Port 3
-  Port4Sts                    EQU     BIT4                        ; The selected status of Port 4.
-  Port5Sts                    EQU     BIT5                        ; The selected status of Port 5
-  SataPortSel                 EQU     BIT24+BIT25                 ; 00  - Select "led" for Port 0 to 5
-                                  ; 01 - Select "delete" for Port 0 to 5
-                                  ; 10 - Select "err" for Port 0 to 5
-                                  ; 11 - Select "led" for Port 0 to 5
-*/
-
-//
-//  Hudson-2 SB MMIO Base (SERIAL_DEBUG_BASE)
-//    offset : 0x1000
-//
-#define SB_SDB_REG00            0x00        //
-#define SB_SDB_REG74            0x74
-
-#define SB_RTC_REG00            0x00        // Seconds - RW
-#define SB_RTC_REG01            0x01        // Seconds Alarm - RW
-#define SB_RTC_REG02            0x02        // Minutes - RW
-#define SB_RTC_REG03            0x03        // Minutes Alarm - RW
-#define SB_RTC_REG04            0x04        // ours - RW
-#define SB_RTC_REG05            0x05        // ours Alarm- RW
-#define SB_RTC_REG06            0x06        // Day of Week - RW
-#define SB_RTC_REG07            0x07        // Date of Mont - RW
-#define SB_RTC_REG08            0x08        // Mont - RW
-#define SB_RTC_REG09            0x09        // Year - RW
-#define SB_RTC_REG0A            0x0A        // Register A - RW
-#define SB_RTC_REG0B            0x0B        // Register B - RW
-#define SB_RTC_REG0C            0x0C        // Register C - R
-#define SB_RTC_REG0D            0x0D        // DateAlarm - RW
-#define SB_RTC_REG32            0x32        // AltCentury - RW
-#define SB_RTC_REG48            0x48        // Century - RW
-#define SB_RTC_REG50            0x50        // Extended RAM Address Port - RW
-#define SB_RTC_REG53            0x53        // Extended RAM Data Port - RW
-#define SB_RTC_REG7E            0x7E        // RTC Time Clear - RW
-#define SB_RTC_REG7F            0x7F        // RTC RAM Enable - RW
-
-#define SB_ECMOS_REG00           0x00        // scratch - reg
-//;BIT0=0   AsicDebug is enabled
-//;BIT1=0   SLT S3 runs
-#define SB_ECMOS_REG01          0x01
-#define SB_ECMOS_REG02          0x02
-#define SB_ECMOS_REG03          0x03
-#define SB_ECMOS_REG04          0x04
-#define SB_ECMOS_REG05          0x05
-#define SB_ECMOS_REG06          0x06
-#define SB_ECMOS_REG07          0x07
-#define SB_ECMOS_REG08          0x08        // save 32BIT Physical address of Config structure
-#define SB_ECMOS_REG09          0x09
-#define SB_ECMOS_REG0A          0x0A
-#define SB_ECMOS_REG0B          0x0B
-
-#define SB_ECMOS_REG0C          0x0C        //;save MODULE_ID
-#define SB_ECMOS_REG0D          0x0D        //;Reserve for NB
-
-#define SB_IOMAP_REG00          0x000   // Dma_C 0
-#define SB_IOMAP_REG02          0x002   // Dma_C 1
-#define SB_IOMAP_REG04          0x004   // Dma_C 2
-#define SB_IOMAP_REG06          0x006   // Dma_C 3
-#define SB_IOMAP_REG08          0x008   // Dma_Status
-#define SB_IOMAP_REG09          0x009   // Dma_WriteRest
-#define SB_IOMAP_REG0A          0x00A   // Dma_WriteMask
-#define SB_IOMAP_REG0B          0x00B   // Dma_WriteMode
-#define SB_IOMAP_REG0C          0x00C   // Dma_Clear
-#define SB_IOMAP_REG0D          0x00D   // Dma_MasterClr
-#define SB_IOMAP_REG0E          0x00E   // Dma_ClrMask
-#define SB_IOMAP_REG0F          0x00F   // Dma_AllMask
-#define SB_IOMAP_REG20          0x020   // IntrCntrlReg1
-#define SB_IOMAP_REG21          0x021   // IntrCntrlReg2
-#define SB_IOMAP_REG40          0x040   // TimerC0
-#define SB_IOMAP_REG41          0x041   // TimerC1
-#define SB_IOMAP_REG42          0x042   // TimerC2
-#define SB_IOMAP_REG43          0x043   // Tmr1CntrlWord
-#define SB_IOMAP_REG61          0x061   // Nmi_Status
-#define SB_IOMAP_REG70          0x070   // Nmi_Enable
-#define SB_IOMAP_REG71          0x071   // RtcDataPort
-#define SB_IOMAP_REG72          0x072   // AlternatRtcAddrPort
-#define SB_IOMAP_REG73          0x073   // AlternatRtcDataPort
-#define SB_IOMAP_REG80          0x080   // Dma_Page_Reserved0
-#define SB_IOMAP_REG81          0x081   // Dma_PageC2
-#define SB_IOMAP_REG82          0x082   // Dma_PageC3
-#define SB_IOMAP_REG83          0x083   // Dma_PageC1
-#define SB_IOMAP_REG84          0x084   // Dma_Page_Reserved1
-#define SB_IOMAP_REG85          0x085   // Dma_Page_Reserved2
-#define SB_IOMAP_REG86          0x086   // Dma_Page_Reserved3
-#define SB_IOMAP_REG87          0x087   // Dma_PageC0
-#define SB_IOMAP_REG88          0x088   // Dma_Page_Reserved4
-#define SB_IOMAP_REG89          0x089   // Dma_PageC6
-#define SB_IOMAP_REG8A          0x08A   // Dma_PageC7
-#define SB_IOMAP_REG8B          0x08B   // Dma_PageC5
-#define SB_IOMAP_REG8C          0x08C   // Dma_Page_Reserved5
-#define SB_IOMAP_REG8D          0x08D   // Dma_Page_Reserved6
-#define SB_IOMAP_REG8E          0x08E   // Dma_Page_Reserved7
-#define SB_IOMAP_REG8F          0x08F   // Dma_Refres
-#define SB_IOMAP_REG92          0x092   // FastInit
-#define SB_IOMAP_REGA0          0x0A0   // IntrCntrl2Reg1
-#define SB_IOMAP_REGA1          0x0A1   // IntrCntrl2Reg2
-#define SB_IOMAP_REGC0          0x0C0   // Dma2_C4Addr
-#define SB_IOMAP_REGC2          0x0C2   // Dma2_C4Cnt
-#define SB_IOMAP_REGC4          0x0C4   // Dma2_C5Addr
-#define SB_IOMAP_REGC6          0x0C6   // Dma2_C5Cnt
-#define SB_IOMAP_REGC8          0x0C8   // Dma2_C6Addr
-#define SB_IOMAP_REGCA          0x0CA   // Dma2_C6Cnt
-#define SB_IOMAP_REGCC          0x0CC   // Dma2_C7Addr
-#define SB_IOMAP_REGCE          0x0CE   // Dma2_C7Cnt
-#define SB_IOMAP_REGD0          0x0D0   // Dma_Status
-#define SB_IOMAP_REGD2          0x0D2   // Dma_WriteRest
-#define SB_IOMAP_REGD4          0x0D4   // Dma_WriteMask
-#define SB_IOMAP_REGD6          0x0D6   // Dma_WriteMode
-#define SB_IOMAP_REGD8          0x0D8   // Dma_Clear
-#define SB_IOMAP_REGDA          0x0DA   // Dma_Clear
-#define SB_IOMAP_REGDC          0x0DC   // Dma_ClrMask
-#define SB_IOMAP_REGDE          0x0DE   // Dma_ClrMask
-#define SB_IOMAP_REGF0          0x0F0   // NCP_Error
-#define SB_IOMAP_REG40B         0x040B  // DMA1_Extend
-#define SB_IOMAP_REG4D0         0x04D0  // IntrEdgeControl
-#define SB_IOMAP_REG4D6         0x04D6  // DMA2_Extend
-#define SB_IOMAP_REGC00         0x0C00  // Pci_Intr_Index
-#define SB_IOMAP_REGC01         0x0C01  // Pci_Intr_Data
-#define SB_IOMAP_REGC14         0x0C14  // Pci_Error
-#define SB_IOMAP_REGC50         0x0C50  // CMIndex
-#define SB_IOMAP_REGC51         0x0C51  // CMData
-#define SB_IOMAP_REGC52         0x0C52  // GpmPort
-#define SB_IOMAP_REGC6F         0x0C6F  // Isa_Misc
-#define SB_IOMAP_REGCD0         0x0CD0  // PMio2_Index
-#define SB_IOMAP_REGCD1         0x0CD1  // PMio2_Data
-#define SB_IOMAP_REGCD4         0x0CD4  // BIOSRAM_Index
-#define SB_IOMAP_REGCD5         0x0CD5  // BIOSRAM_Data
-#define SB_IOMAP_REGCD6         0x0CD6  // PM_Index
-#define SB_IOMAP_REGCD7         0x0CD7  // PM_Data
-#define SB_IOMAP_REGCF9         0x0CF9          // CF9Rst reg
-
-
-#define SB_SPI_MMIO_REG00       0x00        //SPI_
-#define SB_SPI_MMIO_REG0C       0x0C        //SPI_Cntrl1 Register
-#define SB_SPI_MMIO_REG1C       0x1C        //
-
-#define SB_SPI_MODE_FAST        0x7        //
-#define SB_SPI_MODE_NORMAL      0x6        //
-#define SB_SPI_MODE_QUAL_144    0x5        //
-#define SB_SPI_MODE_QUAL_122    0x4        //
-#define SB_SPI_MODE_QUAL_114    0x3        //
-#define SB_SPI_MODE_QUAL_112    0x2        //
-
-#define AMD_NB_REG78            0x78
-#define AMD_NB_SCRATCH          AMD_NB_REG78
-#define MailBoxPort             0x3E
-
-// GPP Link Configuration
-#define GPP_CFGMODE_X4000       0x0
-#define GPP_CFGMODE_X2200       0x2
-#define GPP_CFGMODE_X2110       0x3
-#define GPP_CFGMODE_X1111       0x4
-
-#define MAX_LT_POLLINGS         0x4000
-
-
-#define ACPIMMIO32(x) (*(unsigned int*)(uintptr_t)(x))
-#define ACPIMMIO16(x) (*(unsigned short*)(uintptr_t)(x))
-#define ACPIMMIO8(x)  (*(unsigned char*)(uintptr_t)(x))
-
-#ifdef XHCI_SUPPORT
-  #define XHCI_ACPI_MMIO_AMD_REG00     0x00
-  #define U3PLL_LOCK                   BIT7
-  #define U3PLL_RESET                  BIT8
-  #define U3PHY_RESET                  BIT9
-  #define U3CORE_RESET                 BIT10
-  #define XHC0_FUNC_RESET              BIT11
-  #define XHC1_FUNC_RESET              BIT12
-
-  #define XHCI_ACPI_MMIO_AMD_REG04     0x04
-  #define XHCI_ACPI_MMIO_AMD_REG08     0x08
-  #define XHCI_ACPI_MMIO_AMD_REG10     0x10
-  #define XHCI_ACPI_MMIO_AMD_REG20     0x20
-  #define XHCI_ACPI_MMIO_AMD_REG88     0x88
-  #define XHCI_ACPI_MMIO_AMD_REG90     0x90 // adaptation timer settings
-  #define XHCI_ACPI_MMIO_AMD_REG98     0x98 //
-  #define XHCI_ACPI_MMIO_AMD_REGA0     0xA0 // BAR 0
-  #define XHCI_ACPI_MMIO_AMD_REGA4     0xA4 // BAR 1
-  #define XHCI_ACPI_MMIO_AMD_REGA8     0xA8 // BAR 2
-  #define XHCI_ACPI_MMIO_AMD_REGB0     0xB0 // SPI_Valid_Base.
-  #define XHCI_ACPI_MMIO_AMD_REGC0     0xC0 // Firmware starting offset for coping
-  #define XHCI_ACPI_MMIO_AMD_REGB4     0xB4
-  #define XHCI_ACPI_MMIO_AMD_REGD0     0xD0
-
-  #define SB_XHCI_REG48                0x48 // XHCI IND_REG Index registers
-  #define SB_XHCI_REG4C                0x4C // XHCI IND_REG Data registers
-
-  #define SB_XHCI_IND_REG00            0x00 //
-  #define SB_XHCI_IND_REG04            0x04 //
-  #define SB_XHCI_IND_REG94            0x94 // adaptation mode settings
-  #define SB_XHCI_IND_REG98            0x98 // CR phase and frequency filter settings
-  #define SB_XHCI_IND_REGD4            0xD4 // adaptation mode settings
-  #define SB_XHCI_IND_REGD8            0xD8 // CR phase and frequency filter settings
-
-  #define SB_XHCI_IND60_BASE            0x40000000 //
-
-  #define SB_XHCI_IND60_REG00          SB_XHCI_IND60_BASE + 0x00 //
-  #define SB_XHCI_IND60_REG04          SB_XHCI_IND60_BASE + 0x04 //
-  #define SB_XHCI_IND60_REG08          SB_XHCI_IND60_BASE + 0x08 //
-  #define SB_XHCI_IND60_REG0C          SB_XHCI_IND60_BASE + 0x0C //
-
-  #define SPI_HEAD_LENGTH 0x0E
-  #define SPI_BAR0_VLD  0x01
-  #define SPI_BASE0     (0x00 << 7)
-  #define SPI_BAR1_VLD  (0x01 << 8)
-  #define SPI_BASE1     (SPI_HEAD_LENGTH << 10)
-  #define SPI_BAR2_VLD  (0x01 << 16)
-  #define SPI_BASE2(x)  ((SPI_HEAD_LENGTH + ACPIMMIO16(x)) << 18)
-
-  #define FW_TO_SIGADDR_OFFSET  0x0C
-  #define BCD_ADDR_OFFSET       0x02
-  #define BCD_SIZE_OFFSET       0x04
-  #define FW_ADDR_OFFSET        0x06
-  #define FW_SIZE_OFFSET        0x08
-  #define ACD_ADDR_OFFSET       0x0A
-  #define ACD_SIZE_OFFSET       0x0C
-
-#endif
-
-#define PKT_DATA_REG       ACPI_MMIO_BASE + GFX_DAC_BASE + 0x00
-#define PKT_LEN_REG        ACPI_MMIO_BASE + GFX_DAC_BASE + 0x14
-#define PKT_CTRL_REG       ACPI_MMIO_BASE + GFX_DAC_BASE + 0x15
-#define EFUS_DAC_ADJUSTMENT_CONTROL    0x850A8
-#define BGADJ                             0x1F
-#define DACADJ                            0x1B
-#define EFUS_DAC_ADJUSTMENT_CONTROL_DATA  (BGADJ + (DACADJ << 8) + BIT16 )
-
-//#define SB_USB1_OVER_CURRENT_CONTROL                            0x11111111
-//#define SB_USB2_OVER_CURRENT_CONTROL                            0x22222222
-//#define SB_USB3_OVER_CURRENT_CONTROL                            0x33333333
-//#define SB_USB4_OVER_CURRENT_CONTROL                            0x44444444
-//#define SB_XHCI0_OVER_CURRENT_CONTROL                           0x55555555
-//#define SB_XHCI1_OVER_CURRENT_CONTROL                           0x66666666
-
-#pragma pack (pop)
-
diff --git a/src/vendorcode/amd/cimx/sb900/Hwm.c b/src/vendorcode/amd/cimx/sb900/Hwm.c
deleted file mode 100644
index 86fd2f8637..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Hwm.c
+++ /dev/null
@@ -1,578 +0,0 @@
-/**
- * @file
- *
- * Southbridge Initial routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-//
-// Declaration of local functions
-//
-VOID
-hwmInitRegister (
-  IN       AMDSBCFG* pConfig
-  );
-
-VOID
-hwmGetRawData (
-  IN       AMDSBCFG* pConfig
-  );
-
-VOID
-hwmCaculate (
-  IN       AMDSBCFG* pConfig
-  );
-
-VOID
-hwmGetCalibrationFactor (
-  IN       AMDSBCFG* pConfig
-  );
-
-VOID
-hwmProcessParameter (
-  IN       AMDSBCFG* pConfig
-  );
-
-VOID
-hwmSetRegister (
-  IN       AMDSBCFG* pConfig
-  );
-
-
-HWM_temp_par_struct tempParDefault[] = {
-  { 5219, 27365 , 0 },
-  { 5222, 27435 , 0 },
-  { 5219, 27516 , BIT0 },  //High Ratio
-  { 5221, 27580 , BIT1 },  //High Current
-  { 5123, 27866 , 0 }
-};
-
-//#ifndef NO_HWM_SUPPORT
-/**
- * hwmInitRegister - Init Hardware Monitor Register.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmInitRegister (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32 LinearRangeOutLimit;
-
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccWidthUint8, 0, 0x55);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccWidthUint8, 0, 0x55);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccWidthUint8, 0, 0x55);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccWidthUint8, 0, 0x55);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccWidthUint8, 0, 0x06);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccWidthUint8, 0, 0x06);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccWidthUint8, 0, 0x06);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccWidthUint8, 0, 0x06);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccWidthUint8, 0, 0x06);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccWidthUint8, 0, 0x01);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccWidthUint8, 0, 0x01);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccWidthUint8, 0, 0x01);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccWidthUint8, 0, 0x01);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccWidthUint8, 0, 0x01);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE6, AccWidthUint8, 0xff, 0x02);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccWidthUint8, 0, 0x05);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccWidthUint8, 0, 0x06);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccWidthUint8, 0, 0x42);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccWidthUint8, 0, 0xFF);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccWidthUint8, 0, 0x1F);
-  //2.13 HWM Sensor Clk
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccWidthUint8, 0, 0x0A);
-  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccWidthUint8, 0, 0x00);
-
-  //2.9 Enhancement of FanOut0 Control
-  //check for fanLinearEnhanceEn
-  if (pConfig->hwm.fanLinearEnhanceEn == 0) {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT11, BIT11);
-    LinearRangeOutLimit = (UINT32) (pConfig->hwm.fanLinearRangeOutLimit);
-    LinearRangeOutLimit = LinearRangeOutLimit << 20;
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4, AccWidthUint32, 0xFF0FFFFF, LinearRangeOutLimit);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT11, 0);
-  }
-  //check for fanLinearHoldFix
-  if (pConfig->hwm.fanLinearHoldFix == 0) {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT20, BIT20);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT20, 0);
-  }
-}
-
-
-/**
- * hwmSbtsiAutoPolling - Hardware Monitor Auto Poll SB-TSI.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmSbtsiAutoPolling (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 dbValue;
-  UINT16 smbusBase;
-
-  smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
-  if (pConfig->hwm.hwmSbtsiAutoPoll == 1) {
-    hwmSbtsiAutoPollingPause (pConfig);
-
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), BIT2);
-    dbValue = 0xff;
-    WriteIO (smbusBase, AccWidthUint8, &dbValue);
-    dbValue = 0x08;
-    WriteIO (smbusBase + 2, AccWidthUint8, &dbValue);
-    dbValue = 0x09;
-    WriteIO (smbusBase + 3, AccWidthUint8, &dbValue);
-    dbValue = 0x98;
-    WriteIO (smbusBase + 4, AccWidthUint8, &dbValue);
-    if ( IsSbA11 () ) {
-      dbValue = 0x00;
-    } else {
-      dbValue = 0x20;
-    }
-    WriteIO (smbusBase + 5, AccWidthUint8, &dbValue);
-    dbValue = 0x48;
-    WriteIO (smbusBase + 2, AccWidthUint8, &dbValue);
-
-    ReadIO (smbusBase + 0, AccWidthUint8, &dbValue);
-    while ( dbValue & BIT0 ) {
-      ReadIO (smbusBase + 0, AccWidthUint8, &dbValue);
-    }
-
-    if ( IsSbA11 () ) {
-      dbValue = 0x09;
-    } else {
-      dbValue = 0x08;
-    }
-    WriteIO (smbusBase + 2, AccWidthUint8, &dbValue);
-    if ( IsSbA11 () ) {
-      dbValue = 0x01;
-    } else {
-      dbValue = 0x10;
-    }
-    WriteIO (smbusBase + 3, AccWidthUint8, &dbValue);
-    dbValue = 0x99;
-    WriteIO (smbusBase + 4, AccWidthUint8, &dbValue);
-    if ( IsSbA11 () ) {
-      dbValue = 0x0f;
-      WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
-    }
-
-    if ( IsSbA12Plus () ) {
-      dbValue = 0x80;
-      WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
-      dbValue = 0x01;
-      WriteIO (smbusBase + 0x17, AccWidthUint8, &dbValue);
-      dbValue = 0x81;
-      WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
-    }
-    //map SB-TSI to tempin0
-    RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + SB_PMIO2_REG92, AccWidthUint8, ~BIT3, BIT3);
-    dbValue = 0x00;
-    WriteIO (smbusBase + 0x16, AccWidthUint8, &dbValue);
-    pConfig->hwm.hwmSbtsiAutoPollStarted = TRUE;
-  } else {
-    hwmSbtsiAutoPollingOff (pConfig);
-  }
-}
-
-/**
- * hwmSbtsiAutoPollingOff - Hardware Monitor Auto Poll SB-TSI
- * Off.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmSbtsiAutoPollingOff (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 dbValue;
-  UINT16 smbusBase;
-
-  if ( pConfig->hwm.hwmEnable ) {
-    smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
-    dbValue = 0x00;
-    WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
-    hwmSbtsiAutoPollingPause (pConfig);
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), 0);
-    RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + SB_PMIO2_REG92, AccWidthUint8, ~BIT3, 0x00);
-    pConfig->hwm.hwmSbtsiAutoPollStarted = FALSE;
-  }
-}
-
-/**
- * hwmSbtsiAutoPollingPause - Pause Hardware Monitor Auto Poll
- * SB-TSI Off.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmSbtsiAutoPollingPause (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 dbValue;
-  UINT16 smbusBase;
-
-  if ( pConfig->hwm.hwmEnable && (pConfig->hwm.hwmSbtsiAutoPoll == 1) ) {
-    smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
-    dbValue = 0x01;
-    WriteIO (smbusBase + 0x16, AccWidthUint8, &dbValue);
-    dbValue = 0x00;
-    while ( dbValue == 0x00 ) {
-      ReadIO (smbusBase + 0x16, AccWidthUint8, &dbValue);
-    }
-  }
-}
-
-/**
- * hwmGetRawData - Hardware Monitor Get Raw Data.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmGetRawData (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 i;
-  UINT16 dwValue;
-//_asm { jmp $ };
-  //fan speed
-  for ( i = 0; i < 5 ; i++ ) {
-    ReadPMIO2 (SB_PMIO2_REG69 + i * 5, AccWidthUint16, &dwValue);
-    if ( (dwValue & 0xFFC0) != 0xFFC0 ) {
-      pConfig->hwm.hwmCurrentRaw.fanSpeed[i] = dwValue;
-    } else {
-      pConfig->hwm.hwmCurrentRaw.fanSpeed[i] = 0xFFFF;
-    }
-  }
-  //temperatue
-  for ( i = 0; i < 5 ; i++ ) {
-    ReadPMIO2 (SB_PMIO2_REG95 + i * 4, AccWidthUint16, &dwValue);
-    if ( ( i == 1 ) || (dwValue > 0x4000) ) {
-      pConfig->hwm.hwmCurrentRaw.temperature[i] = dwValue;
-    }
-  }
-  //voltage
-  for ( i = 0; i < 8 ; i++ ) {
-    ReadPMIO2 (SB_PMIO2_REGB8 + i * 4, AccWidthUint16, &dwValue);
-    if ( (dwValue & 0xFFC0) != 0xFFC0 ) {
-      pConfig->hwm.hwmCurrentRaw.voltage[i] = dwValue;
-    }
-  }
-}
-
-/**
- * hwmCaculate - Hardware Monitor Caculate Raw Data to Display Data.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmCaculate (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 i;
-  UINT16 dwValue;
-  //UINT32 ddValue;
-  //fan speed
-  for ( i = 0; i < 5 ; i++ ) {
-    dwValue = pConfig->hwm.hwmCurrentRaw.fanSpeed[i];
-    if ((dwValue == 0xffff) || (dwValue == 0x0000)) {
-      pConfig->hwm.hwmCurrent.fanSpeed[i] = 0;
-    } else {
-      pConfig->hwm.hwmCurrent.fanSpeed[i] = ( 22720 >> pConfig->hwm.fanSampleFreqDiv ) * 60 / dwValue / 2;
-    }
-  }
-  //temperatue
-  for ( i = 0; i < 5 ; i++ ) {
-    dwValue = pConfig->hwm.hwmCurrentRaw.temperature[i];
-    if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 1)) {
-      if ( IsSbA11 () ) {
-        dwValue = (dwValue >> 8) * 10;
-      } else {
-        dwValue = ((dwValue & 0xff00) >> 8) * 10 + (((dwValue & 0x00ff) * 10 ) >> 8);
-      }
-    } else {
-      dwValue = ((dwValue << 3) * pConfig->hwm.hwmTempPar[i].At / pConfig->hwm.hwmCalibrationFactor / 100 - pConfig->hwm.hwmTempPar[i].Ct) / 10  ;
-    }
-    if ( pConfig->hwm.hwmCurrentRaw.temperature[i] == 0 ) {
-      dwValue = 0;
-    }
-    if ( dwValue < 10000 ) {
-      pConfig->hwm.hwmCurrent.temperature[i] = dwValue;
-    } else {
-      pConfig->hwm.hwmCurrent.temperature[i] = 0;
-    }
-  }
-  //voltage
-  for ( i = 0; i < 8 ; i++ ) {
-    dwValue = pConfig->hwm.hwmCurrentRaw.voltage[i];
-    pConfig->hwm.hwmCurrent.voltage[i] = (dwValue >> 6) * 512 / pConfig->hwm.hwmCalibrationFactor;
-  }
-}
-
-/**
- * hwmGetCalibrationFactor - Hardware Monitor Get Calibration
- * Factor
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmGetCalibrationFactor (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 dbValue;
-//  UINT16 dwValue;
-//  UINT32 ddValue;
-  //temperatue parameter
-  ReadPMIO2 (SB_PMIO2_REGEA, AccWidthUint8, &dbValue);
-  if ( dbValue & BIT7 ) {
-    if ( dbValue & BIT6 ) {pConfig->hwm.hwmCalibrationFactor = 0x100 + dbValue;
-      } else {pConfig->hwm.hwmCalibrationFactor = 0x200 + (dbValue & 0x3f ); }
-  } else {
-    pConfig->hwm.hwmCalibrationFactor = 0x200;
-  }
-}
-
-/**
- * hwmProcessParameter - Hardware Monitor process Parameter
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmProcessParameter (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 i;
-  UINT8 tempChannel;
-  UINT8 dbValue;
-  UINT16 dwValue;
-//  UINT32 ddValue;
-  hwmGetCalibrationFactor (pConfig);
-  //temperatue parameter
-  for ( i = 0; i < 5 ; i++ ) {
-    if ( pConfig->hwm.hwmTempPar[i].At == 0 ) {
-      pConfig->hwm.hwmTempPar[i] = tempParDefault[i];
-    }
-  }
-  for ( i = 0; i < 5 ; i++ ) {
-    if ( pConfig->hwm.hwmFanControl[i].LowDuty_reg03 == 100 ) {
-      pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03 = 255;
-    } else {
-      pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03 = (pConfig->hwm.hwmFanControl[i].LowDuty_reg03 << 8) / 100;
-    }
-    if ( pConfig->hwm.hwmFanControl[i].MedDuty_reg04 == 100 ) {
-      pConfig->hwm.hwmFanControlCooked[i].MedDuty_reg04 = 255;
-    } else {
-      pConfig->hwm.hwmFanControlCooked[i].MedDuty_reg04 = (pConfig->hwm.hwmFanControl[i].MedDuty_reg04 << 8) / 100;
-    }
-
-    if ( pConfig->hwm.hwmFanControl[i].HighTemp_reg0A > pConfig->hwm.hwmFanControl[i].MedTemp_reg08 ) {
-      dbValue = (UINT8) ((256 - pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03) / (pConfig->hwm.hwmFanControl[i].HighTemp_reg0A - pConfig->hwm.hwmFanControl[i].MedTemp_reg08));
-    } else {
-      dbValue = (UINT8) ((256 - pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03));
-    }
-
-    dwValue = pConfig->hwm.hwmFanControl[i].LowTemp_reg06;
-    if (pConfig->hwm.hwmFanControl[i].InputControl_reg00 > 4) {
-      tempChannel = 0;
-    } else {
-      tempChannel = pConfig->hwm.hwmFanControl[i].InputControl_reg00;
-    }
-    if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 0)) {
-      dwValue = dwValue << 8;
-    } else {
-      dbValue = (UINT8) (dbValue * 10000 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At / 512);
-      dwValue = ((dwValue * 100 + pConfig->hwm.hwmTempPar[tempChannel].Ct ) * 100 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At) >> 3;
-    }
-    pConfig->hwm.hwmFanControlCooked[i].LowTemp_reg06 = dwValue;
-    pConfig->hwm.hwmFanControlCooked[i].Multiplier_reg05 = dbValue & 0x3f;
-
-    dwValue = pConfig->hwm.hwmFanControl[i].MedTemp_reg08;
-    if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 0)) {
-      dwValue = dwValue << 8;
-    } else {
-      dwValue = ((dwValue * 100 + pConfig->hwm.hwmTempPar[tempChannel].Ct ) * 100 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At) >> 3;
-    }
-    pConfig->hwm.hwmFanControlCooked[i].MedTemp_reg08 = dwValue;
-    dwValue = pConfig->hwm.hwmFanControl[i].HighTemp_reg0A;
-    if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 0)) {
-      dwValue = dwValue << 8;
-    } else {
-      dwValue = ((dwValue * 100 + pConfig->hwm.hwmTempPar[tempChannel].Ct ) * 100 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At) >> 3;
-    }
-    pConfig->hwm.hwmFanControlCooked[i].HighTemp_reg0A = dwValue;
-  }
-}
-
-/**
- * hwmSetRegister - Hardware Monitor Set Parameter
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmSetRegister (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 *pDbValue;
-  UINT8 i;
-  UINT8 registerN;
-  UINT8 registerPM2RegF8;
-  UINT8 registerPM2RegF9;
-
-  //UINT16 dwValue;
-//  UINT32 ddValue;
-  //Configure Fans
-  for ( i = 0; i < 5 ; i++ ) {
-    pDbValue = &(pConfig->hwm.hwmFanControlCooked[i].InputControl_reg00);
-    for ( registerN = 0; registerN < 0x0E ; registerN++ ) {
-      WritePMIO2 (i * 0x10 + registerN, AccWidthUint8, pDbValue);
-      pDbValue ++;
-    }
-  }
-  //Configure Sample Frequency Divider
-  WritePMIO2 (SB_PMIO2_REG63, AccWidthUint8, &(pConfig->hwm.fanSampleFreqDiv));
-
-  //Configure Mode
-  ReadPMIO2 (0xF8, AccWidthUint8, &registerPM2RegF8);
-  ReadPMIO2 (0xF9, AccWidthUint8, &registerPM2RegF9);
-  for ( i = 0; i < 5 ; i++ ) {
-    if (pConfig->hwm.hwmTempPar[i].Mode == BIT0) {
-      registerPM2RegF8 |= 1 << (i + 3);
-    } else if (pConfig->hwm.hwmTempPar[i].Mode == BIT1) {
-      registerPM2RegF9 |= 1 << (i + 3);
-    }
-  }
-  WritePMIO2 (0xF8, AccWidthUint8, &registerPM2RegF8);
-  WritePMIO2 (0xF9, AccWidthUint8, &registerPM2RegF9);
-}
-
-/**
- * hwmUpdateData - Hardware Monitor Update Data.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmUpdateData (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  if ( pConfig->hwm.hwmEnable ) {
-    hwmSbtsiAutoPolling (pConfig);
-    hwmGetRawData (pConfig);
-    hwmCaculate (pConfig);
-  }
-}
-
-/**
- * hwmCopyFanControl - Hardware Monitor Copy Fan Control Data.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmCopyFanControl (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 *fanControl;
-  UINT8 *fanControlCooked;
-  if ( pConfig->hwm.hwmEnable ) {
-    fanControl = & pConfig->hwm.hwmFanControl[0].InputControl_reg00;
-    fanControlCooked = & pConfig->hwm.hwmFanControlCooked[0].InputControl_reg00;
-    MemoryCopy (fanControlCooked, fanControl, (sizeof (HWM_fan_ctl_struct) * 5));
-  }
-}
-/**
- * hwmInit - Init Hardware Monitor.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  hwmInitRegister (pConfig);
-  if ( pConfig->hwm.hwmEnable ) {
-    hwmCopyFanControl (pConfig);
-    hwmProcessParameter (pConfig);
-    hwmSetRegister (pConfig);
-    hwmSbtsiAutoPolling (pConfig);
-  }
-}
-
-//#endif
diff --git a/src/vendorcode/amd/cimx/sb900/IoLib.c b/src/vendorcode/amd/cimx/sb900/IoLib.c
deleted file mode 100644
index 2a8d128330..0000000000
--- a/src/vendorcode/amd/cimx/sb900/IoLib.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-
-VOID
-ReadIO (
-  IN       UINT16 Address,
-  IN       UINT8 OpFlag,
-  IN       VOID* Value
-  )
-{
-  OpFlag = OpFlag & 0x7f;
-  switch ( OpFlag ) {
-  case AccWidthUint8:
-    *(UINT8*)Value = ReadIo8 (Address);
-    break;
-  case AccWidthUint16:
-    *(UINT16*)Value = ReadIo16 (Address);
-    break;
-  case AccWidthUint32:
-    *(UINT32*)Value = ReadIo32 (Address);
-    break;
-  default:
-    break;
-  }
-}
-
-VOID
-WriteIO (
-  IN       UINT16 Address,
-  IN       UINT8 OpFlag,
-  IN       VOID* Value
-  )
-{
-  OpFlag = OpFlag & 0x7f;
-  switch ( OpFlag ) {
-  case AccWidthUint8:
-    WriteIo8 (Address, *(UINT8*)Value);
-    break;
-  case AccWidthUint16:
-    WriteIo16 (Address, *(UINT16*)Value);
-    break;
-  case AccWidthUint32:
-    WriteIo32 (Address, *(UINT32*)Value);
-    break;
-  default:
-    break;
-  }
-}
-
-VOID
-RWIO (
-  IN       UINT16 Address,
-  IN       UINT8 OpFlag,
-  IN       UINT32 Mask,
-  IN       UINT32 Data
-  )
-{
-  UINT32 Result;
-  ReadIO (Address, OpFlag, &Result);
-  Result = (Result & Mask) | Data;
-  WriteIO (Address, OpFlag, &Result);
-}
diff --git a/src/vendorcode/amd/cimx/sb900/Legacy.c b/src/vendorcode/amd/cimx/sb900/Legacy.c
deleted file mode 100644
index 2703d6b6e2..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Legacy.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-UINT32
-GetFixUp (
-  OUT VOID
-  )
-{
-  AMD_CONFIG_PARAMS* Result;
-  Result = (AMD_CONFIG_PARAMS*) getConfigPointer ();
-  if ( Result->ImageBasePtr > 0x100000 && Result->ImageBasePtr < 0xFF000000 ) {
-    return 0;
-  }
-  return Result->ImageBasePtr;
-}
diff --git a/src/vendorcode/amd/cimx/sb900/Makefile.inc b/src/vendorcode/amd/cimx/sb900/Makefile.inc
deleted file mode 100644
index 416df7e214..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Makefile.inc
+++ /dev/null
@@ -1,60 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/cimx/sb900
-CPPFLAGS_x86_32 += -I$(src)/vendorcode/amd/cimx/sb900
-
-CPPFLAGS_x86_64 += -I$(src)/southbridge/amd/cimx/sb900
-CPPFLAGS_x86_64 += -I$(src)/vendorcode/amd/cimx/sb900
-
-romstage-y += AcpiLib.c
-romstage-y += Azalia.c
-romstage-y += Dispatcher.c
-romstage-y += EcFanc.c
-romstage-y += EcFanLib.c
-romstage-y += Gec.c
-romstage-y += Gpp.c
-romstage-y += Pmio2Lib.c
-romstage-y += Sata.c
-romstage-y += SbCmn.c
-romstage-y += SbMain.c
-romstage-y += SBPort.c
-romstage-y += MemLib.c
-romstage-y += PciLib.c
-romstage-y += IoLib.c
-romstage-y += PmioLib.c
-romstage-y += AmdLib.c
-romstage-y += SbPeLib.c
-romstage-y += AmdSbLib.c
-romstage-y += EcLib.c
-romstage-y += Ec.c
-romstage-y += Smm.c
-romstage-y += Usb.c
-romstage-y += Hwm.c
-
-ramstage-y += AcpiLib.c
-ramstage-y += Azalia.c
-ramstage-y += Dispatcher.c
-ramstage-y += EcFanc.c
-ramstage-y += EcFanLib.c
-ramstage-y += Gec.c
-ramstage-y += Gpp.c
-ramstage-y += Pmio2Lib.c
-ramstage-y += Sata.c
-ramstage-y += SbCmn.c
-ramstage-y += SbMain.c
-ramstage-y += SBPort.c
-ramstage-y += MemLib.c
-ramstage-y += PciLib.c
-ramstage-y += IoLib.c
-ramstage-y += PmioLib.c
-ramstage-y += AmdLib.c
-ramstage-y += SbPeLib.c
-ramstage-y += AmdSbLib.c
-ramstage-y += EcLib.c
-ramstage-y += Ec.c
-ramstage-y += Smm.c
-ramstage-y += Usb.c
-#ramstage-y += Legacy.c
-#ramstage-y += SbModInf.c
-ramstage-y += Debug.c
-ramstage-y += Hwm.c
diff --git a/src/vendorcode/amd/cimx/sb900/MemLib.c b/src/vendorcode/amd/cimx/sb900/MemLib.c
deleted file mode 100644
index 801f04923a..0000000000
--- a/src/vendorcode/amd/cimx/sb900/MemLib.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-VOID
-ReadMEM (
-  IN       UINT32 Address,
-  IN       UINT8 OpFlag,
-  IN       VOID* Value
-  )
-{
-  OpFlag = OpFlag & 0x7f;
-  switch ( OpFlag ) {
-  case AccWidthUint8:
-    *((UINT8*)Value) = *((UINT8*) ((UINTN)Address));
-    break;
-  case AccWidthUint16:
-    *((UINT16*)Value) = *((UINT16*) ((UINTN)Address));
-    break;
-  case AccWidthUint32:
-    *((UINT32*)Value) = *((UINT32*) ((UINTN)Address));
-    break;
-  default:
-    break;
-  }
-}
-
-VOID
-WriteMEM (
-  IN       UINT32 Address,
-  IN       UINT8 OpFlag,
-  IN       VOID* Value
-  )
-{
-  OpFlag = OpFlag & 0x7f;
-  switch ( OpFlag ) {
-  case AccWidthUint8 :
-    *((UINT8*) ((UINTN)Address)) = *((UINT8*)Value);
-    break;
-  case AccWidthUint16:
-    *((UINT16*) ((UINTN)Address)) = *((UINT16*)Value);
-    break;
-  case AccWidthUint32:
-    *((UINT32*) ((UINTN)Address)) = *((UINT32*)Value);
-    break;
-  default:
-    break;
-  }
-}
-
-VOID
-RWMEM (
-  IN       UINT32 Address,
-  IN       UINT8 OpFlag,
-  IN       UINT32 Mask,
-  IN       UINT32 Data
-  )
-{
-  UINT32 Result;
-  ReadMEM (Address, OpFlag, &Result);
-  Result = (Result & Mask) | Data;
-  WriteMEM (Address, OpFlag, &Result);
-}
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/OEM.h b/src/vendorcode/amd/cimx/sb900/OEM.h
deleted file mode 100644
index 8c9b9a6b51..0000000000
--- a/src/vendorcode/amd/cimx/sb900/OEM.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#ifndef BIOS_SIZE
-  #define BIOS_SIZE                      0x04   //04 - 1MB
-#endif
-#ifndef LEGACY_FREE
-	#define LEGACY_FREE                    0x00
-#endif
-#define ACPI_SLEEP_TRAP                0x01
-//#define SPREAD_SPECTRUM_EPROM_LOAD     0x01
-
-/**
- * Module Specific Defines for platform BIOS
- *
- */
-
-/**
- * PCIEX_BASE_ADDRESS - Define PCIE base address
- *
- * @param[Option]     MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
- */
-#ifdef  MOVE_PCIEBAR_TO_F0000000
-  #define PCIEX_BASE_ADDRESS           0xF7000000
-#else
-  #define PCIEX_BASE_ADDRESS           0xE0000000
-#endif
-
-/**
- * SMBUS0_BASE_ADDRESS - Smbus base address
- *
- */
-#ifndef SMBUS0_BASE_ADDRESS
-  #define SMBUS0_BASE_ADDRESS          0xB00
-#endif
-
-/**
- * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address
- *
- */
-#ifndef SMBUS1_BASE_ADDRESS
-  #define SMBUS1_BASE_ADDRESS          0xB20
-#endif
-
-/**
- * SIO_PME_BASE_ADDRESS - Super IO PME base address
- *
- */
-#ifndef SIO_PME_BASE_ADDRESS
-  #define SIO_PME_BASE_ADDRESS         0xE00
-#endif
-
-/**
- * SPI_BASE_ADDRESS - SPI controller (ROM) base address
- *
- */
-#ifndef SPI_BASE_ADDRESS
-  #define SPI_BASE_ADDRESS             0xFEC10000
-#endif
-
-/**
- * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address
- *
- */
-#ifndef WATCHDOG_TIMER_BASE_ADDRESS
-  #define WATCHDOG_TIMER_BASE_ADDRESS  0xFEC000F0        // Watchdog Timer Base Address
-#endif
-
-/**
- * HPET_BASE_ADDRESS - HPET base address
- *
- */
-#ifndef HPET_BASE_ADDRESS
-  #define HPET_BASE_ADDRESS            0xFED00000        // HPET Base address
-#endif
-
-/**
- * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address
- *
- */
-#ifdef ALT_ADDR_400
-  #define ACPI_BLK_BASE                0x400
-#else
-  #define ACPI_BLK_BASE                0x800
-#endif
-
-#define PM1_STATUS_OFFSET              0x00
-#define PM1_ENABLE_OFFSET              0x02
-#define PM1_CONTROL_OFFSET             0x04
-#define PM_TIMER_OFFSET                0x08
-#define CPU_CONTROL_OFFSET             0x10
-#define EVENT_STATUS_OFFSET            0x20
-#define EVENT_ENABLE_OFFSET            0x24
-
-/**
- * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
- *
- */
-#define PM1_EVT_BLK_ADDRESS           ACPI_BLK_BASE + PM1_STATUS_OFFSET     // AcpiPm1EvtBlkAddr
-
-/**
- * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
- *
- */
-#define PM1_CNT_BLK_ADDRESS           ACPI_BLK_BASE + PM1_CONTROL_OFFSET    // AcpiPm1CntBlkAddr
-
-/**
- * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
- *
- */
-#define PM1_TMR_BLK_ADDRESS           ACPI_BLK_BASE + PM_TIMER_OFFSET       // AcpiPmTmrBlkAddr
-
-/**
- * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
- *
- */
-#define CPU_CNT_BLK_ADDRESS           ACPI_BLK_BASE + CPU_CONTROL_OFFSET    // CpuControlBlkAddr
-
-/**
- * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
- *
- */
-#define GPE0_BLK_ADDRESS              ACPI_BLK_BASE + EVENT_STATUS_OFFSET   // AcpiGpe0BlkAddr
-
-/**
- * SMI_CMD_PORT - ACPI SMI Command block base address
- *
- */
-#define SMI_CMD_PORT                  0xB0              // SmiCmdPortAddr
-
-/**
- * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
- *
- */
-#define ACPI_PMA_CNT_BLK_ADDRESS      0xFE00            // AcpiPmaCntBlkAddr
-
-/**
- * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
- *    Define value for SSID while SATA controller set to IDE mode.
- */
-#define SATA_IDE_MODE_SSID           0x78001022
-/**
- * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
- *    Define value for SSID while SATA controller set to RAID mode.
- */
-#define SATA_RAID_MODE_SSID          0x78021022
-
-/**
- * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
- *    Define value for SSID while SATA controller set to RAID5 mode.
- */
-#define SATA_RAID5_MODE_SSID         0x78031022
-
-/**
- * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
- *    Define value for SSID while SATA controller set to AHCI mode.
- */
-#define SATA_AHCI_SSID               0x78011022
-
-/**
- * OHCI_SSID - All SB OHCI controllers SSID value.
- *
- */
-#define OHCI_SSID                    0x78071022
-
-/**
- * EHCI_SSID - All SB EHCI controllers SSID value.
- *
- */
-#define EHCI_SSID                    0x78081022
-
-/**
- * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
- *
- */
-#define OHCI4_SSID                   0x78091022
-
-/**
- * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
- *
- */
-#define SMBUS_SSID                   0x780B1022
-
-/**
- * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
- *
- */
-#define IDE_SSID                     0x780C1022
-
-/**
- * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
- *
- */
-#define AZALIA_SSID                  0x780D1022
-
-/**
- * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
- *
- */
-#define LPC_SSID                     0x780E1022
-
-/**
- * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
- *
- */
-#define PCIB_SSID                    0x780F1022
-
diff --git a/src/vendorcode/amd/cimx/sb900/PciLib.c b/src/vendorcode/amd/cimx/sb900/PciLib.c
deleted file mode 100644
index e95c2084aa..0000000000
--- a/src/vendorcode/amd/cimx/sb900/PciLib.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-VOID
-ReadPCI (
-  IN       UINT32 Address,
-  IN       UINT8 OpFlag,
-  IN       VOID* Value
-  )
-{
-  OpFlag = OpFlag & 0x7f;
-
-  if ( (UINT16)Address < 0xff ) {
-    //Normal Config Access
-    UINT32 AddrCf8;
-    AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
-    WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
-    ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
-  }
-}
-
-VOID
-WritePCI (
-  IN       UINT32 Address,
-  IN       UINT8 OpFlag,
-  IN       VOID* Value
-  )
-{
-  OpFlag = OpFlag & 0x7f;
-  if ( (UINT16)Address < 0xff ) {
-    //Normal Config Access
-    UINT32 AddrCf8;
-    AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
-    WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
-    WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
-  }
-}
-
-VOID
-RWPCI (
-  IN       UINT32 Address,
-  IN       UINT8 OpFlag,
-  IN       UINT32 Mask,
-  IN       UINT32 Data
-  )
-{
-  UINT32 Result;
-  Result = 0;
-  OpFlag = OpFlag & 0x7f;
-  ReadPCI (Address, OpFlag, &Result);
-  Result = (Result & Mask) | Data;
-  WritePCI (Address, OpFlag, &Result);
-}
diff --git a/src/vendorcode/amd/cimx/sb900/Pmio2Lib.c b/src/vendorcode/amd/cimx/sb900/Pmio2Lib.c
deleted file mode 100644
index 1c8f8fdd34..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Pmio2Lib.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
- * @file
- *
- * Southbridge PMIO2 access common routine
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read PMIO2
- *
- *
- *
- * @param[in] Address  - PMIO2 Offset value
- * @param[in] OpFlag   - Access sizes
- * @param[in] Value    - Read Data Buffer
- *
- */
-VOID
-ReadPMIO2 (
-  IN       UINT8 Address,
-  IN       UINT8 OpFlag,
-  IN       VOID* Value
-  )
-{
-  UINT8 i;
-  OpFlag = OpFlag & 0x7f;
-
-  if ( OpFlag == 0x02 ) {
-    OpFlag = 0x03;
-  }
-  for ( i = 0; i <= OpFlag; i++ ) {
-    WriteIO (0xCD0, AccWidthUint8, &Address);                   // SB_IOMAP_REGCD0
-    Address++;
-    ReadIO (0xCD1, AccWidthUint8, (UINT8 *) Value + i);         // SB_IOMAP_REGCD1
-  }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PMIO 2
- *
- *
- *
- * @param[in] Address  - PMIO2 Offset value
- * @param[in] OpFlag   - Access sizes
- * @param[in] Value    - Write Data Buffer
- *
- */
-VOID
-WritePMIO2 (
-  IN       UINT8 Address,
-  IN       UINT8 OpFlag,
-  IN       VOID* Value
-  )
-{
-  UINT8 i;
-  OpFlag = OpFlag & 0x7f;
-
-  if ( OpFlag == 0x02 ) {
-    OpFlag = 0x03;
-  }
-  for ( i = 0; i <= OpFlag; i++ ) {
-    WriteIO (0xCD0, AccWidthUint8, &Address);                   // SB_IOMAP_REGCD0
-    Address++;
-    WriteIO (0xCD1, AccWidthUint8, (UINT8 *)Value + i);            // SB_IOMAP_REGCD1
-  }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * RWPMIO2 - Read/Write PMIO2
- *
- *
- *
- * @param[in] Address    - PMIO2 Offset value
- * @param[in] OpFlag     - Access sizes
- * @param[in] AndMask    - Data And Mask 32 bits
- * @param[in] OrMask     - Data OR Mask 32 bits
- *
- */
-VOID
-RWPMIO2 (
-  IN       UINT8 Address,
-  IN       UINT8  OpFlag,
-  IN       UINT32 AndMask,
-  IN       UINT32 OrMask
-  )
-{
-  UINT32 Result;
-  OpFlag = OpFlag & 0x7f;
-  ReadPMIO2 (Address, OpFlag, &Result);
-  Result = (Result & AndMask) | OrMask;
-  WritePMIO2 (Address, OpFlag, &Result);
-}
diff --git a/src/vendorcode/amd/cimx/sb900/PmioLib.c b/src/vendorcode/amd/cimx/sb900/PmioLib.c
deleted file mode 100644
index fdd15a3a7c..0000000000
--- a/src/vendorcode/amd/cimx/sb900/PmioLib.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/**
- * @file
- *
- * Southbridge PMIO access common routine
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read PMIO
- *
- *
- *
- * @param[in] Address  - PMIO Offset value
- * @param[in] OpFlag   - Access sizes
- * @param[in] Value    - Read Data Buffer
- *
- */
-VOID
-ReadPMIO (
-  IN       UINT8 Address,
-  IN       UINT8 OpFlag,
-  IN       VOID* Value
-  )
-{
-  UINT8 i;
-  OpFlag = OpFlag & 0x7f;
-
-  if ( OpFlag == 0x02 ) {
-    OpFlag = 0x03;
-  }
-  for ( i = 0; i <= OpFlag; i++ ) {
-    WriteIO (0xCD6, AccWidthUint8, &Address);                   // SB_IOMAP_REGCD6
-    Address++;
-    ReadIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i);          // SB_IOMAP_REGCD7
-  }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PMIO
- *
- *
- *
- * @param[in] Address  - PMIO Offset value
- * @param[in] OpFlag   - Access sizes
- * @param[in] Value    - Write Data Buffer
- *
- */
-VOID
-WritePMIO (
-  IN       UINT8 Address,
-  IN       UINT8 OpFlag,
-  IN       VOID* Value
-  )
-{
-  UINT8 i;
-  OpFlag = OpFlag & 0x7f;
-
-  if ( OpFlag == 0x02 ) {
-    OpFlag = 0x03;
-  }
-  for ( i = 0; i <= OpFlag; i++ ) {
-    WriteIO (0xCD6, AccWidthUint8, &Address);                   // SB_IOMAP_REGCD6
-    Address++;
-    WriteIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i);         // SB_IOMAP_REGCD7
-  }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * RWPMIO - Read/Write PMIO
- *
- *
- *
- * @param[in] Address    - PMIO Offset value
- * @param[in] OpFlag     - Access sizes
- * @param[in] AndMask    - Data And Mask 32 bits
- * @param[in] OrMask     - Data OR Mask 32 bits
- *
- */
-VOID
-RWPMIO (
-  IN       UINT8 Address,
-  IN       UINT8   OpFlag,
-  IN       UINT32 AndMask,
-  IN       UINT32 OrMask
-  )
-{
-  UINT32 Result;
-  OpFlag = OpFlag & 0x7f;
-  ReadPMIO (Address, OpFlag, &Result);
-  Result = (Result & AndMask) | OrMask;
-  WritePMIO (Address, OpFlag, &Result);
-}
diff --git a/src/vendorcode/amd/cimx/sb900/SBPort.c b/src/vendorcode/amd/cimx/sb900/SBPort.c
deleted file mode 100644
index 75df24655c..0000000000
--- a/src/vendorcode/amd/cimx/sb900/SBPort.c
+++ /dev/null
@@ -1,738 +0,0 @@
-
-/**
- * @file
- *
- * Southbridge Init during POWER-ON
- *
- * Prepare Southbridge environment during power on stage.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-#include "Hudson-2.h"
-
-/**
- * sbPorInitPciTable - PCI device registers initial during the power on stage.
- *
- *
- *
- *
- */
-REG8MASK sbPorInitPciTable[] =
-{
-  // SATA device
-  {0x00, SATA_BUS_DEV_FUN, 0},
-  {SB_SATA_REG84 + 3, ~BIT2, 0},
-  {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
-  {0xFF, 0xFF, 0xFF},
-  // LPC Device (Bus 0, Dev 20, Func 3)
-  {0x00, LPC_BUS_DEV_FUN, 0},
-  {SB_LPC_REG44, 0xFF, BIT6 + BIT7}, //Enable COM1 and COM2
-  {SB_LPC_REG47, 0xFF, BIT5},
-  {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
-  {SB_LPC_REG7C, 0x00, BIT0 + BIT2},
-  {SB_LPC_REG78, 0xF0, BIT2 + BIT3},     // Enable LDRQ pin
-  {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
-  // A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
-  // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
-  {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
-  {SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
-  {SB_LPC_REGA4, ~ BIT0, BIT0}, //[BUG Fix] Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined
-  {0xFF, 0xFF, 0xFF},
-  // P2P Bridge (Bus 0, Dev 20, Func 4)
-  {0x00, PCIB_BUS_DEV_FUN, 0},
-  {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
-  // ENH230012: Disable P2P bridge decoder for IO address 0x1000-0x1FFF in SBPOR
-  // ENH260809: Add PCI port 80 support in Hudson-2/3
-#ifdef SB_PCIB_PORT_80_SUPPORT
-  {SB_PCIB_REG1C, 0x00, 0xF0},
-  {SB_PCIB_REG1D, 0x00, 0x00},
-  {SB_PCIB_REG04, 0x00, 0x21},
-#endif
-  {SB_PCIB_REG40, 0xDF, 0x20},
-  {SB_PCIB_REG50, 0x02, 0x01},
-  {0xFF, 0xFF, 0xFF},
-};
-
-/**
- * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
- *
- *
- *
- *
- */
-AcpiRegWrite sbPmioPorInitTable[] =
-{
-  {00, 00, 0xB0, 0xAC}, // Signature
-  {MISC_BASE >> 8,  SB_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12]
-  //RPR 8.9 USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock.
-  {MISC_BASE >> 8,  SB_MISC_REG40, 0xEF, 0x00},
-//  {MISC_BASE >> 8,  0x24 + 2, 0xFF, 0x20}, Testing CPU clk strength
-  {PMIO_BASE >> 8,  SB_PMIOA_REG5D, 0x00, BIT0},
-  {PMIO_BASE >> 8,  SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
-  {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG28, 0xFF, BIT0 + BIT2},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG44 + 3, 0x67, BIT7 + BIT3}, // 2.5 Enable Boot Timer
-  {PMIO_BASE >> 8,  SB_PMIOA_REG48, 0xFF, BIT0},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG00, 0xFF, 0x0E},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG00 + 2, 0xFF, 0x40},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG00 + 3, 0xFF, 0x08},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
-  {PMIO_BASE >> 8,  SB_PMIOA_REGEC, 0xFD, BIT1},
-  //{PMIO_BASE >> 8,  SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG08 + 1, 0xFF, BIT0},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG04 + 3, 0xFD, BIT1},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
-  {PMIO_BASE >> 8,  SB_PMIOA_REGF0, ~BIT2, 0x00},
-  // RPR GEC I/O Termination Setting
-  // PM_Reg 0xF6 = Power-on default setting
-  // PM_Reg 0xF7 = Power-on default setting
-  // PM_Reg 0xF8 = 0x6C
-  // PM_Reg 0xF9 = 0x21
-  // PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS
-  {PMIO_BASE >> 8, SB_PMIOA_REGF8,     0x00, 0x6C},
-  {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x07},
-  {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
-  // PRP GEC -end
-  {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xee, 0x04},      // Release NB_PCIE_RST
-  {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
-
-  {PMIO_BASE >> 8,  SB_PMIOA_REGBE, 0xDF, BIT5},
-
-  //OBS200280
-  //{PMIO_BASE >> 8,  SB_PMIOA_REGBE, 0xFF, BIT1},
-
-
-  {0xFF, 0xFF, 0xFF, 0xFF},
-};
-
-/**
- * sbPowerOnInit - Config Southbridge during power on stage.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbPowerOnInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8   dbPortStatus;
-  //UINT8   dbSysConfig;
-  UINT32  abValue;
-  UINT32  abValue2;
-  UINT8   dbValue;
-  UINT8   dbEfuse;
-  UINT32   dbSpiMode;
-  UINT16  dwAsfPort;
-  UINT16  smbusBase;
-  UINT8   cimSataMode;
-//  UINT8   cimSpiFastReadEnable;
-//  UINT8   cimSpiFastReadSpeed;
-  UINT8   cimSataInternal100Spread;
-  UINT8   indexValue;
-  UINT32  ddValue;
-  UINT8  SataPortNum;
-  UINT8     XhciEfuse;
-  XhciEfuse = XHCI_EFUSE_LOCATION;
-
-  cimSataMode = pConfig->SATAMODE.SataModeReg;
-//  if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) {
-//    cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
-//  } else {
-//    cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
-//  }
-//  cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
-  cimSataInternal100Spread = ( UINT8 ) pConfig->SataInternal100Spread;
-
-#if  SB_CIMx_PARAMETER == 0
-  cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
-  cimSataMode = (UINT8) ((cimSataMode & 0x0F) | cimSataClkModeDefault);
-  cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
-  cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
-  cimSataInternal100Spread = SataInternal100SpreadDefault;
-#endif
-
-  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
-
-// Hudson-2 Only Enabled (Mmio_mem_enablr)  // Default value is correct
-  RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
-
-  RWPMIO (0xD3, AccWidthUint8, ~BIT4, 0);
-  RWPMIO (0xD3, AccWidthUint8, ~BIT4, BIT4);
-
-  if ( pConfig->Cg2Pll == 1 ) {
-    TurnOffCG2 ();
-    pConfig->SATAMODE.SataMode.SataClkMode = 0x0a;
-  }
-
-  //enable CF9
-  RWPMIO (0xD2, AccWidthUint8, ~BIT6, 0);
-
-// Set A-Link bridge access address. This address is set at device 14h, function 0,
-// register 0f0h.   This is an I/O address. The I/O address must be on 16-byte boundary.
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
-  writeAlink (0x80000004, 0x04);     // RPR 4.2 Enable Hudson-2 to issue memory read/write requests in the upstream direction
-  abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29));      // RPR 4.5 Disable the credit variable in the downstream arbitration equation
-  abValue = abValue | BIT0;
-  writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
-  writeAlink (0x30, 0x10);         // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
-  writeAlink (0x34, readAlink (0x34) | BIT9);
-  rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, 0x00);
-
-  // Enable external Stickybit register reset feature
-  //writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x30);
-  //abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29));
-  //abValue |= BIT6 + BIT5;
-  //writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue);
-
-  // Configure UMI target link speed
-  dbEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
-  getEfuseStatus (&dbEfuse);
-  if ( dbEfuse & BIT0 ) {
-    pConfig->NbSbGen2 = 0;
-  }
-
-  dbEfuse = FCH_Variant_EFUSE_LOCATION;
-  getEfuseStatus (&dbEfuse);
-  if ((dbEfuse == 0x07) || (dbEfuse == 0x08)) {
-    pConfig->NbSbGen2 = 0;
-  }
-
-  if (pConfig->NbSbGen2) {
-    abValue = 2;
-    abValue2 = BIT0;
-  } else {
-    abValue = 1;
-    abValue2 = 0;
-  }
-  rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFE, abValue2);
-  rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, abValue);
-
-  if (pConfig->sdbEnable) {
-    rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT12, 0x00);
-    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 0, AccWidthUint8, 0, pConfig->Debug_Reg00);
-    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 2, AccWidthUint8, 0, pConfig->Debug_Reg02);
-    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 4, AccWidthUint8, 0, pConfig->Debug_Reg04);
-    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 1, AccWidthUint8, 0, pConfig->Debug_Reg01);
-    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 3, AccWidthUint8, 0, pConfig->Debug_Reg03);
-    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 5, AccWidthUint8, 0, pConfig->Debug_Reg05);
-  }
-
-// Set Build option into SB
-  WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
-// Enabled SMBUS0/SMBUS1 (ASF) Base Address
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus1BaseAddress) + BIT0);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), 0); //clear BIT[2:1]
-  smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
-  dbValue = 0x00;
-  WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
-
-  dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
-  getEfuseStatus (&dbEfuse);
-
-  programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
-
-  //RPR 3.4 Enabling ClkRun Function
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, ~ BIT2, BIT2);
-  //BUG265683: Mismatch clkrun enable register setting between RPR and CIMX code
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGD0, AccWidthUint8, ~ BIT2, 0);
-
-  SataPortNum = 0;
-  for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
-    SbStall (2);
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
-    SbStall (2);
-  }
-
-  dbValue = 0x0A;
-  WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
-  ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
-  dbValue &= 0xEF;
-  WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
-
-  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
-  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 0 );
-  if (pConfig->BuildParameters.SpiSpeed) {
-    RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT13 + BIT12), ((pConfig->BuildParameters.SpiSpeed - 1 ) << 12));
-  }
-  if (pConfig->BuildParameters.SpiFastSpeed) {
-    RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT15 + BIT14), ((pConfig->BuildParameters.SpiFastSpeed - 1 ) << 14));
-  }
-  //if (pConfig->BuildParameters.SpiBurstWrite) {
-  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG1C, AccWidthUint32 | S3_SAVE, ~(BIT10), ((pConfig->BuildParameters.SpiBurstWrite) << 10));
-  //}
-  dbSpiMode = pConfig->BuildParameters.SpiMode;
-  if (pConfig->BuildParameters.SpiMode) {
-    if ((dbSpiMode == SB_SPI_MODE_QUAL_114) || (dbSpiMode == SB_SPI_MODE_QUAL_112) || (dbSpiMode == SB_SPI_MODE_QUAL_144) || (dbSpiMode == SB_SPI_MODE_QUAL_122)) {
-    //  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFF0000, 0x013e);
-    //  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0x80 );
-    //  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFEFFFF, 0x10000);
-    //  SbStall (1000);
-    }
-    RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, ~( BIT18 + BIT29 + BIT30), ((pConfig->BuildParameters.SpiMode & 1) << 18) + ((pConfig->BuildParameters.SpiMode & 6) << 28));
-  }
-
-//  if ( cimSpiFastReadSpeed ) {
-//    RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
-//  }
-  //Program power on pci init table
-  programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]),
-                       ARRAY_SIZE(sbPorInitPciTable));
-
-  programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
-
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0);
-
-  if (pConfig->SATAMODE.SataModeReg == 0) {
-    pConfig->SATAMODE.SataModeReg = (pConfig->SATAMODE.SataMode.SataController << 0) \
-      + (pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt << 1) \
-      + (pConfig->SATAMODE.SataMode.SataSetMaxGen2 << 2) \
-      + (pConfig->SATAMODE.SataMode.SataIdeCombinedMode << 3) \
-      + (pConfig->SATAMODE.SataMode.SataClkMode << 4);
-  }
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0x00, pConfig->SATAMODE.SataModeReg);
-
-  if (dbEfuse & BIT0) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
-  }
-
-  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
-  if ( ((dbPortStatus & 0xF0) == 0x10) ) {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
-  }
-
-  if ( pConfig->BuildParameters.LegacyFree ) {
-    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
-  } else {
-    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
-  }
-
-  if ( cimSataInternal100Spread ) {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, 0xFF, BIT4);
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFB, 0x00);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, ~BIT4, 0x00);
-  }
-  // Toggle GEVENT4 to reset all GPP devices
-  sbGppTogglePcieReset (pConfig);
-
-  if ( cimSataInternal100Spread ) {
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFF, 0x04);
-  }
-
-  dbValue = 0x08;
-  WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
-  ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-  if ( !pConfig->BuildParameters.EcKbd ) {
-    // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
-    dbValue = dbValue | 0x0A;
-  }
-  WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-
-  dbValue = 0x09;
-  WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
-  ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-  if ( !pConfig->BuildParameters.EcKbd ) {
-    // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
-    dbValue = dbValue & 0xF9;
-  }
-  if ( pConfig->BuildParameters.LegacyFree ) {
-    // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
-    dbValue = dbValue & 0x9F;
-  }
-  // Enabled IRQ input
-  dbValue = dbValue | BIT4;
-  WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-
-  dwAsfPort = ((UINT16) pConfig->BuildParameters.Smbus1BaseAddress & 0xFFF0);
-  if ( dwAsfPort != 0 ) {
-    RWIO (dwAsfPort + 0x0E, AccWidthUint8, 0x0, 0x70);  // 0x70 will change to EQU ( Remote control address)
-  }
-
-#ifndef NO_EC_SUPPORT
-  getChipSysMode (&dbPortStatus);
-  if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
-    // EC is disabled by jumper setting or board config
-    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
-    ecPowerOnInit ( pConfig);
-    imcSleep ( pConfig);
-  }
-#endif
-
-
-  ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
-  ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
-  if ( ddValue == 0x78121022 ) {
-//
-// First Xhci controller.
-//
-    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
-    ddValue = 0;
-    indexValue = XHCI_REGISTER_BAR03;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    ddValue = (UINT32) dbValue;
-
-    indexValue = XHCI_REGISTER_BAR02;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    ddValue <<= 8;
-    ddValue |= (UINT32) dbValue;
-
-    indexValue = XHCI_REGISTER_BAR01;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    ddValue <<= 8;
-    ddValue |= (UINT32) dbValue;
-
-    indexValue = XHCI_REGISTER_BAR00;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    ddValue <<= 8;
-    ddValue |= (UINT32) dbValue;
-    WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
-
-    indexValue = XHCI_REGISTER_04H;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
-
-    indexValue = XHCI_REGISTER_0CH;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
-
-    indexValue = XHCI_REGISTER_3CH;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
-//
-// Second Xhci controller.
-//
-    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
-    ddValue = 0;
-    indexValue = XHCI1_REGISTER_BAR03;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    ddValue = (UINT32) dbValue;
-
-    indexValue = XHCI1_REGISTER_BAR02;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    ddValue <<= 8;
-    ddValue |= (UINT32) dbValue;
-
-    indexValue = XHCI1_REGISTER_BAR01;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    ddValue <<= 8;
-    ddValue |= (UINT32) dbValue;
-
-    indexValue = XHCI1_REGISTER_BAR00;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    ddValue <<= 8;
-    ddValue |= (UINT32) dbValue;
-    WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
-
-    indexValue = XHCI1_REGISTER_04H;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
-
-    indexValue = XHCI1_REGISTER_0CH;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
-
-    indexValue = XHCI1_REGISTER_3CH;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-    WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
-  }
-  // RPR 3.2 Enabling SPI ROM Prefetch
-  // Set LPC cfg 0xBA bit 8
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT8);
-  if (IsSbA12Plus ()) {
-    // Enable SPI Prefetch for USB, set LPC cfg 0xBA bit 7 to 1 for A12 and above
-    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT7);
-  }
-#ifdef XHCI_SUPPORT
-#ifdef XHCI_INIT_IN_ROM_SUPPORT
-  if ( pConfig->XhciSwitch == 1 ) {
-    if ( pConfig->S3Resume == 0 ) {
-      XhciEarlyInit ();
-    } else {
-      XhciInitIndirectReg ();
-    }
-  } else {
-    // for power saving.
-
-    // add Efuse checking for Xhci enable/disable
-    getEfuseStatus (&XhciEfuse);
-    if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
-      RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFBFF, 0x0);
-    }
-  }
-#endif
-#endif
-}
-
-#ifdef XHCI_SUPPORT
-VOID
-XhciInitIndirectReg (
-  )
-{
-  UINT32 ddDrivingStrength;
-  UINT32 port;
-  ddDrivingStrength = 0;
-  port = 0;
-#ifdef SB_USB_BATTERY_CHARGE_SUPPORT
-  RWXhciIndReg ( 0x40000018, 0xFFFFFFFF, 0x00000030);
-#endif
-//
-// RPR SuperSpeed PHY Configuration (adaptation mode setting)
-//
-  RWXhciIndReg ( SB_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021);
-  RWXhciIndReg ( SB_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021);
-//
-// RPR SuperSpeed PHY Configuration (CR phase and frequency filter settings)
-//
-  RWXhciIndReg ( SB_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A);
-  RWXhciIndReg ( SB_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A);
-
-//
-// RPR BLM Meaasge
-//
-  RWXhciIndReg ( SB_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000);
-//
-// RPR 8.13 xHCI USB 2.0 PHY Settings
-// Step 1 is done by hardware default
-// Step 2
-#ifdef USB3_EHCI_DRIVING_STRENGTH
-  for (port = 0; port < 4; port ++) {
-    ddDrivingStrength = (USB3_EHCI_DRIVING_STRENGTH >> (port * 4)) & 0xF;
-    if (ddDrivingStrength & BIT3) {
-      ddDrivingStrength &= 0x07;
-      if (port < 2) {
-        RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
-        RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
-      } else {
-        RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
-        RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
-      }
-    }
-  }
-#endif
-
-// Step 3
-  if (IsSbA11 ()) {
-    RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x00 << 8)));
-    RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x15 << 8)));
-  } else {
-    RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)));
-    RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)));
-  }
-}
-
-VOID
-XhciEarlyInit (
-  )
-{
-  UINT16  BcdAddress;
-  UINT16  BcdSize;
-  UINT16  AcdAddress;
-  UINT16  AcdSize;
-  UINT16  FwAddress;
-  UINT16  FwSize;
-  UINTN   XhciFwStarting;
-  UINT32  SpiValidBase;
-  UINT32  RegData;
-  UINT16  i;
-
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0x00000000, 0x00400700);
-  SbStall (20);
-//
-// Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
-//
-  GetRomSigPtr (&XhciFwStarting);
-
-  if (XhciFwStarting == 0) {
-    return;
-  }
-
-  XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
-  if (IsLpcRom ()) {
-  //XHCI firmware re-load
-    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, ~BIT2, (BIT2 + BIT1 + BIT0));
-    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, 0x00000FFF, (UINT32) (XhciFwStarting));
-  }
-//
-// RPR Enable SuperSpeed receive special error case logic. 0x20 bit8
-// RPR Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
-// Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
-//
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, 0xFFFFF8FF, 0x00000700);
-//
-// RPR SuperSpeed PHY Configuration (adaptation timer setting)
-//
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
-  //RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
-
-//
-// Step 1. to enable Xhci IO and Firmware load mode
-//
-
-#ifdef XHCI_SUPPORT_ONE_CONTROLLER
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000001);
-#else
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000003);
-#endif
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xEFFFFFFF, 0x10000000);
-
-//
-// Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
-//
-
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccWidthUint32, 0x00000000, (SPI_HEAD_LENGTH << 16));
-
-  BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
-  BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccWidthUint16, 0x0000, BcdAddress);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccWidthUint16, 0x0000, BcdSize);
-
-  AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
-  AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccWidthUint16, 0x0000, AcdAddress);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccWidthUint16, 0x0000, AcdSize);
-
-  SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccWidthUint32, 0x00000000, SpiValidBase);
-
-    //
-    // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
-    //
-  for (i = 0; i < SPI_HEAD_LENGTH; i++) {
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + i));
-  }
-
-  for (i = 0; i < BcdSize; i++) {
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + i));
-  }
-
-  for (i = 0; i < AcdSize; i++) {
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + i));
-  }
-
-//
-// Step 3. to enable the instruction RAM preload functionality.
-//
-  FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
-  FwAddress += 2;
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccWidthUint16, 0x0000, FwAddress);
-
-  FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccWidthUint16, 0x0000, FwSize);
-
-    //
-    // Set the starting address offset for Instruction RAM preload.
-    //
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccWidthUint16, 0x0000, 0);
-
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, BIT29);
-
-  for (;;) {
-    ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
-    if (RegData & BIT30) break;
-  }
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, 0);
-
-//
-// Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
-//
-
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PLL_RESET, 0); //Release U3PLLreset
-  for (;;) {
-    ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
-    if (RegData & U3PLL_LOCK) break;
-  }
-
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PHY_RESET, 0); //Release U3PHY
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3CORE_RESET, 0); //Release core reset
-
-// RPR 8.8 SuperSpeed PHY Configuration, it is only for A11.
-  if (IsSbA11 ()) {
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
-  }
-
-  XhciInitIndirectReg ();
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5), 0); // Disable Device 22
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7), BIT7); // Enable 2.0 devices
-  //if (!(pConfig->S4Resume)) {
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI
-  //}
-//
-// Step 5.
-//
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18);
-}
-#endif
diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c
deleted file mode 100644
index 397ed7d0ab..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Sata.c
+++ /dev/null
@@ -1,1042 +0,0 @@
-
-/**
- * @file
- *
- * Config Southbridge SATA controller
- *
- * Init SATA features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*     * Redistributions of source code must retain the above copyright
-*       notice, this list of conditions and the following disclaimer.
-*     * Redistributions in binary form must reproduce the above copyright
-*       notice, this list of conditions and the following disclaimer in the
-*       documentation and/or other materials provided with the distribution.
-*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-*       its contributors may be used to endorse or promote products derived
-*       from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-****************************************************************************
-*/
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-
-//
-// Declaration of local functions
-//
-VOID  sataSetIrqIntResource (IN AMDSBCFG* pConfig);
-VOID  sataBar5setting (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
-#ifdef SATA_BUS_DEV_FUN_FPGA
-  VOID  sataBar5settingFpga (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
-#endif
-VOID  shutdownUnconnectedSataPortClock (IN AMDSBCFG* pConfig, IN UINT32 ddBar5);
-VOID  CaculateAhciPortNumber (IN AMDSBCFG* pConfig, IN UINT32 ddBar5);
-VOID  sataDriveDetection (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
-#ifdef SATA_BUS_DEV_FUN_FPGA
-  VOID  sataDriveDetectionFpga (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
-#endif
-VOID  sataGpioPorcedure (IN AMDSBCFG* pConfig);
-
-/**
- * sataSetIrqIntResource - Config SATA IRQ/INT# resource
- *
- *
- *   - Private function
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sataSetIrqIntResource (
-  IN       AMDSBCFG*   pConfig
-  )
-{
-  UINT8   dbValue;
-  // IRQ14/IRQ15 come from IDE or SATA
-  dbValue = 0x08;
-  WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
-  ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-  dbValue = dbValue & 0x0F;
-  if (pConfig->SataClass == 3) {
-    dbValue = dbValue | 0x50;
-  } else {
-    if (pConfig->SataIdeMode == 1) {
-      // Both IDE & SATA set to Native mode
-      dbValue = dbValue | 0xF0;
-    }
-  }
-  WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-}
-
-/**
- * sataBar5setting - Config SATA BAR5
- *
- *   - Private function
- *
- * @param[in] pConfig - Southbridge configuration structure pointer.
- * @param[in] *pBar5   - SATA BAR5 buffer.
- *
- */
-VOID
-sataBar5setting (
-  IN       AMDSBCFG*   pConfig,
-  IN       UINT32      *pBar5
-  )
-{
-  //Get BAR5 value
-  ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
-  //Assign temporary BAR if is not already assigned
-  if ( (*pBar5 == 0) || (*pBar5 == - 1) ) {
-    //assign temporary BAR5
-    if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == - 1) ) {
-      *pBar5 = 0xFEC01000;
-    } else {
-      *pBar5 = pConfig->TempMMIO;
-    }
-    WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
-  }
-  //Clear Bits 9:0
-  *pBar5 = *pBar5 & 0xFFFFFC00;
-}
-#ifdef SATA_BUS_DEV_FUN_FPGA
-VOID
-sataBar5settingFpga (
-  IN       AMDSBCFG*   pConfig,
-  IN       UINT32      *pBar5
-  )
-{
-  UINT8  dbValue;
-  //Get BAR5 value
-  ReadPCI (((SATA_BUS_DEV_FUN_FPGA << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
-  //Assign temporary BAR if is not already assigned
-  if ( (*pBar5 == 0) || (*pBar5 == - 1) ) {
-    //assign temporary BAR5
-    if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == - 1) ) {
-      *pBar5 = 0xFEC01000;
-    } else {
-      *pBar5 = pConfig->TempMMIO;
-    }
-    WritePCI (((SATA_BUS_DEV_FUN_FPGA << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
-  }
-  //Clear Bits 9:0
-  *pBar5 = *pBar5 & 0xFFFFFC00;
-  dbValue = 0x07;
-  WritePCI (((SATA_BUS_DEV_FUN_FPGA << 16) + 0x04), AccWidthUint8, &dbValue);
-  WritePCI (((PCIB_BUS_DEV_FUN << 16) + 0x04), AccWidthUint8, &dbValue);
-}
-#endif
-/**
- * shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock
- *
- *   - Private function
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- * @param[in] ddBar5 Sata BAR5 base address.
- *
- */
-VOID
-shutdownUnconnectedSataPortClock (
-  IN       AMDSBCFG* pConfig,
-  IN       UINT32 ddBar5
-  )
-{
-  UINT8  dbPortNum;
-  UINT32  ddPortSataStatus;
-  UINT8  cimSataClkAutoOff;
-
-  cimSataClkAutoOff = (UINT8) pConfig->SataClkAutoOff;
-#if  SB_CIMx_PARAMETER == 0
-  cimSataClkAutoOff = cimSataClkAutoOffDefault;
-#endif
-  if ( cimSataClkAutoOff == TRUE ) {
-    //ENH225976 Enable SATA auto clock control by default ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) {
-    for ( dbPortNum = 0; dbPortNum < 8; dbPortNum++ ) {
-      ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint32, &ddPortSataStatus);
-      // Shutdown the clock for the port and do the necessary port reporting changes.
-      // ?? Error port status should be 1 not 3
-      ddPortSataStatus &= 0x00000F0F;
-      if ( (!((ddPortSataStatus == 0x601) || (ddPortSataStatus == 0x201) || (ddPortSataStatus == 0x103))) && (! ((pConfig->SATAESPPORT.SataPortReg) & (1 << dbPortNum))) ) {
-        TRACE ((DMSG_SB_TRACE, "Shutting down clock for SATA port %X \n", dbPortNum));
-        RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, (1 << dbPortNum));
-      }
-    }     //end of for (dbPortNum=0;dbPortNum<6;dbPortNum++)
-  }  //end of SataClkAuto Off option
-}
-
-/**
- * CaculateAhciPortNumber - Caculat AHCI Port Number
- *
- *   - Private function
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- * @param[in] ddBar5 Sata BAR5 base address.
- *
- */
-VOID
-CaculateAhciPortNumber (
-  IN       AMDSBCFG* pConfig,
-  IN       UINT32 ddBar5
-  )
-{
-  UINT8  dbPortNum;
-  UINT8  dbPortSataStatus;
-  UINT8  NumOfPorts;
-  UINT8  MaxPortNum;
-  NumOfPorts = 0;
-  MaxPortNum = 4;
-  if ( (pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt) == ENABLED ) {
-    MaxPortNum = 6;
-  } else if ( (pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == ENABLED ) {
-    MaxPortNum = 8;
-  }
-  ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, &dbPortSataStatus);
-  for ( dbPortNum = 0; dbPortNum < MaxPortNum; dbPortNum++ ) {
-    if ( dbPortSataStatus & (1 << dbPortNum) ) {
-      RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(1 << dbPortNum), 00);
-    }
-  }
-  ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
-  //if all ports are in disabled state, report atleast one port
-  if ( (dbPortSataStatus & 0xFF) == 0) {
-    RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, (UINT32) ~(0xFF), 01);
-  }
-  ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
-  for (dbPortNum = 0; dbPortNum < MaxPortNum; dbPortNum ++) {
-    if (dbPortSataStatus & (1 << dbPortNum)) {
-      NumOfPorts++;
-    }
-  }
-  if ( NumOfPorts == 0) {
-    NumOfPorts = 0x01;
-  }
-  RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1);
-}
-
-/**
- * sataGpioPorcedure - Sata GPIO function Procedure
- *
- *   - Private function
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sataGpioPorcedure (
-  IN  AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddBar5;
-  UINT32  ddData;
-  UINT32  eMb;
-  UINT32  ddTempVariable;
-  UINT8  cimSataSgpio0;
-
-  ddBar5 = 0;
-  eMb = 0;
-  cimSataSgpio0 = (UINT8) pConfig->SataSgpio0;
-
-#if  SB_CIMx_PARAMETER == 0
-  cimSataSgpio0 = cimSataSgpio0Default;
-#endif
-
-  sataBar5setting (pConfig, &ddBar5);
-  ReadMEM (ddBar5 + SB_SATA_BAR5_REG1C , AccWidthUint32 | S3_SAVE, &ddData);
-  eMb = (ddBar5 + (( ddData & 0xFFFF0000) >> 14));
-  if ( eMb ) {
-    ddTempVariable = 0x03040C00;
-    WriteMEM ( ddBar5 + eMb, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-    ddTempVariable = 0x00C08240;
-    WriteMEM ( ddBar5 + eMb + 4, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-    ddTempVariable = 0x00000001;
-    WriteMEM ( ddBar5 + eMb + 8, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-    if ( cimSataSgpio0 ) {
-      ddTempVariable = 0x00000060;
-    } else {
-      ddTempVariable = 0x00000061;
-    }
-    WriteMEM ( ddBar5 + eMb + 0x0C, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-
-    RWMEM ((ddBar5 + SB_SATA_BAR5_REG20), AccWidthUint16 | S3_SAVE, ~(BIT8), BIT8);
-    do {
-      ReadMEM (ddBar5 + SB_SATA_BAR5_REG20 , AccWidthUint32 | S3_SAVE, &ddData);
-      ddData = ddData & BIT8;
-    } while ( ddData != 0 );
-
-    ddTempVariable = 0x03040F00;
-    WriteMEM ( ddBar5 + eMb, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-    ddTempVariable = 0x00008240;
-    WriteMEM ( ddBar5 + eMb + 4, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-    ddTempVariable = 0x00000002;
-    WriteMEM ( ddBar5 + eMb + 8, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-    ddTempVariable = 0x00800000;
-    WriteMEM ( ddBar5 + eMb + 0x0C, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-    ddTempVariable = 0x0F003700;
-    WriteMEM ( ddBar5 + eMb + 0x0C, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-    RWMEM ((ddBar5 + SB_SATA_BAR5_REG20), AccWidthUint16 | S3_SAVE, ~(BIT8), BIT8);
-    do {
-      ReadMEM (ddBar5 + SB_SATA_BAR5_REG20 , AccWidthUint32 | S3_SAVE, &ddData);
-      ddData = ddData & BIT8;
-    } while ( ddData != 0 );
-  }
-}
-
-
-/**
- * Table for class code of SATA Controller in different modes
- *
- *
- *
- *
- */
-UINT32 sataIfCodeTable[] =
-{
-  0x01018F40, //sata class ID of IDE
-  0x01040040, //sata class ID of RAID
-  0x01060140, //sata class ID of AHCI
-  0x01018A40, //sata class ID of Legacy IDE
-  0x01018F40, //sata class ID of IDE to AHCI mode
-};
-
-/**
- * Table for device id of SATA Controller in different modes
- *
- *
- *
- *
- */
-
-UINT16 sataDeviceIDTable[] =
-{
-  SB_SATA_DID,  //sata device ID of IDE
-  SB_SATA_RAID_DID,  //sata device ID of RAID
-  SB_SATA_AHCI_DID,  //sata class ID of AHCI
-  SB_SATA_DID,  //sata device ID of Legacy IDE
-  SB_SATA_DID,  //sata device ID of IDE->AHCI mode
-};
-
-/**
- * Table for Sata Phy Fine Setting
- *
- *
- *
- *
- */
-SATAPHYSETTING sataPhyTable[] =
-{
-  //Gen3
-  {0x0030, 0x0057A607},
-  {0x0031, 0x0057A607},
-  {0x0032, 0x0057A407},
-  {0x0033, 0x0057A407},
-  {0x0034, 0x0057A607},
-  {0x0035, 0x0057A607},
-  {0x0036, 0x0057A403},
-  {0x0037, 0x0057A403},
-
-  //Gen2
-  {0x0120, 0x00071302},
-
-  //Gen1
-  {0x0110, 0x00174101}
-};
-
-/**
- * sataInitBeforePciEnum - Config SATA controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sataInitBeforePciEnum (
-  IN       AMDSBCFG*   pConfig
-  )
-{
-  UINT32  ddTempVar;
-  UINT32  ddValue;
-  UINT32  *tempptr;
-  UINT16  *pDeviceIdptr;
-  UINT32  dwDeviceId;
-  UINT8   dbValue;
-  UINT8   pValue;
-  UINT8   dbChannel;
-  UINT16    i;
-  SATAPHYSETTING  *pPhyTable;
-
-  pConfig->SATAPORTPOWER.SataPortPowerReg = \
-    + pConfig->SATAPORTPOWER.SataPortPower.PORT0 \
-    + (pConfig->SATAPORTPOWER.SataPortPower.PORT1 << 1) \
-    + (pConfig->SATAPORTPOWER.SataPortPower.PORT2 << 2) \
-    + (pConfig->SATAPORTPOWER.SataPortPower.PORT3 << 3) \
-    + (pConfig->SATAPORTPOWER.SataPortPower.PORT4 << 4) \
-    + (pConfig->SATAPORTPOWER.SataPortPower.PORT5 << 5) \
-    + (pConfig->SATAPORTPOWER.SataPortPower.PORT6 << 6) \
-    + (pConfig->SATAPORTPOWER.SataPortPower.PORT7 << 7);
-  // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h
-  // BIT4:disable fast boot //?
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT4);
-  // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting IDE PCI register 40h
-  RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
-  // RPR Enable IDE DMA read enhancement
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48 + 3), AccWidthUint8 | S3_SAVE, 0xff, BIT7);
-  // RPR Unused SATA Ports Disabled
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0, pConfig->SATAPORTPOWER.SataPortPowerReg);
-  dbValue = (UINT8)pConfig->SataClass;
-  if (dbValue == AHCI_MODE_7804) {
-    dbValue = AHCI_MODE;
-  }
-  if (dbValue == IDE_TO_AHCI_MODE_7804) {
-    dbValue = IDE_TO_AHCI_MODE;
-  }
-  // Disable PATA MSI
-  RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG34), AccWidthUint8 | S3_SAVE, 0x00, 0x00);
-  RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG06), AccWidthUint8 | S3_SAVE, 0xEF, 0x00);
-
-  if ( (pConfig->SataClass == 3) | (pConfig->SataClass == 0)) {
-    dbChannel = 0x00;
-    ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48 + 3), AccWidthUint8, &dbChannel);
-    dbChannel &= 0xCF;
-    if ( pConfig->SataDisUnusedIdePChannel ) {
-      dbChannel |= 0x10;
-    }
-    if ( pConfig->SataDisUnusedIdeSChannel ) {
-      dbChannel |= 0x20;
-    }
-    WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48 + 3), AccWidthUint8, &dbChannel);
-  }
-
-  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED ) {
-    ReadPCI (((IDE_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 11), AccWidthUint8, &dbChannel);
-    dbChannel &= 0xCF;
-    if ( pConfig->IdeDisUnusedIdePChannel ) {
-      dbChannel |= 0x10;
-    }
-    if ( pConfig->IdeDisUnusedIdeSChannel ) {
-      dbChannel |= 0x20;
-    }
-    WritePCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40 + 11), AccWidthUint8, &dbChannel);
-  }
-  // Get the appropriate class code from the table and write it to PCI register 08h-0Bh
-  // Set the appropriate SATA class based on the input parameters
-  // SATA IDE Controller Class ID & SSID
-  tempptr = (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]);
-  if ( (pConfig->SataIdeMode == 1) && (pConfig->SataClass != 3) ) {
-    ddValue = tempptr[0];
-    // Write the class code to IDE PCI register 08h-0Bh
-    RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
-  }
-  ddValue = tempptr[dbValue];
-  // Write the class code to SATA PCI register 08h-0Bh
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
-  if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
-    //Set PATA controller to native mode
-    RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
-  }
-  if (pConfig->BuildParameters.IdeSsid != 0 ) {
-    RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);
-  }
-  // SATA Controller Class ID & SSID
-  pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
-  ddTempVar = pConfig->BuildParameters.SataIDESsid;
-  dwDeviceId = pDeviceIdptr[dbValue];
-  if ( pConfig->SataClass == RAID_MODE) {
-    ddTempVar = pConfig->BuildParameters.SataRAID5Ssid;
-    dwDeviceId = SB_SATA_RAID5_DID;
-    pValue = SATA_EFUSE_LOCATION;
-    getEfuseStatus (&pValue);
-    if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) {
-      dwDeviceId = SB_SATA_RAID_DID;
-      ddTempVar = pConfig->BuildParameters.SataRAIDSsid;
-    }
-  }
-  if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) ||
-    ((pConfig->SataClass) == AHCI_MODE_7804) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_7804) ) {
-    ddTempVar = pConfig->BuildParameters.SataAHCISsid;
-  }
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
-  RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
-
-  // SATA IRQ Resource
-  sataSetIrqIntResource (pConfig);
-
-  // RPR 9.5 SATA PHY Programming Sequence
-  pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]);
-  for (i = 0; i < ARRAY_SIZE(sataPhyTable); i++) {
-    RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80, AccWidthUint16 | S3_SAVE, 0x00, pPhyTable->wPhyCoreControl);
-    RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune);
-    ++pPhyTable;
-  }
-  RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80, AccWidthUint16 | S3_SAVE, 0x00, 0x110);
-  RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG9C, AccWidthUint32 | S3_SAVE, (UINT32) (~(0x7 << 4)), (UINT32) (0x2 << 4));
-  RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80, AccWidthUint16 | S3_SAVE, 0x00, 0x10);
-
-  RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
-  // Disable write access to PCI header
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
-  if ( IsSbA12Plus () ) {
-    //SATA PCI Config 0x4C[31:26] program 111111b (six 1's)
-    //SATA PCI Config 0x48[11] program 1
-    //SATA PCI Config 0x84[31] program 0
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG4C), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x3f << 26)), (UINT32) (0x3f << 26));
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11));
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31));
-  }
-
-  //SATA PCI config register 0x4C [20] =1
-  //SATA PCI config register 0x4C [21] =1
-  //SATA PCI config register 0x4C [18] =1
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG4C), AccWidthUint32 | S3_SAVE, ~ (BIT18 + BIT20 + BIT21), (BIT18 + BIT20 + BIT21));
-}
-
-/**
- * sataInitAfterPciEnum - Config SATA controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sataInitAfterPciEnum (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddAndMask;
-  UINT32  ddOrMask;
-  UINT32  ddBar5;
-  UINT8  dbVar;
-  UINT8  dbPortNum;
-  UINT8  dbEfuse;
-  UINT8  dbPortMode;
-  UINT16  SataPortMode;
-  UINT8  cimSataAggrLinkPmCap;
-  UINT8  cimSataPortMultCap;
-  UINT8  cimSataPscCap;
-  UINT8  cimSataSscCap;
-  UINT8  cimSataFisBasedSwitching;
-  UINT8  cimSataCccSupport;
-  UINT8  cimSataMsiCapability;
-  UINT8  cimSataTargetSupport8Device;
-  UINT8  cimSataDisableGenericMode;
-  UINT8  cimSataAhciEnclosureManagement;
-  UINT8  cimSataSgpio0;
-  UINT8  cimSataSgpio1;
-  UINT8  cimSataHotRemovelEnh;
-  UINT8  cimSataPhyPllShutDown;
-  UINT8  dbCccInt;
-
-  cimSataAggrLinkPmCap = (UINT8) pConfig->SataAggrLinkPmCap;
-  cimSataPortMultCap = (UINT8) pConfig->SataPortMultCap;
-  cimSataPscCap = (UINT8) pConfig->SataPscCap;
-  cimSataSscCap = (UINT8) pConfig->SataSscCap;
-  cimSataFisBasedSwitching = (UINT8) pConfig->SataFisBasedSwitching;
-  cimSataCccSupport = (UINT8) pConfig->SataCccSupport;
-  cimSataMsiCapability = (UINT8) pConfig->SataMsiCapability;
-  cimSataTargetSupport8Device = (UINT8) pConfig->SataTargetSupport8Device;
-  cimSataDisableGenericMode = (UINT8) pConfig->SataDisableGenericMode;
-  cimSataAhciEnclosureManagement = (UINT8) pConfig->SataAhciEnclosureManagement;
-  cimSataSgpio0 = (UINT8) pConfig->SataSgpio0;
-  cimSataSgpio1 = (UINT8) pConfig->SataSgpio1;
-  cimSataHotRemovelEnh = (UINT8) pConfig->SataHotRemoveEnh;
-  cimSataPhyPllShutDown = (UINT8) pConfig->SataPhyPllShutDown;
-
-#if  SB_CIMx_PARAMETER == 0
-  cimSataAggrLinkPmCap = cimSataAggrLinkPmCapDefault;
-  cimSataPortMultCap = cimSataPortMultCapDefault;
-  cimSataPscCap = cimSataPscCapDefault;
-  cimSataSscCap = cimSataSscCapDefault;
-  cimSataFisBasedSwitching = cimSataFisBasedSwitchingDefault;
-  cimSataCccSupport = cimSataCccSupportDefault;
-  cimSataMsiCapability = cimSataMsiCapabilityDefault;
-  cimSataTargetSupport8Device = cimSataTargetSupport8DeviceDefault;
-  cimSataDisableGenericMode = cimSataDisableGenericModeDefault;
-  cimSataAhciEnclosureManagement = cimSataAhciEnclosureManagementDefault;
-  cimSataSgpio0 = cimSataSgpio0Default;
-  cimSataSgpio1 = cimSataSgpio1Default;
-  cimSataHotRemovelEnh = cimSataHotRemoveEnhDefault;
-  cimSataPhyPllShutDown = cimSataPhyPllShutDownDefault;
-#endif
-
-  ddAndMask = 0;
-  ddOrMask = 0;
-  ddBar5 = 0;
-  if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {
-    return;   //return if SATA controller is disabled.
-  }
-
-  //Enable write access to pci header, pm capabilities
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
-
-  sataBar5setting (pConfig, &ddBar5);
-
-  ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);   //memory and io access enable
-  dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
-  getEfuseStatus (&dbEfuse);
-
-  if ( !cimSataPortMultCap ) {
-    ddAndMask |= BIT12;
-  }
-  if ( cimSataAggrLinkPmCap ) {
-    ddOrMask |= BIT11;
-  } else {
-    ddAndMask |= BIT11;
-  }
-  if ( cimSataPscCap ) {
-    ddOrMask |= BIT1;
-  } else {
-    ddAndMask |= BIT1;
-  }
-  if ( cimSataSscCap ) {
-    ddOrMask |= BIT26;
-  } else {
-    ddAndMask |= BIT26;
-  }
-  if ( cimSataFisBasedSwitching ) {
-    if (dbEfuse & BIT1) {
-      ddAndMask |= BIT10;
-    } else {
-      ddOrMask |= BIT10;
-    }
-  } else {
-    ddAndMask |= BIT10;
-  }
-  // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
-  if ( cimSataCccSupport ) {
-    ddOrMask |= BIT19;
-  } else {
-    ddAndMask |= BIT19;
-  }
-  if ( cimSataAhciEnclosureManagement ) {
-    ddOrMask |= BIT27;
-  } else {
-    ddAndMask |= BIT27;
-  }
-  RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask);
-
-
-  // SATA ESP port setting
-  // These config bits are set for SATA driver to identify which ports are external SATA ports and need to
-  // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
-  // not enable power management (HIPM & DIPM) for these ports.
-  pConfig->SATAESPPORT.SataPortReg = \
-    + pConfig->SATAESPPORT.SataEspPort.PORT0 \
-    + (pConfig->SATAESPPORT.SataEspPort.PORT1 << 1) \
-    + (pConfig->SATAESPPORT.SataEspPort.PORT2 << 2) \
-    + (pConfig->SATAESPPORT.SataEspPort.PORT3 << 3) \
-    + (pConfig->SATAESPPORT.SataEspPort.PORT4 << 4) \
-    + (pConfig->SATAESPPORT.SataEspPort.PORT5 << 5) \
-    + (pConfig->SATAESPPORT.SataEspPort.PORT6 << 6) \
-    + (pConfig->SATAESPPORT.SataEspPort.PORT7 << 7);
-  if ( pConfig->SATAESPPORT.SataPortReg != 0 ) {
-    RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(pConfig->SATAESPPORT.SataPortReg), 0);
-    RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, 0xFF00FF00, (pConfig->SATAESPPORT.SataPortReg << 16));
-    // RPR 8.7 External SATA Port Indication Registers
-    // If any of the ports was programmed as an external port, HCAP.SXS should also be set
-    RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), BIT20);
-  } else {
-    // RPR 8.7 External SATA Port Indication Registers
-    // If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port)
-    RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, 0xFF00FF00, 0x00);
-    RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), 0x00);
-  }
-
-  if ( cimSataFisBasedSwitching ) {
-    if (dbEfuse & BIT1) {
-      RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, 0x00FFFFFF, 0x00);
-    } else {
-      RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, 0x00FFFFFF, 0xFF000000);
-    }
-  } else {
-    RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, 0x00FFFFFF, 0x00);
-  }
-
-  //SB02712 Turn off MSI for SATA IDE mode.
-  if ((pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE)) {
-    cimSataMsiCapability = 0;
-  }
-  //Enabled SATA MSI capability
-  // RPR 8.11 SATA MSI and D3 Power State Capability
-  if (IsSbA12Plus ()) {
-    if ( cimSataMsiCapability ) {
-      RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x50);
-    } else {
-      RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70);
-    }
-  } else {
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70);
-  }
-
-  if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
-    // RAID or AHCI
-    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {
-      // IDE2 Controller is enabled
-      if ((pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt) == ENABLED) {
-        // 6 AHCI mode
-        RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0x00, 0x3F);
-        RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
-        RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
-        RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint8, 0x07, 0x30);
-      } else {
-        RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0x00, 0x0F);
-        if ( pConfig->SataCccSupport ) {
-          RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
-        } else {
-          RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2);
-        }
-      }
-    } else {
-      // IDE2 Controller is disabled
-      RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT1 + BIT0);
-      RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0x00, 0xFF);
-      if ( pConfig->SataCccSupport ) {
-        RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT3);
-      } else {
-        RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
-      }
-    }
-  }
-  if ( pConfig->BIOSOSHandoff == 1 ) {
-    RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, BIT0);
-  } else {
-    RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);
-  }
-  pConfig->SATAPORTMODE.SataPortMode = \
-    pConfig->SATAPORTMODE.SataPortMd.PORT0 \
-    + (pConfig->SATAPORTMODE.SataPortMd.PORT1 << 2) \
-    + (pConfig->SATAPORTMODE.SataPortMd.PORT2 << 4) \
-    + (pConfig->SATAPORTMODE.SataPortMd.PORT3 << 6) \
-    + (pConfig->SATAPORTMODE.SataPortMd.PORT4 << 8) \
-    + (pConfig->SATAPORTMODE.SataPortMd.PORT5 << 10) \
-    + (pConfig->SATAPORTMODE.SataPortMd.PORT6 << 12) \
-    + (pConfig->SATAPORTMODE.SataPortMd.PORT7 << 14);
-  SataPortMode = (UINT16)pConfig->SATAPORTMODE.SataPortMode;
-  dbPortNum = 0;
-
-  while ( dbPortNum < 8 ) {
-    dbPortMode = (UINT8) (SataPortMode & 3);
-    if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {
-      if ( dbPortMode == BIT0 ) {
-        // set GEN 1
-        RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10);
-      }
-      if ( dbPortMode == BIT1 ) {
-        // set GEN2 (default is GEN3)
-        RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x20);
-      }
-      RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
-      cimSbStall (1000);
-      RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
-    }
-    SataPortMode >>= 2;
-    dbPortNum ++;
-  }
-  SbStall (1000);
-  SataPortMode = (UINT16)pConfig->SATAPORTMODE.SataPortMode;
-  dbPortNum = 0;
-
-  while ( dbPortNum < 8 ) {
-    dbPortMode = (UINT8) (SataPortMode & 3);
-    if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {
-      RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
-    }
-    dbPortNum ++;
-    SataPortMode >>= 2;
-  }
-
-  if ( cimSataTargetSupport8Device ) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint16, ~BIT12, BIT12);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint16, ~BIT12, 0x00);
-  }
-
-  if ( cimSataDisableGenericMode ) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint16, ~BIT13, BIT13);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint16, ~BIT13, 0x00);
-  }
-  // 9.19 Optionally Disable Hot-removal Detection Enhancement
-  if ( cimSataHotRemovelEnh ) {
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80), AccWidthUint16 | S3_SAVE, ~BIT8, BIT8 );
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA8), AccWidthUint16 | S3_SAVE, ~BIT0, BIT0);
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80), AccWidthUint16 | S3_SAVE, ~BIT8, 0 );
-  }
-  if ( cimSataSgpio0 ) {
-    sataGpioPorcedure (pConfig);
-  }
-  if ( cimSataSgpio1 ) {
-    sataGpioPorcedure (pConfig);
-  }
-  if ( IsSbA11 () ) {
-    if ( cimSataPhyPllShutDown ) {
-      RWPCI (((SATA_BUS_DEV_FUN << 16) + 0x87), AccWidthUint8 | S3_SAVE, ~(BIT6 + BIT7), BIT6 + BIT7);
-    } else {
-      RWPCI (((SATA_BUS_DEV_FUN << 16) + 0x87), AccWidthUint8 | S3_SAVE, ~(BIT6 + BIT7), 0x00);
-    }
-  } else {
-    if ( cimSataPhyPllShutDown ) {
-      RWPCI (((SATA_BUS_DEV_FUN << 16) + 0x87), AccWidthUint8 | S3_SAVE, ~(BIT6), BIT6);
-    } else {
-      RWPCI (((SATA_BUS_DEV_FUN << 16) + 0x87), AccWidthUint8 | S3_SAVE, ~(BIT6), 0x00);
-    }
-  }
-  if ( IsSbA12Plus () ) {
-    //SATA PCI Config 0x4C[31:26] program 111111b (six 1's)
-    //SATA PCI Config 0x48[11] program 1
-    //SATA PCI Config 0x84[31] program 0
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG4C), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x3f << 26)), (UINT32) (0x3f << 26));
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11));
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31));
-  }
-  // RPR 9.18 CCC Interrupt
-  dbCccInt = 4;
-  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {
-    if ((pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt) == ENABLED) {
-      dbCccInt = 6;
-    }
-  } else {
-    dbCccInt = 8;
-  }
-  RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint8, 0x07, (dbCccInt << 3));
-
-  shutdownUnconnectedSataPortClock (pConfig, ddBar5);
-
-  WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
-
-  // RPR 9.13 Disable SATA FLR Capability
-  // SATA_PCI_config 0x70 [15:8] = 0x00
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG70), AccWidthUint32 | S3_SAVE, 0xFFFF00FF, 0x00);
-  //Disable write access to pci header, pm capabilities
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
-}
-
-
-/**
- * sataInitMidPost - Config SATA controller in Middle POST.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sataInitMidPost (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32   ddBar5;
-  sataBar5setting (pConfig, &ddBar5);
-  //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround.
-  if ( ! (pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE)  && ((pConfig->SataClass) != RAID_MODE) ) ) {
-    sataDriveDetection (pConfig, &ddBar5);
-  }
-#ifdef SATA_BUS_DEV_FUN_FPGA
-  sataBar5settingFpga (pConfig, &ddBar5);
-  sataDriveDetectionFpga (pConfig, &ddBar5);
-#endif
-}
-
-/**
- * sataDriveDetection - Sata drive detection
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- * @param[in] *pBar5 Sata BAR5 base address.
- *
- */
-VOID
-sataDriveDetection (
-  IN       AMDSBCFG* pConfig,
-  IN       UINT32 *pBar5
-  )
-{
-  UINT32   ddVar0;
-  UINT8   dbPortNum;
-  UINT8   dbVar0;
-  UINT16   dwIoBase;
-  UINT32   ddVar1;
-  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
-  TRACE ((DMSG_SB_TRACE, "SATA BAR5 is %X \n", *pBar5));
-  if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) {
-    for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) {
-      ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
-      if ( ( ddVar0 & 0x0F ) == 0x03 ) {
-        if ( dbPortNum & BIT0 ) {
-          //this port belongs to secondary channel
-          ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
-        } else {
-          //this port belongs to primary channel
-          ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
-        }
-        //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
-        if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
-          dwIoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (dbPortNum & BIT0) << 7)) & 0x80 )) );
-        }
-        if ( dbPortNum & BIT1 ) {
-          //this port is slave
-          dbVar0 = 0xB0;
-        } else {
-          //this port is master
-          dbVar0 = 0xA0;
-        }
-        dwIoBase &= 0xFFF8;
-        WriteIO (dwIoBase + 6, AccWidthUint8, &dbVar0);
-        //Wait in loop for 30s for the drive to become ready
-        for ( ddVar1 = 0; ddVar1 < 300000; ddVar1++ ) {
-          ReadIO (dwIoBase + 7, AccWidthUint8, &dbVar0);
-          if ( (dbVar0 & 0x88) == 0 ) {
-            break;
-          }
-          SbStall (100);
-        }
-      } //end of if ( ( ddVar0 & 0x0F ) == 0x03)
-    } //for (dbPortNum = 0; dbPortNum < 4; dbPortNum++)
-  } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE))
-}
-
-#ifdef SATA_BUS_DEV_FUN_FPGA
-VOID
-sataDriveDetectionFpga (
-  IN       AMDSBCFG* pConfig,
-  IN       UINT32 *pBar5
-  )
-{
-  UINT32   ddVar0;
-  UINT8   dbPortNum;
-  UINT8   dbVar0;
-  UINT16   dwIoBase;
-  UINT32   ddVar1;
-  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
-  TRACE ((DMSG_SB_TRACE, "SATA BAR5 is %X \n", *pBar5));
-  for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) {
-    ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
-    if ( ( ddVar0 & 0x0F ) == 0x03 ) {
-      if ( dbPortNum & BIT0 ) {
-        //this port belongs to secondary channel
-        ReadPCI (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
-      } else {
-        //this port belongs to primary channel
-        ReadPCI (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
-      }
-      //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
-      if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
-        dwIoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (dbPortNum & BIT0) << 7)) & 0x80 )) );
-      }
-      if ( dbPortNum & BIT1 ) {
-        //this port is slave
-        dbVar0 = 0xB0;
-      } else {
-        //this port is master
-        dbVar0 = 0xA0;
-      }
-      dwIoBase &= 0xFFF8;
-      WriteIO (dwIoBase + 6, AccWidthUint8, &dbVar0);
-      //Wait in loop for 30s for the drive to become ready
-      for ( ddVar1 = 0; ddVar1 < 300000; ddVar1++ ) {
-        ReadIO (dwIoBase + 7, AccWidthUint8, &dbVar0);
-        if ( (dbVar0 & 0x88) == 0 ) {
-          break;
-        }
-        SbStall (100);
-      }
-    } //end of if ( ( ddVar0 & 0x0F ) == 0x03)
-  } //for (dbPortNum = 0; dbPortNum < 4; dbPortNum++)
-}
-#endif
-
-/**
- * sataInitLatePost - Prepare SATA controller to boot to OS.
- *
- *              - Set class ID to AHCI (if set to AHCI * Mode)
- *              - Enable AHCI interrupt
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sataInitLatePost (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddBar5;
-  UINT8  dbVar;
-  UINT8  dbPortNum;
-
-  //Return immediately is sata controller is not enabled
-  if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {
-    return;
-  }
-  //Enable write access to pci header, pm capabilities
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
-
-  sataBar5setting (pConfig, &ddBar5);
-
-  ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
-  //Enable memory and io access
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);
-
-  if (( pConfig->SataClass == IDE_TO_AHCI_MODE) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_7804 )) {
-    //program the AHCI class code
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100);
-    //Set interrupt enable bit
-    RWMEM ((ddBar5 + 0x04), AccWidthUint8, (UINT32)~0, BIT1);
-    //program the correct device id for AHCI mode
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, SB_SATA_AHCI_DID);
-  }
-
-  if (( pConfig->SataClass == AHCI_MODE_7804 ) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_7804 )) {
-    //program the correct device id for AHCI 7804 mode
-    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, SB_SATA_AMDAHCI_DID);
-  }
-  // OBS236459 IDE controller not shown in device manager when Os installed on IDE mode port
-  //if ( pConfig->SataClass == IDE_TO_AHCI_MODE_7804 ) {
-    //Disable IDE2 and Enable 8 channel for IDE-AHCI mode
-    //RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, ~BIT1, BIT3);
-  //}
-
-  //Clear error status
-  RWMEM ((ddBar5 + SB_SATA_BAR5_REG130), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
-  RWMEM ((ddBar5 + SB_SATA_BAR5_REG1B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
-  RWMEM ((ddBar5 + SB_SATA_BAR5_REG230), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
-  RWMEM ((ddBar5 + SB_SATA_BAR5_REG2B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
-  RWMEM ((ddBar5 + SB_SATA_BAR5_REG330), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
-  RWMEM ((ddBar5 + SB_SATA_BAR5_REG3B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
-  RWMEM ((ddBar5 + SB_SATA_BAR5_REG430), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
-  RWMEM ((ddBar5 + SB_SATA_BAR5_REG4B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
-  CaculateAhciPortNumber (pConfig, ddBar5);
-  //Restore memory and io access bits
-  WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar );
-  //Disable write access to pci header and pm capabilities
-  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
-  for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) {
-    RWMEM ((ddBar5 + 0x110 + (dbPortNum * 0x80)), AccWidthUint32, 0xFFFFFFFF, 0x00);
-  }
-}
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h b/src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h
deleted file mode 100644
index 7c89da044e..0000000000
--- a/src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#ifndef _BIOS_RAM_USAGE_H_
-#define _BIOS_RAM_USAGE_H_
-
-#define RESTORE_MEMORY_CONTROLLER_START 0
-#define XHCI_REGISTER_BAR00           0xD0
-#define XHCI_REGISTER_BAR01           0xD1
-#define XHCI_REGISTER_BAR02           0xD2
-#define XHCI_REGISTER_BAR03           0xD3
-#define XHCI_REGISTER_04H             0xD4
-#define XHCI_REGISTER_0CH             0xD5
-#define XHCI_REGISTER_3CH             0xD6
-#define XHCI1_REGISTER_BAR00          0xE0
-#define XHCI1_REGISTER_BAR01          0xE1
-#define XHCI1_REGISTER_BAR02          0xE2
-#define XHCI1_REGISTER_BAR03          0xE3
-#define XHCI1_REGISTER_04H            0xE4
-#define XHCI1_REGISTER_0CH            0xE5
-#define XHCI1_REGISTER_3CH            0xE6
-#define RTC_WORKAROUND_DATA_START     0xF0
-#define BOOT_TIME_FLAG_SEC            0xF8
-#define BOOT_TIME_FLAG_INT19          0xFC
-
-#endif
-
diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c
deleted file mode 100644
index b1784d7ddd..0000000000
--- a/src/vendorcode/amd/cimx/sb900/SbCmn.c
+++ /dev/null
@@ -1,1545 +0,0 @@
-/**
- * @file
- *
- * Southbridge Initial routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-
-//
-// Declaration of local functions
-//
-
-VOID abcfgTbl (IN ABTBLENTRY* pABTbl);
-VOID A13ResumeResetTwoSecondRtcWakeup (void);
-
-
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- *  @page LegacyInterfaceCalls  Legacy Interface Calls
- *  <TD>@subpage SB_POWERON_INIT_Page "SB_POWERON_INIT"</TD><TD></TD>
- *  <TD>@subpage SB_BEFORE_PCI_INIT_Page "SB_BEFORE_PCI_INIT"</TD><TD></TD>
- *  <TD>@subpage SB_AFTER_PCI_INIT_Page "SB_AFTER_PCI_INIT"</TD><TD></TD>
- *  <TD>@subpage SB_LATE_POST_INIT_Page "SB_LATE_POST_INIT"</TD><TD></TD>
- *  <TD>@subpage SB_BEFORE_PCI_RESTORE_INIT_Page "SB_BEFORE_PCI_RESTORE_INIT"</TD><TD></TD>
- *  <TD>@subpage SB_AFTER_PCI_RESTORE_INIT_Page "SB_AFTER_PCI_RESTORE_INIT"</TD><TD></TD>
- *  <TD>@subpage SB_SMM_SERVICE_Page "SB_SMM_SERVICE"</TD><TD></TD>
- *  <TD>@subpage SB_SMM_ACPION_Page "SB_SMM_ACPION"</TD><TD></TD>
- *
- *  @page LegacyInterfaceCallOuts  Legacy Interface CallOuts
- *  <TD>@subpage CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
- *  <TD>@subpage CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
- *
-*/
-
-/**
- * sbEarlyPostByteInitTable - PCI device registers initial during early POST.
- *
- */
-REG8MASK sbEarlyPostByteInitTable[] =
-{
-  // SMBUS Device (Bus 0, Dev 20, Func 0)
-  {0x00, SMBUS_BUS_DEV_FUN, 0},
-  {SB_CFG_REG10, 0X00, (SBCIMx_Version & 0xFF)}, //Program the version information
-  {SB_CFG_REG11, 0X00, (SBCIMx_Version >> 8)},
-  {0xFF, 0xFF, 0xFF},
-
-  // IDE Device (Bus 0, Dev 20, Func 1)
-  {0x00, IDE_BUS_DEV_FUN, 0},
-  {SB_IDE_REG62 + 1, ~BIT0, BIT5},  // Enabling IDE Explicit Pre-Fetch  IDE PCI Config 0x62[8]=0
-  // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1
-  {0xFF, 0xFF, 0xFF},
-
-  // Azalia Device (Bus 0, Dev 20, Func 2)
-  {0x00, AZALIA_BUS_DEV_FUN, 0},
-  {SB_AZ_REG4C, ~BIT0, BIT0},
-  {0xFF, 0xFF, 0xFF},
-
-  // LPC Device (Bus 0, Dev 20, Func 3)
-  {0x00, LPC_BUS_DEV_FUN, 0},
-  {SB_LPC_REG40, ~BIT2, BIT2},                          // RPR Enabling LPC DMA Function  0x40[2]=1b 0x78[0]=0b
-  {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
-  {SB_LPC_REG78, 0xFC, 00},                             // RPR Enabling LPC DMA Function  0x40[2]=1b 0x78[0]=0b / Disables MSI capability
-  {SB_LPC_REGBB, ~BIT0, BIT0 + BIT3 + BIT4 + BIT5},     // Enabled SPI Prefetch from HOST.
-  {0xFF, 0xFF, 0xFF},
-
-  // PCIB Bridge (Bus 0, Dev 20, Func 4)
-  {0x00, PCIB_BUS_DEV_FUN, 0},
-  {SB_PCIB_REG40, 0xFF, BIT5},      // RPR PCI-bridge Subtractive Decode
-  {SB_PCIB_REG4B, 0xFF, BIT7},      //
-  {SB_PCIB_REG66, 0xFF, BIT4},      // RPR Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
-  {SB_PCIB_REG65, 0xFF, BIT7},      // RPR proper operation of CLKRUN#.
-  {SB_PCIB_REG0D, 0x00, 0x40},      // Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
-  {SB_PCIB_REG1B, 0x00, 0x40},      // of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
-  {SB_PCIB_REG66 + 1, 0xFF, BIT1},  // RPR Enable PCI bus GNT3#..
-  {0xFF, 0xFF, 0xFF},
-
-  // SATA Device (Bus 0, Dev 17, Func 0)
-  {0x00, SATA_BUS_DEV_FUN, 0},
-  {SB_SATA_REG44, 0xff, BIT0},       // RPR Enables the SATA watchdog timer register prior to the SATA BIOS post
-  {SB_SATA_REG44 + 2, 0, 0x20},      // RPR SATA PCI Watchdog timer setting
-                                     // [SB01923] Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
-  {0xFF, 0xFF, 0xFF},
-};
-
-
-/**
- * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST.
- *
- */
-AcpiRegWrite sbPmioEPostInitTable[] =
-{
-  {00, 00, 0xB0, 0xAC}, // Signature
-  // HPET workaround
-  {PMIO_BASE >> 8,  SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG54 + 2, 0x7F, BIT7},
-  {PMIO_BASE >> 8,  SB_PMIOA_REG54 + 2, 0x7F, 0x00},
-  // End of HPET workaround
-  // Enable Hudson-2 A12 ACPI bits at PMIO 0xC0 [30, 10:3]
-  // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time.
-  // UsbGoodClkDlyEn         4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time.
-  // ForceNBCPUPwr           5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood.
-  // MergeUsbPerReq          6 Set to 1 to merge usb perdical traffic into usb request as one of break event.
-  // IMCWatchDogRstEn        7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled.
-  // GeventStsFixEn          8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit.
-  // PmeTimerFixEn           9 Set to 1 to reset Pme Timer when going to sleep state.
-  // UserRst2EcEn           10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled.
-  // Smbus0ClkSEn           30 Set to 1 to enable SMBus0 controller clock stretch support.
-  {PMIO_BASE >> 8, SB_PMIOA_REGC4, ~BIT2, BIT2},
-  {PMIO_BASE >> 8, SB_PMIOA_REGC0, 0, 0xF9},
-  {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 1, 0x04, 0x03},
-  // RtcSts              19-17 RTC_STS set only in Sleep State.
-  // GppPme                 20 Set to 1 to enable PME request from SB GPP.
-  // Pcireset               22 Set to 1 to allow SW to reset PCIe.
-  {PMIO_BASE >> 8, SB_PMIOA_REGC2, 0x20, 0x58},
-  {PMIO_BASE >> 8, SB_PMIOA_REGC2 + 1, 0, 0x40},
-  {PMIO_BASE >> 8, SB_PMIOA_REGC2, ~(BIT4), BIT4},
-  {PMIO_BASE >> 8, SB_PMIOA_REGCC, 0xF8, 0x01},
-  {PMIO_BASE >> 8, SB_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
-  {PMIO_BASE >> 8, SB_PMIOA_REG74 + 3, ~BIT5, 0},
-  {PMIO_BASE >> 8, SB_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1},
-  {PMIO_BASE >> 8, SB_PMIOA_REGDE, ~BIT4, BIT4},
-  {PMIO_BASE >> 8, SB_PMIOA_REGBA, ~BIT3, BIT3},
-  {PMIO_BASE >> 8, SB_PMIOA_REGBA + 1, ~BIT6, BIT6},
-  {PMIO_BASE >> 8, SB_PMIOA_REGBC, ~BIT1, BIT1},
-  {PMIO_BASE >> 8, SB_PMIOA_REGED, ~(BIT4 + BIT0 + BIT1), 0},
-  //RPR Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01
-  {PMIO_BASE >> 8, SB_PMIOA_REGDC, 0x7C, BIT0},
-  {SMI_BASE >> 8, SB_SMI_Gevent1, 0, 1},
-  {SMI_BASE >> 8, SB_SMI_Gevent3, 0, 3},
-  {SMI_BASE >> 8, SB_SMI_Gevent4, 0, 4},
-  {SMI_BASE >> 8, SB_SMI_Gevent5, 0, 5},
-  {SMI_BASE >> 8, SB_SMI_Gevent6, 0, 6},
-  {SMI_BASE >> 8, SB_SMI_Gevent23, 0, 23},
-  {SMI_BASE >> 8, SB_SMI_xHC0Pme, 0, 11},
-  {SMI_BASE >> 8, SB_SMI_xHC1Pme, 0, 11},
-  {SMI_BASE >> 8, SB_SMI_Usbwakup0, 0, 11},
-  {SMI_BASE >> 8, SB_SMI_Usbwakup1, 0, 11},
-#ifndef USB_LOGO_SUPPORT
-  {SMI_BASE >> 8, SB_SMI_Usbwakup2, 0, 11},
-  {SMI_BASE >> 8, SB_SMI_Usbwakup3, 0, 11},
-#endif
-  {SMI_BASE >> 8, SB_SMI_IMCGevent0, 0, 12},
-  {SMI_BASE >> 8, SB_SMI_FanThGevent, 0, 13},
-  {SMI_BASE >> 8, SB_SMI_SBGppPme0, 0, 15},
-  {SMI_BASE >> 8, SB_SMI_SBGppPme1, 0, 16},
-  {SMI_BASE >> 8, SB_SMI_SBGppPme2, 0, 17},
-  {SMI_BASE >> 8, SB_SMI_SBGppPme3, 0, 18},
-  {SMI_BASE >> 8, SB_SMI_GecPme, 0, 19},
-  {SMI_BASE >> 8, SB_SMI_CIRPme, 0, 28},
-  {SMI_BASE >> 8, SB_SMI_Gevent8, 0, 24},
-  {SMI_BASE >> 8, SB_SMI_AzaliaPme, 0, 27},
-  {SMI_BASE >> 8, SB_SMI_SataGevent0, 0, 30},
-  {SMI_BASE >> 8, SB_SMI_SataGevent1, 0, 31},
-  {SMI_BASE >> 8, SB_SMI_REG08,  0xE7, 0},
-  {SMI_BASE >> 8, SB_SMI_REG0C + 2, ~BIT3, BIT3},
-  {SMI_BASE >> 8, SB_SMI_TWARN, 0, 9},
-// RPR CG PLL CMOX Clock Driver Setting for power saving
-  {MISC_BASE >> 8, SB_MISC_REG18 + 0x06, 0, 0xE0},
-  {MISC_BASE >> 8, SB_MISC_REG18 + 0x07, 0, 0x1F},
-  //{SERIAL_DEBUG_BASE >> 8, SB_SDB_REG74, 0, 0},
-  {0xFF, 0xFF, 0xFF, 0xFF},
-};
-
-/**
- * abTblEntry800 - AB-Link Configuration Table for Hudson-2
- *
- */
-ABTBLENTRY abTblEntry800[] =
-{
-  // RPR Enable downstream posted transactions to pass non-posted transactions.
-  {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
-
-  // RPR Enable Hudson-2 to issue memory read/write requests in the upstream direction.
-  {AXCFG, SB_AB_REG04, BIT2, BIT2},
-
-  // RPR Enabling IDE/PCIB Prefetch for Performance Enhancement
-  // PCIB prefetch   ABCFG 0x10060 [20] = 1   ABCFG 0x10064 [20] = 1
-  {ABCFG, SB_ABCFG_REG10060, BIT20, BIT20}, //  PCIB prefetch enable
-  {ABCFG, SB_ABCFG_REG10064, BIT20, BIT20}, //  PCIB prefetch enable
-
-  // RPR Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices.
-  // RPR Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11)
-  {ABCFG, SB_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18},
-
-  // RPR Enabled SMI ordering enhancement. ABCFG 0x90[21]
-  // RPR 7.7 USB Delay A-Link Express L1 State. ABCFG 0x90[16]
-  {ABCFG, SB_ABCFG_REG90, BIT21 + BIT16, BIT21 + BIT16},
-
-  // RPR Disable the credit variable in the downstream arbitration equation
-  // RPR Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set)
-  {ABCFG, SB_ABCFG_REG9C, BIT0, BIT0},
-
-  // RPR Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
-  // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
-  {ABCFG, SB_ABCFG_REG94, BIT20, BIT20 + 0x00FEE},
-
-  // RPR Programming cycle delay for AB and BIF clock gating
-  // RPR Enable the AB and BIF clock-gating logic.
-  // RPR Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently
-  // RPR Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP
-  {ABCFG, SB_ABCFG_REG10054,  0x00FFFFFF, 0x010407FF},
-  {ABCFG, SB_ABCFG_REG98,  0xFFFC00FF, 0x00034700},
-  {ABCFG, SB_ABCFG_REG54,  0x00FF0000, 0x00040000},
-  // RPR Non-Posted Memory Write Support
-  {AXINDC, SB_AX_INDXC_REG10, BIT9, BIT9},
-  // RPR 4.18 UMI L1 Configuration
-  //Step 1: AXINDC_Reg 0x02[0] = 0x1 Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off.
-  //Step 2: AXINDP_Reg 0x02[15] = 0x1 Sets REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to prevent LC from going to L1 when there are outstanding completions.
-  {AXINDC, SB_AX_INDXC_REG02, BIT0, BIT0},
-  {AXINDP, SB_AX_INDXP_REG02, BIT15, BIT15},
-  {ABCFG, 0, 0, (UINT8) 0xFF},  // This dummy entry is to clear ab index
-  { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
-};
-
-/**
- * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature
- *
- */
-ABTBLENTRY SbPcieOrderRule[] =
-{
-// abPostPassNpDownStreamTbl
-  {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31},
-  {ABCFG, SB_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5},
-  {ABCFG, SB_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7},
-  {ABCFG, SB_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23},
-  {ABCFG, SB_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5},
-  {AXINDC, SB_AX_INDXC_REG02, BIT9, BIT9},
-  {ABCFG, SB_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12},
-// abPostPassNpUpStreamTbl
-  {ABCFG, SB_ABCFG_REG58, BIT10, BIT10},
-  {ABCFG, SB_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4},
-  {ABCFG, SB_ABCFG_REG54, BIT1, BIT1},
-  { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
-};
-
-/**
- * Table for SD controller capability register
- *
- *
- *
- *
- */
-UINT32 sdCap[] =
-{
-  0x00000000, //
-  0x039FD972, //
-  0x839ED972, //
-  0x839AD972, //
-  0x839DD972, //
-  0x839CD972, //
-  0x8398D972, //
-};
-
-/**
- * Table for Spread Spectrum
- *
- * RPR 12.9 Internal Clock Generator Spread Profile - to set default value to 0.363%.
- *
- *
- */
-SB_SPREAD_SPECTRUM_ENTRY SpreadParameterTable[] =
-{
-  {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},               //  Disabled
-  {1, 0x318, 0, 0x6F83, 0x90, 0, 0x07, 0, 1, 1},// -3630 ppm :1:Default
-  {1, 0x318, 0, 0x7AE1, 0x9F, 0, 0x0D, 0, 1, 1},// -4000 ppm :2
-  {1, 0x318, 0, 0x77CF, 0x9B, 0, 0x0B, 0, 1, 1},// -3900 ppm :3
-  {1, 0x318, 0, 0x74BC, 0x94, 0, 0x0A, 0, 1, 1},// -3800 ppm :4
-  {1, 0x318, 0, 0x71AA, 0x93, 0, 0x08, 0, 1, 1},// -3700 ppm :5
-  {1, 0x318, 0, 0x6FD2, 0x90, 0, 0x07, 0, 1, 1},// -3640 ppm :6
-  {1, 0x318, 0, 0x6F83, 0x90, 0, 0x07, 0, 1, 1},// -3630 ppm :7
-  {1, 0x318, 0, 0x6F35, 0x8F, 0, 0x07, 0, 1, 1},// -3620 ppm :8
-  {1, 0x318, 0, 0x6EE6, 0x8F, 0, 0x07, 0, 1, 1},// -3610 ppm :9
-  {1, 0x318, 0, 0x6E98, 0x8F, 0, 0x07, 0, 1, 1},// -3600 ppm :10
-  {1, 0x318, 0, 0x6E49, 0x8E, 0, 0x07, 0, 1, 1},// -3590 ppm :11
-  {1, 0x018, 0, 0x6666, 0x83, 0, 0x00, 0, 0, 1} // -3500 ppm :12
-};
-
-/**
- * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
- *
- *    This settings should be done during S3 resume also
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-commonInitEarlyBoot (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32   abValue;
-  UINT16   dwTempVar;
-  SB_CPUID_DATA  CpuId;
-  UINT8   cimNativepciesupport;
-  UINT8   cimIrConfig;
-  UINT8   Data;
-  UINT8   cimALinkClkGateOff;
-  UINT8   cimBLinkClkGateOff;
-
-  cimNativepciesupport = (UINT8) pConfig->NativePcieSupport;
-  cimIrConfig = (UINT8) pConfig->IrConfig;
-  cimALinkClkGateOff = (UINT8) pConfig->ALinkClkGateOff;
-  cimBLinkClkGateOff = (UINT8) pConfig->BLinkClkGateOff;
-
-#if  SB_CIMx_PARAMETER == 0
-  cimNativepciesupport = cimNativepciesupportDefault;
-  cimIrConfig = cimIrConfigDefault;
-#endif
-  //Clear hwmSbtsiAutoPollStarted
-  pConfig->hwm.hwmSbtsiAutoPollStarted = FALSE;
-  //Ac Loss Control
-  AcLossControl (pConfig->PwrFailShadow);
-
-  //SB VGA Init
-  // OBS194249 Cobia_Nutmeg_DP-VGA Electrical SI validation_Lower RGB Luminance level BGADJ=0x1F & DACADJ=0x1B
-  // Removed for OBS194249 causes display issue in Windows
-  // SbVgaInit ();
-
-  //IR init Logical device 0x05
-  if ( cimIrConfig ) {
-    EnterEcConfig ();
-    RWEC8 (0x07, 0x00, 0x05);         //Select logical device 05, IR controller
-    RWEC8 (0x60, 0x00, 0x05);         //Set Base Address to 550h
-    RWEC8 (0x61, 0x00, 0x50);
-    RWEC8 (0x70, 0xF0, 0x05);         //Set IRQ to 05h
-    RWEC8 (0x30, 0x00, 0x01);         //Enable logical device 5, IR controller
-    Data = 0xAB;
-    WriteIO (0x550, AccWidthUint8, &Data);
-    ReadIO (0x551, AccWidthUint8, &Data);
-    Data = (((Data & 0xFC ) | 0x20) | cimIrConfig);
-    WriteIO (0x551, AccWidthUint8, &Data);
-//    Data = 0xCA;
-//    WriteIO (0x550, AccWidthUint8, &Data);
-//    Data = 0x81;
-//    WriteIO (0x551, AccWidthUint8, &Data);
-
-    ExitEcConfig ();
-    Data = 0xA0;                      // EC APIC index
-    WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
-    Data = 0x05;                      // IRQ5
-    WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
-  } else {
-    EnterEcConfig ();
-    //if (pConfig->Sdb != 1 ) {
-      //RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 0x04, AccWidthUint8, 0, 0);
-    //}
-    RWEC8 (0x07, 0x00, 0x05);         //Select logical device 05, IR controller
-    RWEC8 (0x30, 0x00, 0x00);         //Disable logical device 5, IR controller
-    ExitEcConfig ();
-  }
-
-
-  TRACE ((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n"));
-  CpuidRead (0x01, &CpuId);
-
-  //
-  // SB CFG programming
-  //
-  //Make BAR registers of smbus visible.
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
-  //Early post initialization of pci config space
-  programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]),
-                       ARRAY_SIZE(sbEarlyPostByteInitTable));
-  if ( pConfig->BuildParameters.SmbusSsid != 0 ) {
-    RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);
-  }
-  //Make BAR registers of smbus invisible.
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6);
-
-  //
-  // LPC CFG programming
-  //
-  // SSID for LPC Controller
-  if (pConfig->BuildParameters.LpcSsid != 0 ) {
-    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);
-  }
-  // LPC MSI
-  if ( pConfig->BuildParameters.LpcMsi) {
-    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG78, AccWidthUint32 | S3_SAVE, ~BIT1, BIT1);
-  }
-
-  //
-  // PCIB CFG programming
-  //
-  //Disable or Enable PCI Clks based on input
-  Data = ~(pConfig->PciClks);
-  RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG42, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2), (Data & 0x0F) << 2 );
-  RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4A, AccWidthUint8 | S3_SAVE, ~(BIT3 + BIT2 + BIT1 + BIT0), Data >> 4 );
-  // PCIB MSI
-  if ( pConfig->BuildParameters.PcibMsi) {
-    RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG40, AccWidthUint8 | S3_SAVE, ~BIT3, BIT3);
-  }
-
-  if (  pConfig->SlowSpeedABlinkClock ) {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG40, AccWidthUint8, ~BIT1, BIT1);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG40, AccWidthUint8, ~BIT1, 0);
-  }
-
-  //
-  // AB CFG programming
-  //
-  // Read Arbiter address, Arbiter address is in PMIO 6Ch
-  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, &dwTempVar);
-  RWIO (dwTempVar, AccWidthUint8, 0, 0);        // Write 0 to enable the arbiter
-
-  abLinkInitBeforePciEnum (pConfig);            // Set ABCFG registers
-  // AB MSI
-  if ( pConfig->BuildParameters.AbMsi) {
-    abValue = readAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29));
-    abValue = abValue | BIT20;
-    writeAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29), abValue);
-  }
-
-
-  //
-  // SB Specific Function programming
-  //
-
-  // PCIE Native setting
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBA + 1, AccWidthUint8, ~BIT14, 0);
-  if ( pConfig->NativePcieSupport == 1) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT3 + BIT2 + BIT0);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT3 + BIT2);
-  }
-
-#ifdef ACPI_SLEEP_TRAP
-  // Set SLP_TYPE as SMI event
-  RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB0, AccWidthUint8, ~(BIT2 + BIT3), BIT2);
-  // Disabled SLP function for S1/S3/S4/S5
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBE, AccWidthUint8, ~BIT5, 0x00);
-  // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1)
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG08 + 3, AccWidthUint8, ~(BIT0 + BIT1), BIT1);
-  // Enabled Global Smi ( BIT7 clear as 0 to enable )
-  RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG98 + 3 , AccWidthUint8, ~BIT7, 0x00);
-#endif
-  // Set Stutter timer settings
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8, ~(BIT3 + BIT4), BIT3 + BIT4);
-  // Set LDTSTP# duration to 10us for HydraD CPU, or when HT link is 200MHz
-  if ((pConfig->AnyHT200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x0A);
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8, 0xFE, 0x28);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x01);
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8, 0xFE, 0x20);
-  }
-  // A/B Clock Gate-OFF
-  if ( (IsSbA12Plus ()) && ( cimALinkClkGateOff || cimBLinkClkGateOff )) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG04 + 2, AccWidthUint8, ~(BIT0), BIT0);
-  }
-  if ( cimALinkClkGateOff ) {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccWidthUint8, 0xFE, BIT0);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccWidthUint8, 0xFE, 0x00);
-  }
-  if ( cimBLinkClkGateOff ) {
-    if ( IsSbA11 () ) {
-      // RPR13.7 B-Link Clock Gating Threshold for A11 only
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x2D, AccWidthUint8, 0xEF, 0x10); //A11 Only
-    }
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccWidthUint8, 0xFD, BIT1);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccWidthUint8, 0xFD, 0x00);
-  }
-  // RPR SSC will provide better jitter margin
-  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccWidthUint8, 0xFC, 0x01);
-  // Set ACPIMMIO by OEM Input table
-  programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
-  // 2.9 NB Power Good Control on System Reset
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBF, AccWidthUint8, ~ (BIT0), 0);
-  // 2.10 Extend SerIrq request
-  RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ (BIT29), (BIT29));
-  // 2.13 Clear status of SATA PERR
-  Data = BIT6;
-  WriteMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG3C, AccWidthUint8, &Data);
-  Data = BIT7;
-  WriteMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG84 + 2, AccWidthUint8, &Data);
-
-  if (IsSbA13Plus ()) {
-    // 2.14 Enable Delayed SLP_S3/S5 to the Board
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 1, AccWidthUint8, 0xFF, BIT2);
-    // 2.15 Enable C-State Wake-up before Warm Reset
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBE, AccWidthUint8, ~ (BIT0), BIT0);
-    // 3.16 Disable LPC A-Link Cycle Bypass
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ (BIT19), (BIT19));
-  }
-  //RPR 3.5 Enabling  LPCCLK0 Power-down Function
-  //OBS261463 Torpedo-IMC Fan Control-System stops somewhere when running S3
-  if ((!isImcEnabled ()) && (IsSbA13Plus ())) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD2, AccWidthUint8, ~ (BIT3), BIT3);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD2, AccWidthUint8, ~ (BIT3), 0);
-  }
-  TRACE ((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n"));
-}
-
-/**
- * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-abSpecialSetBeforePciEnum (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32   abValue;
-  abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
-  abValue &= 0xf0;
-  if ( pConfig->SbPcieOrderRule && abValue ) {
-    abValue = readAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29));
-    abValue = abValue | BIT9;
-    writeAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), abValue);
-  }
-}
-
-/**
- * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
- *
- *    This settings might not program during S3 resume
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-commonInitEarlyPost (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8  dbPortStatus;
-  UINT8  Data;
-  UINT32  Data32;
-  UINT8  cimSpreadSpectrum;
-  UINT8  maxSpreadEntry;
-  AMDSBCFG*   pTmp;
-  pTmp = pConfig;
-
-  maxSpreadEntry = (sizeof SpreadParameterTable) / (sizeof (SB_SPREAD_SPECTRUM_ENTRY));
-
-  cimSpreadSpectrum = pConfig->SpreadSpectrum;
-#if  SB_CIMx_PARAMETER == 0
-  cimSpreadSpectrum = cimSpreadSpectrumDefault;
-#endif
-  programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioEPostInitTable[0]));
-
-  // Turn on and configure LPC clock (48MHz)
-  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x28, AccWidthUint32, ~(BIT21 + BIT20 + BIT19), 2 << 19);
-  RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG40, AccWidthUint8, ~BIT7, 0);
-
-  if ( cimSpreadSpectrum ) {
-    if ( IsSbA11 () ) {
-    // Misc_Reg_40[25]=1 -> allow to change spread profile
-    // Misc_Reg19=83 -> new spread profile
-    // Misc_Reg[12:10]=9975be
-    // Misc_Reg0B=91
-    // Misc_Reg09=21
-    // Misc_Misc_Reg_08[0]=1 -> enable spread
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x43, AccWidthUint8, ~BIT1, BIT1);
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x19, AccWidthUint8, 0, 0x83);
-      getChipSysMode (&dbPortStatus);
-      if ( ((dbPortStatus & ChipSysIntClkGen) != ChipSysIntClkGen) ) {
-        RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1A, AccWidthUint8, ~(BIT5 + BIT6 + BIT7), 0x80);
-      }
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x99);
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x75);
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xBE);
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x91);
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21);
-    }
-    if ( cimSpreadSpectrum >= maxSpreadEntry ) {
-      cimSpreadSpectrum = 1;
-    }
-    if ( IsSbA12Plus () ) {
-
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccWidthUint32, (UINT32) (~(0x1 << 25)), ( SpreadParameterTable[cimSpreadSpectrum].P_40_25 << 25));
-
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccWidthUint32, (UINT32) (~(0x1 << 0)), (0x0 << 0));
-
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint32, (UINT32) (~(0x7FF << 5)), (SpreadParameterTable[cimSpreadSpectrum].P_18_15_5 << 5));
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint32, (UINT32) (~(0xF << 16)), (SpreadParameterTable[cimSpreadSpectrum].P_18_19_16 << 16));
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint32, (UINT32) (~(0xFFFF << 8)), (SpreadParameterTable[cimSpreadSpectrum].P_10_23_8 << 8));
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint32, (UINT32) (~(0xFF << 0)), (SpreadParameterTable[cimSpreadSpectrum].P_10_7_0 << 0));
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccWidthUint32, (UINT32) (~(0x3F << 0)), (SpreadParameterTable[cimSpreadSpectrum].P_1C_5_0 << 0));
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccWidthUint32, (UINT32) (~(0xF << 28)), (SpreadParameterTable[cimSpreadSpectrum].P_08_31_28 << 28));
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccWidthUint32, (UINT32) (~(0x1 << 7)), (SpreadParameterTable[cimSpreadSpectrum].P_08_7 << 7));
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccWidthUint32, (UINT32) (~(0x1 << 8)), (SpreadParameterTable[cimSpreadSpectrum].P_08_8 << 8));
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint32, (UINT32) (~(0x3 << 24)), (SpreadParameterTable[cimSpreadSpectrum].P_10_25_24 << 24));
-    }
-    if ( IsExternalClockMode () ) {
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x00);
-    } else {
-      RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x01);
-    }
-  } else {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x00);
-  }
-
-  // SD Configuration
-  if ( pConfig->sdConfig ) {
-    //OBS263741 TTP1000D: SD Host Controller can't be enabled after disabling it in BIOS setup.
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE +  SB_PMIOA_REGD3, AccWidthUint8, 0xBF, 0x40);
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE +  SB_MISC_REG41, AccWidthUint8, 0xF1, 0x48);
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE +  SB_MISC_REG42, AccWidthUint8, 0xFE, 0x00);
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE +  SB_PMIOA_REGE7, AccWidthUint8, 0x00, 0x12);
-    // INT#A SD resource
-    Data = 0x97; // Azalia APIC index
-    WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
-    Data = 0x10; // IRQ16 (INTA#)
-    WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
-
-    ReadPCI ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA4, AccWidthUint32, &Data32);
-    Data32 |= BIT31 + BIT24 + BIT18 + BIT16; //ADMA
-    if ( pConfig->sdConfig == 2) {
-      Data32 &=  ~(BIT16 + BIT24); //DMA
-    } else if ( pConfig->sdConfig == 3) {
-      Data32 &=  ~(BIT16 + BIT18 + BIT24); //PIO
-    }
-    Data32 &= ~(BIT17 + BIT23); //clear bitwidth
-    Data32 |= (pConfig->sdSpeed << 17) + (pConfig->sdBitwidth << 23);
-    RWPCI ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA4, AccWidthUint32 | S3_SAVE, 0, Data32);
-    //SB02544: SD: Some SD cards cannot be detected in HIGH speed mode
-    if ( IsSbA12Plus () ) {
-      RWPCI ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGB0, AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x03 << 10)), (UINT32) (0x03 << 10));
-    }
-    //BUG260949  There isn't code that set SSID of SD Controller in Hudson CIMX
-    ReadPCI ((SD_BUS_DEV_FUN << 16) + SD_PCI_REG00, AccWidthUint32, &Data32);
-    RWPCI ((SD_BUS_DEV_FUN << 16) + SD_PCI_REG2C, AccWidthUint32 | S3_SAVE, 0, Data32);
-  } else {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE +  SB_PMIOA_REGD3, AccWidthUint8, 0xBF, 0x00);
-  }
-
-  // RPR PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode (BIT5)
-  // RPR OSC Clock setting for  internal clock generator mode (BIT6)
-  getChipSysMode (&dbPortStatus);
-  if ( ((dbPortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE +  SB_MISC_REG04 + 1, AccWidthUint8, ~(BIT5 + BIT6), BIT5 + BIT6);
-  }
-
-  // Set ASF SMBUS master function enabled here (temporary)
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16 | S3_SAVE, ~(BIT0 + BIT2), BIT0 + BIT2);
-
-  programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
-
-#ifndef NO_EC_SUPPORT
-  // Software IMC enable
-  if (((pConfig->BuildParameters.ImcEnableOverWrite == 1) && ((dbPortStatus & ChipSysEcEnable) == 0)) || ((pConfig->BuildParameters.ImcEnableOverWrite == 2) && ((dbPortStatus & ChipSysEcEnable) == ChipSysEcEnable))) {
-    if (validateImcFirmware (pConfig)) {
-      softwareToggleImcStrapping (pConfig);
-    }
-  }
-#endif
-
-}
-/**
- * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-abLinkInitBeforePciEnum (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  cimResetCpuOnSyncFlood;
-  ABTBLENTRY  *pAbTblPtr;
-  AMDSBCFG* Temp;
-
-  cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood;
-#if  SB_CIMx_PARAMETER == 0
-  cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault;
-#endif
-  Temp = pConfig;
-  if ( pConfig->SbPcieOrderRule == 1 ) {
-    pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]);
-    abcfgTbl (pAbTblPtr);
-  }
-  if ( pConfig->SbPcieOrderRule == 2 ) {
-    rwAlink (SB_ABCFG_REG10090 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 10), (UINT32) (0x7 << 10));
-    rwAlink (SB_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1F << 11), (UINT32) (0x1C << 11));
-    rwAlink (SB_ABCFG_REGB4 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 0), (UINT32) (0x3 << 0));
-  }
-  pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&abTblEntry800[0]);
-  abcfgTbl (pAbTblPtr);
-  if ( cimResetCpuOnSyncFlood ) {
-    rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2);
-  }
-
-  if ( pConfig->AbClockGating ) {
-    rwAlink (SB_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
-    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
-    rwAlink (SB_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24));
-    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24));
-  } else {
-    rwAlink (SB_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24));
-    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24));
-  }
-
-
-  if ( pConfig->GppClockGating ) {
-    rwAlink (SB_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 12), (UINT32) (0x4 << 12));
-    rwAlink (SB_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x7 << 8));
-    rwAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0));
-  } else {
-    rwAlink (SB_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x0 << 8));
-    rwAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0));
-  }
-
-  if ( pConfig->L1TimerOverwrite ) {
-    rwAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 12), (UINT32) (pConfig->L1TimerOverwrite  << 12));
-    rwAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x1  << 15));
-  }
-
-  if ( pConfig->UmiLinkWidth ) {
-//    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
-  }
-  if ( pConfig->UmiDynamicSpeedChange ) {
-    rwAlink ((UINT32) SB_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0));
-    rwAlink ((UINT32) SB_AX_CFG_REG88, ~ (UINT32) (0xF << 0), (UINT32) (0x2 << 0));
-    rwAlink ((UINT32) SB_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 18), (UINT32) (0x1 << 18));
-  }
-  if ( pConfig->PcieRefClockOverclocking ) {
-//    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
-  }
-  if ( pConfig->SbAlinkGppTxDriverStrength  ) {
-    rwAlink (SB_ABCFG_REGA8 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 18), (UINT32) ((pConfig->SbAlinkGppTxDriverStrength - 1) << 18));
-    rwAlink (SB_ABCFG_REGA0 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 8), (UINT32) (0x1 << 8));
-  }
-  if ( pConfig->PcieAER ) {
-//    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
-  }
-  if ( pConfig->PcieRAS ) {
-//    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
-  }
-}
-
-/**
- * abcfgTbl - Program ABCFG by input table.
- *
- *
- * @param[in] pABTbl  ABCFG config table.
- *
- */
-VOID
-abcfgTbl (
-  IN       ABTBLENTRY* pABTbl
-  )
-{
-  UINT32   ddValue;
-
-  while ( (pABTbl->regType) != 0xFF ) {
-    TRACE ((DMSG_SB_TRACE, "RegType: %X, RegNumber: %X, AndMask = %X, OrMask = %X \n", pABTbl->regType, pABTbl->regIndex, pABTbl->regMask, pABTbl->regData));
-    if ( pABTbl->regType == AXINDC ) {
-      ddValue = 0x30 | (pABTbl->regType << 29);
-      writeAlink (ddValue, (pABTbl->regIndex & 0x00FFFFFF));
-      ddValue = 0x34 | (pABTbl->regType << 29);
-      writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
-    } else if ( pABTbl->regType == AXINDP ) {
-      ddValue = 0x38 | (pABTbl->regType << 29);
-      writeAlink (ddValue, (pABTbl->regIndex & 0x00FFFFFF));
-      ddValue = 0x3C | (pABTbl->regType << 29);
-      writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
-    } else {
-      ddValue = pABTbl->regIndex | (pABTbl->regType << 29);
-      writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
-    }
-    ++pABTbl;
-  }
-
-  //Clear ALink Access Index
-  ddValue = 0;
-  WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue);
-  TRACE ((DMSG_SB_TRACE, "Exiting abcfgTbl\n"));
-}
-
-/**
- * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-commonInitLateBoot (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8  dbValue;
-  UINT32  ddVar;
-  UINT8  NStBit;
-  UINT8  NSBit;
-  UINT8  indexValue;
-
-  // We need to do the following setting in late post also because some bios core pci enumeration changes these values
-  // programmed during early post.
-  // RPR 4.5 Master Latency Timer
-
-  dbValue = 0x40;
-  WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG0D, AccWidthUint8, &dbValue);
-  WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG1B, AccWidthUint8, &dbValue);
-
-  //RPR 6.4 CLKRUN#
-  // SB P2P AutoClock control settings.
-  // ddVar = (pConfig->PcibAutoClkCtrlLow) | (pConfig->PcibAutoClkCtrlLow);
-  if ( pConfig->ClockRun ) {
-    ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG54, AccWidthUint8, &dbValue);
-    NStBit = dbValue & 0x03;
-    NSBit = (dbValue & 0x3F ) >> 2;
-    ddVar = (4 + (NStBit * 2) + (( 17 + NSBit) * 3) + 4) | 0x01;
-    if ( IsSbA12Plus () ) {
-      ddVar = 9; //4 clocks
-    }
-    WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4C, AccWidthUint32, &ddVar);
-  }
-
-
-
-  ddVar = (pConfig->PcibClkStopOverride);
-  RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6));
-
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, 0xBF | S3_SAVE, BIT3 + BIT4 + BIT5);
-
-  if ( IsGCPU () ) {
-    GcpuRelatedSetting (pConfig);
-  } else {
-    c3PopupSetting (pConfig);
-  }
-  //[RPR 2.12] Mt C1E Enable
-  MtC1eEnable (pConfig);
-
-  RWPCI ((0xC1 << 16) + 0xBC, AccWidthUint8, 0x7f, 0x80);
-
-  //if (pConfig->Sdb == 1 ) {
-    //RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE +  SB_SDB_REG00, AccWidthUint8, 0xFF, 0x05);
-  //}
-
-  if ( pConfig->XhciSwitch == 1 ) {
-    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccWidthUint8, &dbValue);
-    indexValue = XHCI_REGISTER_BAR00;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x11, AccWidthUint8, &dbValue);
-    indexValue = XHCI_REGISTER_BAR01;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x12, AccWidthUint8, &dbValue);
-    indexValue = XHCI_REGISTER_BAR02;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x13, AccWidthUint8, &dbValue);
-    indexValue = XHCI_REGISTER_BAR03;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
-    indexValue = XHCI_REGISTER_04H;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
-    indexValue = XHCI_REGISTER_0CH;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
-    indexValue = XHCI_REGISTER_3CH;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccWidthUint8, &dbValue);
-    indexValue = XHCI1_REGISTER_BAR00;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x11, AccWidthUint8, &dbValue);
-    indexValue = XHCI1_REGISTER_BAR01;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x12, AccWidthUint8, &dbValue);
-    indexValue = XHCI1_REGISTER_BAR02;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x13, AccWidthUint8, &dbValue);
-    indexValue = XHCI1_REGISTER_BAR03;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
-    indexValue = XHCI1_REGISTER_04H;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
-    indexValue = XHCI1_REGISTER_0CH;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-
-    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
-    indexValue = XHCI1_REGISTER_3CH;
-    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
-    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
-  }
-}
-
-/**
- * hpetInit - Program Southbridge HPET function
- *
- *
- *
- * @param[in] pConfig         Southbridge configuration structure pointer.
- * @param[in] pStaticOptions  Platform build configuration table.
- *
- */
-VOID
-hpetInit (
-  IN       AMDSBCFG* pConfig,
-  IN       BUILDPARAM *pStaticOptions
-  )
-{
-  DESCRIPTION_HEADER* pHpetTable;
-  UINT8 cimHpetTimer;
-  UINT8 cimHpetMsiDis;
-
-  cimHpetTimer = (UINT8) pConfig->HpetTimer;
-  cimHpetMsiDis = (UINT8) pConfig->HpetMsiDis;
-#if  SB_CIMx_PARAMETER == 0
-  cimHpetTimer = cimHpetTimerDefault;
-  cimHpetMsiDis = cimHpetMsiDisDefault;
-#endif
-  pHpetTable = NULL;
-  if ( cimHpetTimer == TRUE ) {
-    //Program the HPET BAR address
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, pStaticOptions->HpetBase);
-    //Enabling decoding of HPET MMIO
-    //Enable HPET MSI support
-    //Enable High Precision Event Timer (also called Multimedia Timer) interrupt
-    if ( cimHpetMsiDis == FALSE ) {
-      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1 + BIT2 + BIT3 + BIT4);
-#ifdef SB_TIMER_TICK_INTERVAL_WA
-      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1);
-#endif
-    } else {
-      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1);
-    }
-
-  } else {
-    if ( ! (pConfig->S3Resume) ) {
-      pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable (Int32FromChar('T', 'E', 'P', 'H'));
-    }
-    if ( pHpetTable != NULL ) {
-      pHpetTable->Signature = Int32FromChar('H', 'P', 'E', 'T');
-    }
-  }
-}
-
-/**
- * c3PopupSetting - Program Southbridge C state function
- *
- *
- *
- * @param[in] pConfig   Southbridge configuration structure pointer.
- *
- */
-VOID
-c3PopupSetting (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  AMDSBCFG* Temp;
-  UINT8  dbValue;
-  Temp = pConfig;
-  dbValue = getNumberOfCpuCores  ();
-#define NON_SUPPORT_PREVIOUS_C3 TRUE
-#ifndef NON_SUPPORT_PREVIOUS_C3
-  if (dbValue > 1) {
-    //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
-    //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
-    //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert
-    //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT2), (BIT1 + BIT2));
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);
-  }
-  //SB800 needs to changed for RD790 support
-  //PM 0x80 [8] = 0 for system with RS780
-  //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
-  //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
-  //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F);
-  //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
-  //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
-  //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
-  //link is disconnected.
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94 + 2, AccWidthUint8, 0, 0x10);
-
-  //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
-  //delay will allow USB DMA to go on in a continuous manner
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 1, AccWidthUint8, 0, 0x10);
-  // Not in the RPR so far, it's hand writing from ASIC
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C, AccWidthUint8 | S3_SAVE, 0, 0x85);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C + 1, AccWidthUint8 | S3_SAVE, 0, 0x01);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E + 1, AccWidthUint8 | S3_SAVE, ~(BIT7 + BIT5), BIT7 + BIT5);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4);
-  // RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x10);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, 0, 0x10);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4 + 1, AccWidthUint8, 0, 0x0B);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~(BIT4 + BIT5), BIT4 + BIT5);
-
-#else
-  //RPR2.4 C-State and VID/FID Change
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~(BIT5), BIT5);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT2), BIT2);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT1), BIT1);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E, AccWidthUint8 | S3_SAVE, ~(BIT6), BIT6);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8 | S3_SAVE, 0, 0x01);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG89, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG9B, AccWidthUint8 | S3_SAVE, ~(BIT6 + BIT5 + BIT4), BIT4);
-
-  //RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT10), BIT10);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG9B, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT0), 0);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG96, AccWidthUint8 | S3_SAVE, 0, 0x10);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG99, AccWidthUint8 | S3_SAVE, 0, 0x10);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG8E, AccWidthUint8 | S3_SAVE, 0, 0x80);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG97, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT0), 0);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT4), BIT4);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT9), BIT9);
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT7), 0);
-
-#endif
-}
-
-/**
- * GcpuRelatedSetting - Program GCPU C related function
- *
- *
- *
- * @param[in] pConfig   Southbridge configuration structure pointer.
- *
- */
-VOID
-GcpuRelatedSetting (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8 cimAcDcMsg;
-  UINT8 cimTimerTickTrack;
-  UINT8 cimClockInterruptTag;
-  UINT8 cimOhciTrafficHanding;
-  UINT8 cimEhciTrafficHanding;
-  UINT8 cimFusionMsgCMultiCore;
-  UINT8 cimFusionMsgCStage;
-  UINT32 ddValue;
-
-  cimAcDcMsg = (UINT8) pConfig->AcDcMsg;
-  cimTimerTickTrack = (UINT8) pConfig->TimerTickTrack;
-  cimClockInterruptTag = (UINT8) pConfig->ClockInterruptTag;
-  cimOhciTrafficHanding = (UINT8) pConfig->OhciTrafficHanding;
-  cimEhciTrafficHanding = (UINT8) pConfig->EhciTrafficHanding;
-  cimFusionMsgCMultiCore = (UINT8) pConfig->FusionMsgCMultiCore;
-  cimFusionMsgCStage = (UINT8) pConfig->FusionMsgCStage;
-#if  SB_CIMx_PARAMETER == 0
-  cimAcDcMsg = cimAcDcMsgDefault;
-  cimTimerTickTrack = cimTimerTickTrackDefault;
-  cimClockInterruptTag = cimClockInterruptTagDefault;
-  cimOhciTrafficHanding = cimOhciTrafficHandingDefault;
-  cimEhciTrafficHanding = cimEhciTrafficHandingDefault;
-  cimFusionMsgCMultiCore = cimFusionMsgCMultiCoreDefault;
-  cimFusionMsgCStage = cimFusionMsgCStageDefault;
-#endif
-  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);
-  ddValue = ddValue & 0xC07F00A0;
-  if ( cimAcDcMsg ) {
-    ddValue = ddValue | BIT0;
-  }
-  if ( cimTimerTickTrack ) {
-    ddValue = ddValue | BIT1;
-  }
-  if ( cimClockInterruptTag ) {
-    ddValue = ddValue | BIT10;
-  }
-  if ( cimOhciTrafficHanding ) {
-    ddValue = ddValue | BIT13;
-  }
-  if ( cimEhciTrafficHanding ) {
-    ddValue = ddValue | BIT15;
-  }
-  if ( cimFusionMsgCMultiCore ) {
-    ddValue = ddValue | BIT23;
-  }
-  if ( cimFusionMsgCMultiCore ) {
-    ddValue = (ddValue | (BIT6 + BIT4 + BIT3 + BIT2));
-  }
-
-  WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);
-}
-
-/**
- * MtC1eEnable - Program Mt C1E Enable Function
- *
- *
- *
- * @param[in] pConfig   Southbridge configuration structure pointer.
- *
- */
-VOID
-MtC1eEnable (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  if ( pConfig->MtC1eEnable ) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7A, AccWidthUint16 | S3_SAVE, ~ BIT15, BIT15);
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7A, AccWidthUint16 | S3_SAVE, ~ (BIT3 + BIT2 + BIT1 + BIT0), 0x01);
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~ BIT13, BIT13);
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~ BIT7, BIT7);
-  }
-}
-
-#ifndef NO_EC_SUPPORT
-/**
- * validateImcFirmware - Validate IMC Firmware.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- * @retval        TRUE   Pass
- * @retval        FALSE  Failed
- */
-BOOLEAN
-validateImcFirmware (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ImcSig;
-  UINT32  ImcSigAddr;
-  UINT32  ImcAddr;
-  UINT32  CurAddr;
-  UINT32  ImcBinSig0;
-  UINT32  ImcBinSig1;
-  UINT16  ImcBinSig2;
-  UINT8  dbIMCChecksume;
-  UINT8  dbIMC;
-  ImcAddr = 0;
-
-  // Software IMC enable
-  ImcSigAddr = 0x80000; // start from 512k to 64M
-  ImcSig = 0x0; //
-  while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) {
-    CurAddr = 0xffffffff - ImcSigAddr + 0x20001;
-    ReadMEM (CurAddr, AccWidthUint32, &ImcSig);
-    ReadMEM ((CurAddr + 4), AccWidthUint32, &ImcAddr);
-    ImcSigAddr <<= 1;
-  }
-
-  dbIMCChecksume = 0xff;
-  if ( ImcSig == 0x55aa55aa ) {
-    // "_AMD_IMC_C" at offset 0x2000 of the binary
-    ReadMEM ((ImcAddr + 0x2000), AccWidthUint32, &ImcBinSig0);
-    ReadMEM ((ImcAddr + 0x2004), AccWidthUint32, &ImcBinSig1);
-    ReadMEM ((ImcAddr + 0x2008), AccWidthUint16, &ImcBinSig2);
-    if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) {
-      dbIMCChecksume = 0;
-      for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) {
-        ReadMEM (CurAddr, AccWidthUint8, &dbIMC);
-        dbIMCChecksume = dbIMCChecksume + dbIMC;
-      }
-    }
-  }
-  if ( dbIMCChecksume ) {
-    return  FALSE;
-  } else {
-    return  TRUE;
-  }
-}
-
-/**
- * softwareToggleImcStrapping - Software Toggle IMC Firmware Strapping.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-softwareToggleImcStrapping (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8  dbValue;
-  UINT8  dbPortStatus;
-  UINT32  abValue;
-  UINT32  abValue1;
-
-  getChipSysMode (&dbPortStatus);
-
-  ReadPMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);
-  //if ( (dbValue & (BIT6 + BIT7)) != 0xC0 ) {  // PwrGoodOut =1, PwrGoodEnB=1
-  //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference.
-
-  //StrapStatus                               StrapOverride
-  //   bit4                                            bit17
-  //   bit6                                            bit12
-  //   bit12                                           bit15
-  //   bit15                                           bit16
-  //   bit16                                           bit18
-  ReadMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80), AccWidthUint32, &abValue);
-  abValue1 = abValue & (~ (BIT4 + BIT6 + BIT17 + BIT12 + BIT15 + BIT16 + BIT18));
-  if (abValue & BIT4) {
-    abValue1 = (abValue1 & ~BIT4) | BIT17;
-  }
-  if (abValue & BIT6) {
-    abValue1 = (abValue1 & ~BIT6) | BIT12;
-  }
-  if (abValue & BIT12) {
-    abValue1 = (abValue1 & ~BIT12) | BIT15;
-  }
-  if (abValue & BIT15) {
-    abValue1 = (abValue1 & ~BIT15) | BIT16;
-  }
-  if (abValue & BIT16) {
-    abValue1 = (abValue1 & ~BIT16) | BIT18;
-  }
-  abValue1 |= BIT31;             // Overwrite enable
-  if ((dbPortStatus & ChipSysEcEnable) == 0) {
-    abValue1 |= BIT2;            // bit2- EcEnableStrap
-  } else {
-    abValue1 &= ~BIT2;           // bit2=0 EcEnableStrap
-  }
-  WriteMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG84), AccWidthUint32, &abValue1);
-  dbValue |= (BIT6 + BIT7);                                             // PwrGoodOut =1, PwrGoodEnB=1
-  WritePMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);
-
-  dbValue = 06;
-  WriteIO (0xcf9, AccWidthUint8, &dbValue);
-  SbStall (0xffffffff);
-}
-#endif
-
-/**
- * A13ResumeResetTwoSecondRtcWakeup - A13 Resume Reset 2 Seconds
- * RTC Wakeup
- *
- *
- *
- * @retval  Nothing
- *
- */
-VOID
-A13ResumeResetTwoSecondRtcWakeup (
-  void
-  )
-{
-  if ( IsSbA13Plus () ) {
-    //Configure RTC clocks and power failure to "off"
-    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG57) |= 0x03;
-    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG56) |= 0x80;
-    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG56) &= 0x7f;
-    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG5B) = 0x04;
-
-    //set 2 seconds RTC wake up
-    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x00) = 0;
-    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x01) = 2;
-    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x02) = 0;
-    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x03) = 0;
-    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x04) = 0;
-    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x05) = 0;
-    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x0d) = 0x80;
-    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x0b) |= 0x22;
-
-    //Do ResumeReset by SB A13 ECO
-    WriteIo8 (0x80, 0xef);
-    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6) |= 0x40;
-    do {
-      WriteIo8 (0x80, 0xfe);
-    } while ( ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6) );
-  }
-}
-
-/**
- * StressResetModeLate - Stress Reset Mode
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-StressResetModeLate (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  switch ( pConfig->StressResetMode ) {
-  case 1:
-    WriteIo8 ((UINT16) (0x64), 0xFE);
-    break;
-  case 2:
-    WriteIo8 ((UINT16) (0xCF9), 0x06);
-    break;
-  case 3:
-    WriteIo8 ((UINT16) (0xCF9), 0x0E);
-    break;
-  case 4:
-    A13ResumeResetTwoSecondRtcWakeup ();
-    return;
-  default:
-    return;
-  }
-  while (pConfig->StressResetMode) {
-  }
-}
-
-/**
- * CheckEfuse - Check Efuse
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-CheckEfuse (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8     EfuseIndex;
-  UINT8     EfuseFailureCount;
-  pConfig->EfuseRemainder = 0;
-  pConfig->EfuseSum = 0;
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5);
-  for ( EfuseIndex = 0; EfuseIndex < 0x20; EfuseIndex ++ ) {
-    pConfig->EfuseByte [EfuseIndex] = getEfuseByte (EfuseIndex);
-  }
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0);
-  for ( EfuseIndex = 0x10; EfuseIndex < 0x20; EfuseIndex ++ ) {
-    pConfig->EfuseSum = pConfig->EfuseSum + pConfig->EfuseByte [EfuseIndex];
-    pConfig->EfuseRemainder = (((pConfig->EfuseRemainder) << 8) + pConfig->EfuseByte [0x2f - EfuseIndex]) % 0xc1;
-  }
-  pConfig->EfuseSum = (UINT8) (0x100 - pConfig->EfuseSum);
-  if (!(( pConfig->EfuseByte [0x0e] == 0 ) && ( pConfig->EfuseByte [0x0f] == 0 ))) {
-    if (( pConfig->EfuseRemainder != pConfig->EfuseByte [0x0e] ) || ( pConfig->EfuseSum != pConfig->EfuseByte [0x0f])) {
-      EfuseFailureCount = ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D);
-      if ( EfuseFailureCount == 0xff ) {
-        EfuseFailureCount = 0;
-        ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D) = 0;
-      }
-      if ( EfuseFailureCount < 2 ) {
-        EfuseFailureCount++;
-        ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D) = EfuseFailureCount;
-        A13ResumeResetTwoSecondRtcWakeup ();
-      }
-    }
-  }
-}
-
-/**
- * ValidateFchVariant - Validate FCH Variant
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-ValidateFchVariant (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8     XhciEfuse;
-  UINT8     PcieEfuse;
-  UINT8     FchVariantEfuse;
-
-  switch ( pConfig->FchVariant ) {
-  case FCH_M3T:
-    //Disable Devices for M3T
-    pConfig->GecConfig = 1;
-    pConfig->hwm.hwmEnable = 0;
-    pConfig->sdConfig = 0;
-    pConfig->IrConfig = 0;
-//    pConfig->USBMODE.UsbMode.Ohci3 = 0;
-//    pConfig->USBMODE.UsbMode.Ehci3 = 0;
-    break;
-  default:
-    break;
-  }
-
-  // add Efuse checking for Xhci enable/disable
-  XhciEfuse = XHCI_EFUSE_LOCATION;
-  getEfuseStatus (&XhciEfuse);
-  if ((XhciEfuse & (BIT0 + BIT1)) == (BIT0 + BIT1)) {
-    pConfig->XhciSwitch = 0;
-  }
-
-  // add Efuse checking for PCIE Gen2 enable
-  PcieEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
-  getEfuseStatus (&PcieEfuse);
-  if ( PcieEfuse & BIT0 ) {
-    pConfig->NbSbGen2 = 0;
-    pConfig->GppGen2 = 0;
-  }
-
-  FchVariantEfuse = FCH_Variant_EFUSE_LOCATION;
-  getEfuseStatus (&FchVariantEfuse);
-  if ((FchVariantEfuse == 0x07) || (FchVariantEfuse == 0x08)) {
-    pConfig->NbSbGen2 = 0;
-  }
-}
-
-/**
- * Is GCPU?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-BOOLEAN
-IsGCPU (
-  OUT VOID
-  )
-{
-  UINT8 ExtendedFamily;
-  UINT8 ExtendedModel;
-  UINT8 BaseFamily;
-  UINT8 BaseModel;
-  UINT8 Stepping;
-  UINT8 Family;
-  UINT8 Model;
-  SB_CPUID_DATA  CpuId;
-
-  CpuidRead (0x01, &CpuId);
-  ExtendedFamily = (UINT8) ((CpuId.EAX_Reg >> 20) & 0xff);
-  ExtendedModel = (UINT8) ((CpuId.EAX_Reg >> 16) & 0xf);
-  BaseFamily = (UINT8) ((CpuId.EAX_Reg >> 8) & 0xf);
-  BaseModel = (UINT8) ((CpuId.EAX_Reg >> 4) & 0xf);
-  Stepping = (UINT8) ((CpuId.EAX_Reg >> 0) & 0xf);
-  Family = BaseFamily + ExtendedFamily;
-  Model = (ExtendedModel >> 4) + BaseModel;
-  if ( (Family == 0x12) || \
-       (Family == 0x14) || \
-       (Family == 0x16) || \
-       ((Family == 0x15) && ((Model == 0x10) || (Model == 0x30))) ) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-/**
- * Is UMI One Lane GEN1 Mode?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-BOOLEAN
-IsUmiOneLaneGen1Mode (
-  OUT VOID
-  )
-{
-  UINT32   abValue;
-  abValue = readAlink ((UINT32) (SB_AX_CFG_REG68));
-  abValue >>= 16;
-  if (((abValue & 0x0f) == 1) && ((abValue & 0x03f0) == 0x0010)) {
-    return (TRUE);
-  } else {
-    return (FALSE);
-  }
-}
-
-/**
- * Record SMI Status
- *
- *
- * @retval  Nothing
- *
- */
-VOID
-RecordSmiStatus (
-  OUT VOID
-  )
-{
-  UINTN   i;
-  UINT8   SwSmiValue;
-  ACPIMMIO8 (0xfed80320) |= 0x01;
-  for ( i = 0; i < 20; i++ ) {
-    ACPIMMIO8 (0xfed10020 + i) = ACPIMMIO8 (0xfed80280 + i);
-  }
-  SwSmiValue = ReadIo8 (0xb0);
-  ACPIMMIO8 (0xfed10040) = SwSmiValue;
-}
-
diff --git a/src/vendorcode/amd/cimx/sb900/SbDef.h b/src/vendorcode/amd/cimx/sb900/SbDef.h
deleted file mode 100644
index b600627e09..0000000000
--- a/src/vendorcode/amd/cimx/sb900/SbDef.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-
-//AMD Library Routines (AMDLIB.C)
-void  InitSerialOut (void);
-unsigned char getNumberOfCpuCores (OUT void);
-unsigned int  readAlink (IN unsigned int Index);
-void  writeAlink (IN unsigned int Index, IN unsigned int Data);
-void  rwAlink (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
-
-//AMD Library Routines (LEGACY.C)
-unsigned int   GetFixUp (OUT void);
-
-//AMD Library Routines (IOLIB.C)
-void  ReadIO (IN unsigned short  Address, IN unsigned char OpFlag, IN void *Value);
-void  WriteIO (IN unsigned short Address, IN unsigned char OpFlag, IN void *Value);
-void  RWIO (IN unsigned short Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
-
-/// CPUID data received registers format
-typedef struct _SB_CPUID_DATA {
-  IN OUT   unsigned int          EAX_Reg;                ///< CPUID instruction result in EAX
-  IN OUT   unsigned int          EBX_Reg;                ///< CPUID instruction result in EBX
-  IN OUT   unsigned int          ECX_Reg;                ///< CPUID instruction result in ECX
-  IN OUT   unsigned int          EDX_Reg;                ///< CPUID instruction result in EDX
-} SB_CPUID_DATA;
-
-//AMD Library Routines (AMDLIB32.ASM)
-unsigned char ReadIo8 (IN unsigned short Address);
-unsigned short ReadIo16 (IN unsigned short Address);
-unsigned int ReadIo32 (IN unsigned short Address);
-void WriteIo8 (IN unsigned short Address, IN unsigned char Data);
-void WriteIo16 (IN unsigned short Address, IN unsigned short Data);
-void WriteIo32 (IN unsigned short Address, IN unsigned int Data);
-unsigned char ReadNumberOfCpuCores (void);
-unsigned long long  ReadTSC (void);
-void CpuidRead (IN unsigned int CpuidFcnAddress, OUT SB_CPUID_DATA  *Value);
-
-
-//AMD Library Routines (MEMLIB.C)
-void  ReadMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value);
-void  WriteMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value);
-void  RWMEM (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
-void
-MemoryCopy (
-  IN       unsigned char *Dest,
-  IN       unsigned char *Source,
-  IN       unsigned long Size
-  );
-
-//AMD Library Routines (PCILIB.C)
-void  ReadPCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value);
-void  WritePCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value);
-void  RWPCI (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int  Data);
-
-//AMD Library Routines (SBPELIB.C)
-/**
- * Read Southbridge Revision ID cie Base
- *
- *
- * @retval  0xXXXXXXXX   Revision ID
- *
- */
-unsigned char getRevisionID (OUT void);
-
-//AMD Library Routines (SBPELIB.C)
-/**
- * Is SB A11?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-unsigned char IsSbA11 (OUT void);
-
-//AMD Library Routines (SBPELIB.C)
-/**
- * Is SB A12?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-unsigned char IsSbA12 (OUT void);
-
-//AMD Library Routines (SBPELIB.C)
-/**
- * Is SB A12 Plus?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-unsigned char IsSbA12Plus (OUT void);
-
-//AMD Library Routines (SBPELIB.C)
-/**
- * Is SB A13 Plus?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-unsigned char IsSbA13Plus (OUT void);
-
-/**
- * Is LPC Rom?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-unsigned char IsExternalClockMode (OUT void);
-
-/**
- * Is External Clock Mode?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-unsigned char IsLpcRom (OUT void);
-
-/**
- * Is GCPU?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-unsigned char
-IsGCPU (
-  OUT void
-  );
-
-//AMD Library Routines (SBPELIB.C)
-/**
- * Assert/deassert Hudson-2 pins used to toggle SB GPP reset or NB PCIE reset
- *
- *
- * @param[in] ResetBlock - PCIE reset for SB GPP or NB PCIE
- * @param[in] ResetOp    - Assert or deassert PCIE reset
- *
- */
-void SbResetPcie (IN RESET_BLOCK  ResetBlock, IN RESET_OP ResetOp);
-
-/**
- * sbGppTogglePcieReset - Toggle PCIE_RST2#
- *
- *
- * @param[in] pConfig
- *
- */
-void sbGppTogglePcieReset (IN AMDSBCFG* pConfig);
-
-/**
- * sbSpiUnlock - Sb SPI Unlock
- *
- *
- * @param[in] pConfig
- *
- */
-void sbSpiUnlock (IN AMDSBCFG* pConfig);
-
-/**
- * sbSpilock - Sb SPI lock
- *
- *
- * @param[in] pConfig
- *
- */
-void sbSpilock (IN AMDSBCFG* pConfig);
-
-/**
- * programPciByteTable - Program PCI register by table (8 bits data)
- *
- *
- *
- * @param[in] pPciByteTable    - Table data pointer
- * @param[in] dwTableSize      - Table length
- *
- */
-void  programPciByteTable (IN REG8MASK* pPciByteTable, IN unsigned short dwTableSize);
-
-/**
- * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
- *
- *
- *
- * @param[in] pAcpiTbl   - Table data pointer
- *
- */
-void  programSbAcpiMmioTbl (IN AcpiRegWrite  *pAcpiTbl);
-
-/**
- * getChipSysMode - Get Chip status
- *
- *
- * @param[in] Value - Return Chip strap status
- *   StrapStatus [15.0] - Hudson-2 chip Strap Status
- *    @li <b>0001</b> - Not USED FWH
- *    @li <b>0002</b> - Not USED LPC ROM
- *    @li <b>0004</b> - EC enabled
- *    @li <b>0008</b> - Reserved
- *    @li <b>0010</b> - Internal Clock mode
- *
- */
-void getChipSysMode (IN void* Value);
-
-/**
- * isImcEnabled - Is IMC Enabled
- * @retval  TRUE for IMC Enabled; FALSE for IMC Disabled
- */
-unsigned char isImcEnabled (void);
-
-/**
- * Read Southbridge CIMx configuration structure pointer
- *
- *
- *
- * @retval  0xXXXXXXXX   CIMx configuration structure pointer.
- *
- */
-AMDSBCFG* getConfigPointer (OUT void);
-
-//AMD Library Routines (PMIOLIB.C)
-/**
- * Read PMIO
- *
- *
- *
- * @param[in] Address  - PMIO Offset value
- * @param[in] OpFlag   - Access sizes
- * @param[in] Value    - Read Data Buffer
- *
- */
-void  ReadPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
-
-/**
- * Write PMIO
- *
- *
- *
- * @param[in] Address  - PMIO Offset value
- * @param[in] OpFlag   - Access sizes
- * @param[in] Value    - Write Data Buffer
- *
- */
-void  WritePMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
-
-/**
- * RWPMIO - Read/Write PMIO
- *
- *
- *
- * @param[in] Address    - PMIO Offset value
- * @param[in] OpFlag     - Access sizes
- * @param[in] AndMask    - Data And Mask 32 bits
- * @param[in] OrMask     - Data OR Mask 32 bits
- *
- */
-void  RWPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN unsigned int AndMask, IN unsigned int OrMask);
-
-//AMD Library Routines (PMIO2LIB.C)
-
-/**
- * Read PMIO2
- *
- *
- *
- * @param[in] Address  - PMIO2 Offset value
- * @param[in] OpFlag   - Access sizes
- * @param[in] Value    - Read Data Buffer
- *
- */
-void  ReadPMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
-
-/**
- * Write PMIO 2
- *
- *
- *
- * @param[in] Address  - PMIO2 Offset value
- * @param[in] OpFlag   - Access sizes
- * @param[in] Value    - Write Data Buffer
- *
- */
-void  WritePMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
-
-/**
- * RWPMIO2 - Read/Write PMIO2
- *
- *
- *
- * @param[in] Address    - PMIO2 Offset value
- * @param[in] OpFlag     - Access sizes
- * @param[in] AndMask    - Data And Mask 32 bits
- * @param[in] OrMask     - Data OR Mask 32 bits
- *
- */
-void  RWPMIO2 (IN unsigned char Address, IN unsigned char  OpFlag, IN unsigned int AndMask, IN unsigned int OrMask);
-//AMD Library Routines (ECLIB.C)
-// ECLIB Routines
-
-// #ifndef NO_EC_SUPPORT
-
-/**
- * EnterEcConfig - Force EC into Config mode
- *
- *
- *
- *
- */
-void  EnterEcConfig (void);
-
-/**
- * ExitEcConfig - Force EC exit Config mode
- *
- *
- *
- *
- */
-void  ExitEcConfig (void);
-
-/**
- * ReadEC8 - Read EC register data
- *
- *
- *
- * @param[in] Address  - EC Register Offset Value
- * @param[in] Value    - Read Data Buffer
- *
- */
-void  ReadEC8 (IN unsigned char Address, IN unsigned char* Value);
-
-/**
- * WriteEC8 - Write date into EC register
- *
- *
- *
- * @param[in] Address  - EC Register Offset Value
- * @param[in] Value    - Write Data Buffer
- *
- */
-void  WriteEC8 (IN unsigned char Address, IN unsigned char* Value);
-
-/**
- * RWEC8 - Read/Write EC register
- *
- *
- *
- * @param[in] Address    - EC Register Offset Value
- * @param[in] AndMask    - Data And Mask 8 bits
- * @param[in] OrMask     - Data OR Mask 8 bits
- *
- */
-void  RWEC8 (IN unsigned char Address, IN unsigned char AndMask, IN unsigned char OrMask);
-
-unsigned char IsZoneFuncEnable (IN unsigned short Flag, IN unsigned char func, IN unsigned char Zone);
-void sbECfancontrolservice (IN AMDSBCFG* pConfig);
-void hwmImcInit (IN AMDSBCFG* pConfig);
-void GetSbAcpiMmioBase (OUT unsigned int* AcpiMmioBase);
-void GetSbAcpiPmBase (OUT  unsigned short* AcpiPmBase);
-void SetAcpiPma (IN  unsigned char pmaControl);
-void imcEnableSurebootTimer (IN AMDSBCFG* pConfig);
-void imcDisableSurebootTimer (IN AMDSBCFG* pConfig);
-void imcDisarmSurebootTimer (IN AMDSBCFG* pConfig);
-void hwmSbtsiAutoPolling (IN AMDSBCFG* pConfig);
-void hwmSbtsiAutoPollingOff (IN AMDSBCFG* pConfig);
-void hwmSbtsiAutoPollingPause (IN AMDSBCFG* pConfig);
-void imcSleep (IN AMDSBCFG* pConfig);
-void imcWakeup (IN AMDSBCFG* pConfig);
-void imcIdle (IN AMDSBCFG* pConfig);
-void imcThermalZoneEnable (IN AMDSBCFG* pConfig);
-void ValidateFchVariant (IN AMDSBCFG* pConfig);
-void CheckEfuse (IN AMDSBCFG* pConfig);
-
-/**
- * Is UMI One Lane GEN1 Mode?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-unsigned char IsUmiOneLaneGen1Mode ( OUT void );
-
-/**
- * Record SMI Status
- *
- *
- * @retval  Nothing
- *
- */
-void RecordSmiStatus ( OUT void );
-// #endif
-
diff --git a/src/vendorcode/amd/cimx/sb900/SbMain.c b/src/vendorcode/amd/cimx/sb900/SbMain.c
deleted file mode 100644
index dc39a944db..0000000000
--- a/src/vendorcode/amd/cimx/sb900/SbMain.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/**
- * @file
- *
- * SB Initialization.
- *
- * Init IOAPIC/IOMMU/Misc NB features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * sbBeforePciInit - Config Southbridge before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-
-VOID
-sbBeforePciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n"));
-  RecordSbConfigPtr ( (UINT32) ((UINTN) (pConfig)));
-  CheckEfuse (pConfig);
-  ValidateFchVariant (pConfig);
-  imcEnableSurebootTimer (pConfig);
-  commonInitEarlyPost (pConfig);
-  commonInitEarlyBoot (pConfig);
-#ifndef NO_EC_SUPPORT
-  ecInitBeforePciEnum (pConfig);
-#endif
-  usbInitBeforePciEnum (pConfig);                     // USB POST TIME Only
-  sataInitBeforePciEnum (pConfig);                    // Init SATA class code and PHY
-  gecInitBeforePciEnum (pConfig);                     // Init GEC
-  azaliaInitBeforePciEnum (pConfig);                  // Detect and configure High Definition Audio
-  sbPcieGppEarlyInit (pConfig);                       // Gpp port init
-  abSpecialSetBeforePciEnum (pConfig);
-  hwmInit (pConfig);
-  TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n"));
-}
-
-/**
- *  sbAfterPciInit - Config Southbridge after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbAfterPciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
-
-  imcEnableSurebootTimer (pConfig);
-  usbInitAfterPciInit (pConfig);                      // Init USB MMIO
-  sataInitAfterPciEnum (pConfig);                     // SATA port enumeration
-  gecInitAfterPciEnum (pConfig);
-  azaliaInitAfterPciEnum (pConfig);                   // Detect and configure High Definition Audio
-  hwmUpdateData (pConfig);
-  TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
-}
-
-/**
- *  sbMidPostInit - Config Southbridge during middle of POST
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbMidPostInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbMidPostInit \n"));
-  imcEnableSurebootTimer (pConfig);
-  sataInitMidPost (pConfig);
-  TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbMidPostInit \n"));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- *  sbLatePost - Prepare Southbridge to boot to OS.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbLatePost (
-  IN       AMDSBCFG* pConfig
-  )
-{
-// UINT16 dwVar;
-  BUILDPARAM  *pStaticOptions;
-  pStaticOptions = &(pConfig->BuildParameters);
-  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
-  commonInitLateBoot (pConfig);
-  sataInitLatePost (pConfig);
-  gecInitLatePost (pConfig);
-  hpetInit (pConfig, pStaticOptions);                 // SB Configure HPET base and enable bit
-#ifndef NO_EC_SUPPORT
-  ecInitLatePost (pConfig);
-#endif
-  sbPcieGppLateInit (pConfig);
-  hwmImcInit (pConfig);
-//  hwmSbtsiAutoPollingOff (pConfig);
-  imcDisarmSurebootTimer (pConfig);
-  usbInitLate (pConfig);                      // Init USB
-  StressResetModeLate (pConfig);                      //
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-
-VOID
-sbBeforePciRestoreInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n"));
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
-  pConfig->S3Resume = 1;
-  ValidateFchVariant (pConfig);
-  commonInitEarlyBoot (pConfig);                      // set /SMBUS/ACPI/IDE/LPC/PCIB
-  abLinkInitBeforePciEnum (pConfig);                  // Set ABCFG registers
-  usbInitBeforePciEnum (pConfig);                     // USB POST TIME Only
-  sataInitBeforePciEnum (pConfig);
-  gecInitBeforePciEnum (pConfig);                     // Init GEC
-  azaliaInitBeforePciEnum (pConfig);                  // Detect and configure High Definition Audio
-  sbPcieGppEarlyInit (pConfig);                       // Gpp port init
-  abSpecialSetBeforePciEnum (pConfig);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-
-VOID
-sbAfterPciRestoreInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  BUILDPARAM  *pStaticOptions;
-
-  pConfig->S3Resume = 1;
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
-  pStaticOptions = &(pConfig->BuildParameters);
-  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
-  commonInitLateBoot (pConfig);
-  sataInitAfterPciEnum (pConfig);
-  gecInitAfterPciEnum (pConfig);
-  azaliaInitAfterPciEnum (pConfig);          // Detect and configure High Definition Audio
-  hpetInit (pConfig, pStaticOptions);        // SB Configure HPET base and enable bit
-  sataInitLatePost (pConfig);
-  c3PopupSetting (pConfig);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
-  hwmInit (pConfig);
-  hwmImcInit (pConfig);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * sbSmmAcpiOn - Config Southbridge during ACPI_ON
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbSmmAcpiOn (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest
-  // recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows
-  AMDSBCFG*   pTmp;      //lx-dummy for /W4 build
-  pTmp = pConfig;
-
-  // Disable Power Button SMI
-  RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6), 0);
-  // USB workaroud
-  // x00[0] = 1;
-  // x04[31] = 0, x04[0] = 1;
-  // x08[31] = 0, x08[7] = 0;
-  // x0C[31] = 0, x0C[7] = 0,
-  // x10[31] = 0, x10[0] = 1;
-  // x14[31] = 0, x14[0] = 1;
-  // x18[31] = 0, x18[7] = 0;
-  // x1C[31] = 0,
-  // x20[31] = 0,
-  //RWMEM (0x00, AccWidthUint32, 0, BIT0);
-  //RWMEM (0x04, AccWidthUint32, 0, BIT0);
-  //RWMEM (0x08, AccWidthUint32, 0, 0);
-  //RWMEM (0x0C, AccWidthUint32, 0, 0);
-  //RWMEM (0x10, AccWidthUint32, 0, BIT0);
-  //RWMEM (0x14, AccWidthUint32, 0, BIT0);
-  //RWMEM (0x18, AccWidthUint32, 0, 0);
-  //RWMEM (0x1C, AccWidthUint32, 0, 0);
-  //RWMEM (0x20, AccWidthUint32, 0, 0);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Call Back routine.
- *
- *
- *
- * @param[in] Func    Callback ID.
- * @param[in] Data    Callback specific data.
- * @param[in] pConfig Southbridge configuration structure pointer.
- */
-UINTN
-CallBackToOEM (
-  IN       UINT32 Func,
-  IN       UINTN  Data,
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32 Result;
-  Result = 0;
-  if ( pConfig->StdHeader.CALLBACK.CalloutPtr == NULL ) return Result;
-  TRACE ((DMSG_SB_TRACE, "Calling %lx ( % x, % x, % x)\n", pConfig->StdHeader.CalloutPtr, Func, Data, pConfig));
-  Result = (*(SBCIM_HOOK_ENTRY*) (UINTN)&pConfig->StdHeader.CALLBACK.CalloutPtr) ( Func, Data, pConfig);
-
-  TRACE ((DMSG_SB_TRACE, "SB Hook Status [ % x]\n", Result));
-  return Result;
-}
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/SbModInf.c b/src/vendorcode/amd/cimx/sb900/SbModInf.c
deleted file mode 100644
index 1fb6fd7547..0000000000
--- a/src/vendorcode/amd/cimx/sb900/SbModInf.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/**
- * @file
- *
- *  Function dispatcher.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*     * Redistributions of source code must retain the above copyright
-*       notice, this list of conditions and the following disclaimer.
-*     * Redistributions in binary form must reproduce the above copyright
-*       notice, this list of conditions and the following disclaimer in the
-*       documentation and/or other materials provided with the distribution.
-*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-*       its contributors may be used to endorse or promote products derived
-*       from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-* ***************************************************************************
-*
-*/
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/// module header
-VOLATILE AMD_MODULE_HEADER mNbModuleHeader = {
-  'DOM$',                        ///< Standard AMD module signature
-  CIMX_SB_ID,                    ///< Chipset ID
-  CIMX_SB_REVISION,              ///< CIMx version
-  AmdSbDispatcher,               ///< Pointer to the module entry
-  NULL                           ///< Pointer link to next module header
-};
diff --git a/src/vendorcode/amd/cimx/sb900/SbPeLib.c b/src/vendorcode/amd/cimx/sb900/SbPeLib.c
deleted file mode 100644
index ee6eba915e..0000000000
--- a/src/vendorcode/amd/cimx/sb900/SbPeLib.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/**
- * @file
- *
- * Southbridge IO access common routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-
-/**
- * Read Southbridge Revision ID cie Base
- *
- *
- * @retval  0xXXXXXXXX   Revision ID
- *
- */
-UINT8
-getRevisionID (
-  OUT VOID
-  )
-{
-  UINT8  dbVar0;
-  ReadPCI (((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08), AccWidthUint8, &dbVar0);
-  return dbVar0;
-}
-
-/**
- * Is SB A11?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-BOOLEAN
-IsSbA11 (
-  OUT VOID
-  )
-{
-  return ( getRevisionID () == AMD_SB_A11 );
-}
-
-/**
- * Is SB A12?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-BOOLEAN
-IsSbA12 (
-  OUT VOID
-  )
-{
-  return ( getRevisionID () == AMD_SB_A12 );
-}
-
-/**
- * Is SB A12 Plus?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-BOOLEAN
-IsSbA12Plus (
-  OUT VOID
-  )
-{
-  return ( getRevisionID () >= AMD_SB_A12 );
-}
-
-/**
- * Is SB A13 Plus?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-BOOLEAN
-IsSbA13Plus (
-  OUT VOID
-  )
-{
-  return ( getRevisionID () >= AMD_SB_A13 );
-}
-
-/**
- * Is External Clock Mode?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-BOOLEAN
-IsExternalClockMode (
-  OUT VOID
-  )
-{
-  return ( (BOOLEAN) ((ACPIMMIO32 (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80) & BIT4) == 0) );
-}
-
-/**
- * Is LPC Rom?
- *
- *
- * @retval  TRUE or FALSE
- *
- */
-BOOLEAN
-IsLpcRom (
-  OUT VOID
-  )
-{
-  return ( (BOOLEAN) ((ACPIMMIO32 (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80) & BIT1) == 0) );
-}
-
-/**
- * Memory Copy
- *
- *
- * @retval  VOID
- *
- */
-VOID
-MemoryCopy (
-  IN       UINT8 *Dest,
-  IN       UINT8 *Source,
-  IN       UINTN Size
-  )
-{
-  UINTN i;
-  for ( i = 0; i < Size; i++  ) {
-    *Dest = *Source;
-    Dest++;
-    Source++;
-  }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * programPciByteTable - Program PCI register by table (8 bits data)
- *
- *
- *
- * @param[in] pPciByteTable    - Table data pointer
- * @param[in] dwTableSize      - Table length
- *
- */
-VOID
-programPciByteTable (
-  IN       REG8MASK* pPciByteTable,
-  IN       UINT16 dwTableSize
-  )
-{
-  UINT8  i;
-  UINT8  dbBusNo;
-  UINT8  dbDevFnNo;
-  UINT32  ddBDFR;
-
-  dbBusNo = pPciByteTable->bRegIndex;
-  dbDevFnNo = pPciByteTable->bANDMask;
-  pPciByteTable++;
-
-  for ( i = 1; i < dwTableSize; i++ ) {
-    if ( (pPciByteTable->bRegIndex == 0xFF) && (pPciByteTable->bANDMask == 0xFF) && (pPciByteTable->bORMask == 0xFF) ) {
-      pPciByteTable++;
-      dbBusNo = pPciByteTable->bRegIndex;
-      dbDevFnNo = pPciByteTable->bANDMask;
-      pPciByteTable++;
-      i++;
-    } else {
-      ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ;
-      TRACE ((DMSG_SB_TRACE, "PFA = %X  AND = %X, OR = %X", ddBDFR, pPciByteTable->bANDMask, pPciByteTable->bORMask));
-      RWPCI (ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask);
-      pPciByteTable++;
-    }
-  }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
- *
- *
- *
- * @param[in] pAcpiTbl   - Table data pointer
- *
- */
-VOID
-programSbAcpiMmioTbl (
-  IN       AcpiRegWrite *pAcpiTbl
-  )
-{
-  UINT8 i;
-  UINT32 ddtempVar;
-  if (pAcpiTbl != NULL) {
-    if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataANDMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) {
-      // Signature Checking
-      pAcpiTbl++;
-      for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) {
-        ddtempVar = 0xFED80000 | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
-        RWMEM (ddtempVar, AccWidthUint8, ((pAcpiTbl->DataANDMask) | 0xFFFFFF00), pAcpiTbl->DataOrMask);
-        pAcpiTbl++;
-      }
-    }
-  }
-}
-
-/**
- * getChipSysMode - Get Chip status
- *
- *
- * @param[in] Value - Return Chip strap status
- *   StrapStatus [15.0] - Hudson-2 chip Strap Status
- *    @li <b>0001</b> - Not USED FWH
- *    @li <b>0002</b> - Not USED LPC ROM
- *    @li <b>0004</b> - EC enabled
- *    @li <b>0008</b> - Reserved
- *    @li <b>0010</b> - Internal Clock mode
- *
- */
-VOID
-getChipSysMode (
-  IN       VOID* Value
-  )
-{
-  ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value);
-}
-
-/**
- * isImcEnabled - Is IMC Enabled
- * @retval  TRUE for IMC Enabled; FALSE for IMC Disabled
- */
-BOOLEAN
-isImcEnabled (
-  )
-{
-  UINT8   dbSysConfig;
-  getChipSysMode (&dbSysConfig);
-  if (dbSysConfig & ChipSysEcEnable) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read Southbridge CIMx configuration structure pointer
- *
- *
- *
- * @retval  0xXXXXXXXX   CIMx configuration structure pointer.
- *
- */
-AMDSBCFG*
-getConfigPointer (
-  OUT VOID
-  )
-{
-  UINT8  dbReg;
-  UINT8  dbValue;
-  UINT8  i;
-  UINT32  ddValue;
-  ddValue = 0;
-  dbReg = SB_ECMOS_REG08;
-
-  for ( i = 0; i <= 3; i++ ) {
-    WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
-    ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue);
-    ddValue |= (dbValue << (i * 8));
-    dbReg++;
-  }
-  return ( (AMDSBCFG*) (UINTN)ddValue);
-}
-
-/**
- * getEfuseStatue - Get Efuse status
- *
- *
- * @param[in] Value - Return Chip strap status
- *
- */
-VOID
-getEfuseStatus (
-  IN       VOID* Value
-  )
-{
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5);
-  WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value);
-  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0);
-}
-
-/**
- * getEfuseByte - Get Efuse Byte
- *
- *
- * @param[in] Index - Efuse Index value
- *
- */
-UINT8
-getEfuseByte (
-  IN       UINT8 Index
-  )
-{
-  UINT8 Data;
-  WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, &Index);
-  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, &Data);
-  return Data;
-}
-
-
-/**
- * SbResetGppDevice - Toggle GEVENT4 to assert/deassert GPP device reset
- *
- *
- * @param[in] ResetBlock - PCIE reset for SB GPP or NB PCIE
- * @param[in] ResetOp    - Assert or deassert PCIE reset
- *
- */
-VOID
-SbResetPcie (
-  IN       RESET_BLOCK  ResetBlock,
-  IN       RESET_OP     ResetOp
-  )
-{
-
-  if (ResetBlock == NbBlock) {
-    if (ResetOp == AssertReset) {
-      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFF, BIT4);
-    } else if (ResetOp == DeassertReset) {
-      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, ~BIT4, 0);
-    }
-  } else if (ResetBlock == SbBlock) {
-    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG04, AccWidthUint8, ~(BIT1 + BIT0), 0x02);
-    if (ResetOp == AssertReset) {
-      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GEVENT_REG04, AccWidthUint8, ~BIT5, 0);
-      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBF, AccWidthUint8, 0xFF, BIT4);
-    } else if (ResetOp == DeassertReset) {
-      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBF, AccWidthUint8, ~BIT4, 0);
-      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GEVENT_REG04, AccWidthUint8, 0xff, BIT5);
-    }
-  }
-}
-
-
-/**
- * sbGppTogglePcieReset - Toggle PCIE_RST2#
- *
- *
- * @param[in] pConfig
- *
- */
-VOID
-sbGppTogglePcieReset (
-  IN     AMDSBCFG*   pConfig
-  )
-{
-  if (pConfig->GppToggleReset) {
-    SbResetPcie (SbBlock, AssertReset);
-    SbStall (500);
-    SbResetPcie (SbBlock, DeassertReset);
-  }
-}
-
-/**
- * sbSpiUnlock - Sb SPI Unlock
- *
- *
- * @param[in] pConfig
- *
- */
-VOID
-sbSpiUnlock (
-  IN     AMDSBCFG*   pConfig
-  )
-{
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG50, AccWidthUint32, ~(BIT0 + BIT1), 0);
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG54, AccWidthUint32, ~(BIT0 + BIT1), 0);
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG58, AccWidthUint32, ~(BIT0 + BIT1), 0);
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG5C, AccWidthUint32, ~(BIT0 + BIT1), 0);
-  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32, ~(BIT22 + BIT23), (BIT22 + BIT23));
-}
-
-/**
- * sbSpilock - Sb SPI lock
- *
- *
- * @param[in] pConfig
- *
- */
-VOID
-sbSpilock (
-  IN     AMDSBCFG*   pConfig
-  )
-{
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG50, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG54, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG58, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
-  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG5C, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
-  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32, ~(BIT22 + BIT23), 0);
-}
-
-/**
- * TurnOffCG2
- *
- *
- * @retval  VOID
- *
- */
-VOID
-TurnOffCG2 (
-  OUT VOID
-  )
-{
-  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccWidthUint8, ~BIT6, 0);
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0x0F, 0xA0);
-  RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + 0x41, AccWidthUint8, ~(BIT1 + BIT0), (BIT1 + BIT0));
-  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccWidthUint8, ~( BIT4), (BIT4));
-  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccWidthUint8, ~(BIT6), (BIT6));
-  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccWidthUint8, ~BIT6, BIT6);
-  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccWidthUint8, ~BIT6, BIT6);
-}
-
-/**
- * BackUpCG2
- *
- *
- * @retval  VOID
- *
- */
-VOID
-BackUpCG2 (
-  OUT VOID
-  )
-{
-  UINT8 dByte;
-  ReadMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccWidthUint8, &dByte);
-  if (dByte & BIT6) {
-    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccWidthUint8, ~(BIT6), (0));
-  }
-}
diff --git a/src/vendorcode/amd/cimx/sb900/SbSubFun.h b/src/vendorcode/amd/cimx/sb900/SbSubFun.h
deleted file mode 100644
index 41ce7b7a9a..0000000000
--- a/src/vendorcode/amd/cimx/sb900/SbSubFun.h
+++ /dev/null
@@ -1,609 +0,0 @@
-/**
- * @file
- *
- * Southbridge CIMx Function Support Define (All)
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "cbtypes.h"
-// Southbridge SBMAIN Routines
-
-/**
- * Southbridge Main Function Public Function
- *
- */
-
-/**
- * sbBeforePciInit - Config Southbridge before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbBeforePciInit (IN AMDSBCFG* pConfig);
-
-
-/**
- * sbAfterPciInit - Config Southbridge after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbAfterPciInit (IN AMDSBCFG* pConfig);
-
-/**
- *  sbMidPostInit - Config Southbridge during middle of POST
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbMidPostInit (IN AMDSBCFG* pConfig);
-
-/**
- *  sbLatePost - Prepare Southbridge to boot to OS.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbLatePost (IN AMDSBCFG* pConfig);
-
-/**
- * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbBeforePciRestoreInit (IN AMDSBCFG* pConfig);
-
-/**
- * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbAfterPciRestoreInit (IN AMDSBCFG* pConfig);
-
-/**
- * sbSmmAcpiOn - Config Southbridge during ACPI_ON
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbSmmAcpiOn (IN AMDSBCFG* pConfig);
-
-/**
- * CallBackToOEM - Call Back routine.
- *
- *
- *
- * @param[in] Func    Callback ID.
- * @param[in] Data    Callback specific data.
- * @param[in] pConfig Southbridge configuration structure pointer.
- */
-UINTN CallBackToOEM (IN unsigned int Func, IN UINTN Data, IN AMDSBCFG* pConfig);
-
-
-// Southbridge SBPOR Routines
-
-/**
- * Southbridge power-on initial Public Function
- *
- */
-
-/**
- * sbPowerOnInit - Config Southbridge during power on stage.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbPowerOnInit (IN AMDSBCFG* pConfig);
-
-/**
- * XhciEarlyInit - XhciEarlyInit.
- *
- *
- *
- *
- *
- */
-void XhciEarlyInit (void);
-
-/**
- * XhciInitIndirectReg - XhciInitIndirectReg.
- *
- *
- *
- *
- *
- */
-void XhciInitIndirectReg (void);
-
-
-// Southbridge Common Routines
-
-/**
- * Southbridge Common Public Function
- *
- */
-
-/**
- * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
- *
- *    This settings should be done during S3 resume also
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void commonInitEarlyBoot (IN AMDSBCFG* pConfig);
-
-/**
- * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
- *
- *    This settings might not program during S3 resume
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void commonInitEarlyPost (IN AMDSBCFG* pConfig);
-
-/**
- * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void commonInitLateBoot (IN AMDSBCFG* pConfig);
-
-/**
- * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void abSpecialSetBeforePciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * hpetInit - Program Southbridge HPET function
- *
- *  ** Eric
- *
- * @param[in] pConfig         Southbridge configuration structure pointer.
- * @param[in] pStaticOptions  Platform build configuration table.
- *
- */
-void hpetInit (IN AMDSBCFG* pConfig, IN BUILDPARAM *pStaticOptions);
-
-/**
- * c3PopupSetting - Program Southbridge C state function
- *
- *  ** Eric
- *
- * @param[in] pConfig   Southbridge configuration structure pointer.
- *
- */
-void c3PopupSetting (IN AMDSBCFG* pConfig);
-
-/**
- * GcpuRelatedSetting - Program GCPU C related function
- *
- *
- *
- * @param[in] pConfig   Southbridge configuration structure pointer.
- *
- */
-void GcpuRelatedSetting (IN AMDSBCFG* pConfig);
-
-/**
- * MtC1eEnable - Program Mt C1E Enable Function
- *
- *
- *
- * @param[in] pConfig   Southbridge configuration structure pointer.
- *
- */
-void MtC1eEnable (IN AMDSBCFG* pConfig);
-
-/**
- * Southbridge Common Private Function
- *
- */
-
-/**
- * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void abLinkInitBeforePciEnum (IN AMDSBCFG* pConfig);
-
-// Southbridge SATA Routines
-
-/**
- * Southbridge SATA Controller Public Function
- *
- */
-
-/**
- * sataInitMidPost - Config SATA controller in Middle POST.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sataInitMidPost (IN AMDSBCFG* pConfig);
-
-/**
- * sataInitAfterPciEnum - Config SATA controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void  sataInitAfterPciEnum (IN AMDSBCFG*   pConfig);
-
-/**
- * sataInitBeforePciEnum - Config SATA controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void  sataInitBeforePciEnum (IN AMDSBCFG*  pConfig);
-
-/**
- * sataInitLatePost - Prepare SATA controller to boot to OS.
- *
- *              - Set class ID to AHCI (if set to AHCI * Mode)
- *              - Enable AHCI interrupt
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void  sataInitLatePost (IN AMDSBCFG* pConfig);
-
-// Southbridge GEC Routines
-
-/**
- * Southbridge GEC Controller Public Function
- *
- */
-
-/**
- * gecInitBeforePciEnum - Config GEC controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void gecInitBeforePciEnum (IN AMDSBCFG*   pConfig);
-
-/**
- * gecInitAfterPciEnum - Config GEC controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void gecInitAfterPciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * gecInitLatePost - Prepare GEC controller to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void gecInitLatePost (IN AMDSBCFG* pConfig);
-
-// Southbridge USB Routines
-
-/**
- * Southbridge USB Controller Public Function
- *
- */
-
-/**
- * Config USB controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void usbInitBeforePciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * Config USB controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void usbInitAfterPciInit (IN AMDSBCFG* pConfig);
-
-/**
- * Config USB controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void usbInitLate (IN AMDSBCFG* pConfig);
-
-/**
- * Config USB1 EHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void usb1EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb2EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb3EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb1OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb2OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb3OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb4OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-
-// Southbridge SMI Service Routines (SMM.C)
-
-/**
- * Southbridge SMI Service Routines Public Function
- *
- */
-
-/**
- * Southbridge SMI service module
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbSmmService (IN AMDSBCFG* pConfig);
-
-/**
- * softwareSMIservice - Software SMI service
- *
- *  ** Eric
- *
- * @param[in] VOID Southbridge software SMI service ID.
- *
- */
-void softwareSMIservice (IN void);
-
-// Southbridge GPP Controller Routines
-
-/**
- * Southbridge GPP Controller Routines Public Function
- *
- */
-
-/**
- * GPP early programming and link training. On exit all populated EPs should be fully operational.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbPcieGppEarlyInit (IN AMDSBCFG* pConfig);
-
-/**
- * sbPcieGppLateInit - Late PCIE initialization for Hudson-2 GPP component
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbPcieGppLateInit (IN AMDSBCFG* pConfig);
-
-// Southbridge HD Controller Routines (AZALIA.C)
-
-/**
- * Southbridge HD Controller Routines (AZALIA.C) Public Function
- *
- */
-
-/**
- * Config HD Audio Before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void azaliaInitBeforePciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * Config HD Audio after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig);
-
-
-// Southbridge EC Routines
-
-#ifndef NO_EC_SUPPORT
-/**
- * Southbridge EC Controller Public Function
- *
- */
-
-/**
- * Config EC controller during power-on
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-  void  ecPowerOnInit (IN AMDSBCFG* pConfig);
-
-/**
- * Config EC controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-  void  ecInitBeforePciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * Prepare EC controller to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-  void  ecInitLatePost (IN AMDSBCFG* pConfig);
-
-/**
- * validateImcFirmware - Validate IMC Firmware.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- * @retval        TRUE   Pass
- * @retval        FALSE     Failed
- */
-  unsigned char  validateImcFirmware (IN AMDSBCFG* pConfig);
-
-/**
- * validateImcFirmware - Validate IMC Firmware.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-  void  softwareToggleImcStrapping (IN AMDSBCFG* pConfig);
-#endif
-
-#ifndef NO_HWM_SUPPORT
-/**
- * hwmInit - Init Hardware Monitor.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-  void  hwmInit (IN AMDSBCFG* pConfig);
-/**
- * hwmUpdateData - Hardware Monitor Update Data.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-  void  hwmUpdateData (IN AMDSBCFG* pConfig);
-/**
- * hwmUpdateData - Hardware Monitor Update Data.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-  void  hwmCopyFanControl (IN AMDSBCFG* pConfig);
-/**
- * hwmCopyFanControl - Copy Hardware Monitor Update Data.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-#endif
-/**
- * Stress Reset Mode Late
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void StressResetModeLate (IN AMDSBCFG* pConfig);
-
-/**
- * TurnOffCG2
- *
- *
- * @retval  VOID
- *
- */
-void TurnOffCG2 (OUT void);
-
-/**
- * BackUpCG2
- *
- *
- * @retval  VOID
- *
- */
-void BackUpCG2 (OUT void);
-
-void XhciA12Fix (OUT void);
diff --git a/src/vendorcode/amd/cimx/sb900/SbType.h b/src/vendorcode/amd/cimx/sb900/SbType.h
deleted file mode 100644
index eeedbba5d8..0000000000
--- a/src/vendorcode/amd/cimx/sb900/SbType.h
+++ /dev/null
@@ -1,1389 +0,0 @@
-
-/**
- * @file
- *
- * Southbridge CIMx configuration structure define
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#ifndef _AMD_SBTYPE_H_
-#define _AMD_SBTYPE_H_
-
-#ifndef  LEGACY_BIOS_SUPPORT
-  #pragma pack (push, 1)
-#endif
-/**
- * Entry point of Southbridge CIMx
- *
- *
- * @param[in] Param1  Southbridge CIMx Function ID.
- * @param[in] Param2  Southbridge Input Data.
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-typedef unsigned int (*SBCIM_HOOK_ENTRY) (unsigned int Param1, unsigned int Param2, void* pConfig);
-/**
- * SMM_SERVICE_ROUTINE - Southbridge SMI service routine
- *
- */
-typedef  void (*SMM_SERVICE_ROUTINE) (void);
-
-
-/**
- * The STATIC platform information for CIMx Module.
- *
- */
-typedef struct _BUILDPARAM {
-  unsigned char   BiosSize;           /**< BiosSize 00-00-01
-                                   *   @par
-                                   *   BIOSSize [2.0] - BIOS Image Size
-                                   *    @li <b>0</b> - 1M
-                                   *    @li <b>1</b> - 2M
-                                   *    @li <b>3</b> - 4M
-                                   *    @li <b>7</b> - 8M
-                                   *  In Hudson-2, default ROM size is 1M Bytes, if your platform ROM bigger then 1M
-                                   *  you have to set the ROM size outside CIMx module and before AGESA module get call
-                                   *
-                                   */
-  unsigned char   LegacyFree;         /**< LegacyFree 00-00-02
-                                   *   @par
-                                   * Config Southbridge CIMx module for Legacy Free Mode
-                                   */
-  unsigned char   SpiSpeed;           /**< SpiSpeed  00-00-03
-                                   *   @par
-                                   *    SPI Speed [1.0] - the clock speed for non-fast read command
-                                   *    @li <b>000</b> - Default
-                                   *    @li <b>001</b> - 66Mhz
-                                   *    @li <b>010</b> - 33Mhz
-                                   *    @li <b>011</b> - 22Mhz
-                                   *    @li <b>100</b> - 16.5Mhz
-                                   *
-                                   */
-  unsigned char   ImcEnableOverWrite; /**< ImcEnableOverWrite  00-00-04
-                                   *   @par
-                                   *    Imc Enable OverWrite
-                                   *    @li <b>00</b> - by default strapping
-                                   *    @li <b>01</b> - On
-                                   *    @li <b>10</b> - Off
-                                   *
-                                   */
-  unsigned char   SpiFastSpeed;   /**< SpiFastSpeed  00-00-05
-                                   *   @par
-                                   *    SPI Speed [1.0] - the clock speed for fast read command
-                                   *    @li <b>000</b> - Default
-                                   *    @li <b>001</b> - 66Mhz
-                                   *    @li <b>010</b> - 33Mhz
-                                   *    @li <b>011</b> - 22Mhz
-                                   *    @li <b>100</b> - 16.5Mhz
-                                   *
-                                   */
-  unsigned char   SpiMode;   /**< SpiMode  00-00-06
-                                   *   @par
-                                   *     @li <b>000</b> - Default
-                                   *     @li <b>101</b> - Qual-io 1-4-4
-                                   *     @li <b>100</b> - Dual-io 1-2-2
-                                   *     @li <b>011</b> - Qual-io 1-1-4
-                                   *     @li <b>010</b> - Dual-io 1-1-2
-                                   *     @li <b>111</b> - FastRead
-                                   *     @li <b>110</b> - Normal
-                                   */
-  unsigned char   SpiAutoMode; /**< SpiAutoMode  00-00-07
-                                   *   @par
-                                   *    SPI Auto Mode
-                                   *    @li <b>0</b> - Disabled
-                                   *    @li <b>1</b> - Enabled
-                                   */
-/** SpiBurstWrite - Reserved  00-00-08 */
-  unsigned char   SpiBurstWrite;
-  unsigned char   EcKbd;              /**< EcKbd  00-00-09
-                                   *   @par
-                                   *   EcKbd [16] - Platform use EC (as SIO) or SIO chip for PS/2 Keyboard and Mouse
-                                   *    @li <b>0</b> - Use SIO PS/2 function.
-                                   *    @li <b>1</b> - Use EC PS/2 function instead of SIO PS/2 function. **
-                                   *    @li <b>**</b> When set 1, EC function have to enable, otherwise, CIMx treat as legacy-free system.
-                                   */
-/** EcChannel0 - Reserved  00-00-10 */
-  unsigned char   EcChannel0;
-/** UsbMsi - Reserved  00-00-11*/
-  unsigned char   UsbMsi;
-/** HdAudioMsi - Reserved  00-00-12*/
-  unsigned char   HdAudioMsi;
-/** LpcMsi - Reserved  00-00-13*/
-  unsigned char   LpcMsi;
-/** PcibMsi - Reserved  00-00-14*/
-  unsigned char   PcibMsi;
-/** AbMsi - Reserved  00-00-15*/
-  unsigned char   AbMsi;
-  unsigned char   SpiWriteSpeed;   /**< SpiReadSpeed  00-00-16
-                                   *   @par
-                                   *     TBD
-                                   */
-
-  unsigned int   Smbus0BaseAddress;    /**< Smbus0BaseAddress  00-00-17
-                                   *   @par
-                                   * Smbus BASE Address
-                                   */
-  unsigned int   Smbus1BaseAddress;    /**< Smbus1BaseAddress  00-00-18
-                                   *   @par
-                                   * Smbus1 (ASF) BASE Address
-                                   */
-  unsigned int   SioPmeBaseAddress;    /**< SioPmeBaseAddress  00-00-19
-                                   *   @par
-                                   * SIO PME BASE Address
-                                   */
-  unsigned int   WatchDogTimerBase;    /**< WatchDogTimerBase  00-00-20
-                                   *   @par
-                                   *  Watch Dog Timer Address
-                                   */
-  unsigned int   GecShadowRomBase;     /**< GecShadowRomBase  00-00-21
-                                   *   @par
-                                   * GEC (NIC) SHADOWROM BASE Address
-                                   */
-  unsigned int   SpiRomBaseAddress;    /**< SpiRomBaseAddress  00-00-22
-                                   *   @par
-                                   * SPI ROM BASE Address
-                                   */
-  unsigned short   AcpiPm1EvtBlkAddr;    /**< AcpiPm1EvtBlkAddr  00-00-23
-                                   *   @par
-                                   * ACPI PM1 event block Address
-                                   */
-  unsigned short   AcpiPm1CntBlkAddr;    /**< AcpiPm1CntBlkAddr  00-00-24
-                                   *   @par
-                                   * ACPI PM1 Control block Address
-                                   */
-  unsigned short   AcpiPmTmrBlkAddr;     /**< AcpiPmTmrBlkAddr  00-00-25
-                                   *   @par
-                                   * ACPI PM timer block Address
-                                   */
-  unsigned short   CpuControlBlkAddr;    /**< CpuControlBlkAddr  00-00-26
-                                   *   @par
-                                   * ACPI CPU control block Address
-                                   */
-  unsigned short   AcpiGpe0BlkAddr;      /**< AcpiGpe0BlkAddr  00-00-27
-                                   *   @par
-                                   * ACPI GPE0 block Address
-                                   */
-  unsigned short   SmiCmdPortAddr;       /**< SmiCmdPortAddr  00-00-28
-                                   *   @par
-                                   * SMI command port Address
-                                   */
-  unsigned short   AcpiPmaCntBlkAddr;    /**< AcpiPmaCntBlkAddr  00-00-29
-                                   *   @par
-                                   * ACPI PMA Control block Address
-                                   */
-  unsigned int   HpetBase;             /**< HpetBase  00-00-30
-                                   *   @par
-                                   * HPET Base address
-                                   */
-  unsigned int   SataIDESsid;          /**< SataIDESsid  00-00-31
-                                   *   @par
-                                   * SATA IDE mode SSID
-                                   */
-  unsigned int   SataRAIDSsid;         /**< SataRAIDSsid  00-00-32
-                                   *   @par
-                                   *  SATA RAID mode SSID
-                                   */
-  unsigned int   SataRAID5Ssid;        /**< SataRAID5Ssid  00-00-33
-                                   *   @par
-                                   * SATA RAID5 mode SSID
-                                   */
-  unsigned int   SataAHCISsid;         /**< SataAHCISsid  00-00-34
-                                   *   @par
-                                   * SATA AHCI mode SSID
-                                   */
-  unsigned int   OhciSsid;             /**< OhciSsid  00-00-35
-                                   *   @par
-                                   * OHCI Controller SSID
-                                   */
-  unsigned int   EhciSsid;             /**< EhciSsid  00-00-36
-                                   *   @par
-                                   * EHCI Controller SSID
-                                   */
-  unsigned int   Ohci4Ssid;            /**< Ohci4Ssid  00-00-37
-                                   *   @par
-                                   * OHCI4 Controller SSID (Force USB 1.1 mode)
-                                   */
-  unsigned int   SmbusSsid;            /**< SmbusSsid  00-00-38
-                                   *   @par
-                                   *  SMBUS controller SSID
-                                   */
-  unsigned int   IdeSsid;              /**< IdeSsid  00-00-39
-                                   *   @par
-                                   * IDE (Sata) controller SSID
-                                   */
-  unsigned int   AzaliaSsid;           /**< AzaliaSsid  00-00-40
-                                   *   @par
-                                   * HD Audio controller SSID
-                                   */
-  unsigned int   LpcSsid;              /**< LpcSsid  00-00-41
-                                   *   @par
-                                   * LPC controller SSID
-                                   */
-  unsigned int   PCIBSsid;             /**< PCIBSsid  00-00-42
-                                   *   @par
-                                   * PCIB controller SSID
-                                   */
-} BUILDPARAM;
-
-/**
- * The Hwm temprature parameter  for CIMx Module. *
- */
-typedef struct _HWM_temp_par_struct {
-  unsigned short At;            ///< At
-  unsigned short Ct;          ///< Ct
-  unsigned char Mode;             ///< Mode BIT0:HiRatio BIT1:HiCurrent
-} HWM_temp_par_struct;
-
-/**
- * The Hwm current struct  for CIMx Module. *
- */
-typedef struct _HWM_cur_struct {
-  unsigned short fanSpeed[5];            ///< fanSpeed
-  unsigned short temperature[5];          ///< temperature
-  unsigned short voltage[8];             ///< voltage
-} HWM_cur_struct;
-
-/**
- * The Hwm control struct  for CIMx Module.
- *
- */
-typedef struct _HWM_fan_ctl_struct {
-  unsigned char InputControl_reg00;       ///< InputControl_reg00
-  unsigned char Control_reg01;            ///< Control_reg01
-  unsigned char Freq_reg02;               ///< Freq_reg02
-  unsigned char LowDuty_reg03;            ///< LowDuty_reg03
-  unsigned char MedDuty_reg04;            ///< MedDuty_reg04
-  unsigned char Multiplier_reg05;         ///< Multiplier_reg05
-  unsigned short LowTemp_reg06;           ///< LowTemp_reg06
-  unsigned short MedTemp_reg08;           ///< MedTemp_reg08
-  unsigned short HighTemp_reg0A;          ///< HighTemp_reg0A
-  unsigned char LinearRange_reg0C;        ///< LinearRange_reg0C
-  unsigned char LinearHoldCount_reg0D;    ///< LinearHoldCount_reg0D
-} HWM_fan_ctl_struct;
-
-/**
- * The Hwm struct  for CIMx Module. *
- */
-typedef struct _HWM_struct {
-  unsigned char hwmEnable;            ///< hwmEnable
-  unsigned int hwmControl;                    /**< hwmControl
-                                        *   @par
-                                        * HWM control configuration
-                                        *    @li <b>0</b> - HWM is Enabled
-                                        *    @li <b>1</b> - IMC is Enabled
-                                        */
-  unsigned char fanSampleFreqDiv;            ///< fanSampleFreqDiv
-  unsigned char hwmSbtsiAutoPoll;            ///< hwmSbtsiAutoPoll
-  unsigned char hwmSbtsiAutoPollStarted;            ///< hwmSbtsiAutoPollStarted
-  unsigned char fanLinearEnhanceEn;          ///< fanLinearEnhanceEn
-  unsigned char fanLinearHoldFix;            ///< fanLinearHoldFix
-  unsigned char fanLinearRangeOutLimit;      ///< fanLinearRangeOutLimit
-  unsigned char hwmSbtsiMode;            ///< hwmSbtsiMode
-  unsigned short hwmCalibrationFactor;            ///< hwmEfuseFactor
-  HWM_cur_struct hwmCurrent;            ///< hwmCurrent
-  HWM_cur_struct hwmCurrentRaw;            ///< hwmCurrentRaw
-  HWM_temp_par_struct hwmTempPar[5];          ///< hwmTempPar
-  HWM_fan_ctl_struct hwmFanControl[5];             ///< hwmFanControl
-  HWM_fan_ctl_struct hwmFanControlCooked[5];             ///< hwmFanControlCooked
-} HWM_struct;
-
-/**
- * The IMC struct  for CIMx Module. *
- */
-typedef struct _IMC_struct {
-  unsigned char imcEnable;            ///< imcEnable
-  unsigned char imcEnabled;            ///< imcEnabled
-  unsigned char imcSureBootTimer;            ///< imcSureBootTimer
-} IMC_struct;
-
-/**
- * The EC fan MSGREG struct  for CIMx Module. *
- */
-typedef struct _EC_struct {
-  unsigned char  MSGFun81zone0MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun81zone0MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun81zone0MSGREG2;  ///<Thermal zone control byte 1
-  unsigned char  MSGFun81zone0MSGREG3;  ///<Thermal zone control byte 2
-  unsigned char  MSGFun81zone0MSGREG4;  ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
-  unsigned char  MSGFun81zone0MSGREG5;  ///<Hysteresis inforamtion
-  unsigned char  MSGFun81zone0MSGREG6;  ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
-  unsigned char  MSGFun81zone0MSGREG7;  ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
-  unsigned char  MSGFun81zone0MSGREG8;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-  unsigned char  MSGFun81zone0MSGREG9;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-
-  //EC LDN9 funtion 81 zone 1
-  unsigned char  MSGFun81zone1MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun81zone1MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun81zone1MSGREG2;  ///<Thermal zone control byte 1
-  unsigned char  MSGFun81zone1MSGREG3;  ///<Thermal zone control byte 2
-  unsigned char  MSGFun81zone1MSGREG4;  ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
-  unsigned char  MSGFun81zone1MSGREG5;  ///<Hysteresis inforamtion
-  unsigned char  MSGFun81zone1MSGREG6;  ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
-  unsigned char  MSGFun81zone1MSGREG7;  ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
-  unsigned char  MSGFun81zone1MSGREG8;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-  unsigned char  MSGFun81zone1MSGREG9;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-
-  //EC LDN9 funtion 81 zone 2
-  unsigned char  MSGFun81zone2MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun81zone2MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun81zone2MSGREG2;  ///<Thermal zone control byte 1
-  unsigned char  MSGFun81zone2MSGREG3;  ///<Thermal zone control byte 2
-  unsigned char  MSGFun81zone2MSGREG4;  ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
-  unsigned char  MSGFun81zone2MSGREG5;  ///<Hysteresis inforamtion
-  unsigned char  MSGFun81zone2MSGREG6;  ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
-  unsigned char  MSGFun81zone2MSGREG7;  ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
-  unsigned char  MSGFun81zone2MSGREG8;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-  unsigned char  MSGFun81zone2MSGREG9;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-
-  //EC LDN9 funtion 81 zone 3
-  unsigned char  MSGFun81zone3MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun81zone3MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun81zone3MSGREG2;  ///<Thermal zone control byte 1
-  unsigned char  MSGFun81zone3MSGREG3;  ///<Thermal zone control byte 2
-  unsigned char  MSGFun81zone3MSGREG4;  ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
-  unsigned char  MSGFun81zone3MSGREG5;  ///<Hysteresis inforamtion
-  unsigned char  MSGFun81zone3MSGREG6;  ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
-  unsigned char  MSGFun81zone3MSGREG7;  ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
-  unsigned char  MSGFun81zone3MSGREG8;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-  unsigned char  MSGFun81zone3MSGREG9;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-
-  //EC LDN9 funtion 83 zone 0
-  unsigned char  MSGFun83zone0MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun83zone0MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun83zone0MSGREG2;  ///<_AC0
-  unsigned char  MSGFun83zone0MSGREG3;  ///<_AC1
-  unsigned char  MSGFun83zone0MSGREG4;  ///<_AC2
-  unsigned char  MSGFun83zone0MSGREG5;  ///<_AC3
-  unsigned char  MSGFun83zone0MSGREG6;  ///<_AC4
-  unsigned char  MSGFun83zone0MSGREG7;  ///<_AC5
-  unsigned char  MSGFun83zone0MSGREG8;  ///<_AC6
-  unsigned char  MSGFun83zone0MSGREG9;  ///<_AC7
-  unsigned char  MSGFun83zone0MSGREGA;  ///<_CRT
-  unsigned char  MSGFun83zone0MSGREGB;  ///<_PSV
-
-  //EC LDN9 funtion 83 zone 1
-  unsigned char  MSGFun83zone1MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun83zone1MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun83zone1MSGREG2;  ///<_AC0
-  unsigned char  MSGFun83zone1MSGREG3;  ///<_AC1
-  unsigned char  MSGFun83zone1MSGREG4;  ///<_AC2
-  unsigned char  MSGFun83zone1MSGREG5;  ///<_AC3
-  unsigned char  MSGFun83zone1MSGREG6;  ///<_AC4
-  unsigned char  MSGFun83zone1MSGREG7;  ///<_AC5
-  unsigned char  MSGFun83zone1MSGREG8;  ///<_AC6
-  unsigned char  MSGFun83zone1MSGREG9;  ///<_AC7
-  unsigned char  MSGFun83zone1MSGREGA;  ///<_CRT
-  unsigned char  MSGFun83zone1MSGREGB;  ///<_PSV
-
-  //EC LDN9 funtion 83 zone 2
-  unsigned char  MSGFun83zone2MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun83zone2MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun83zone2MSGREG2;  ///<_AC0
-  unsigned char  MSGFun83zone2MSGREG3;  ///<_AC1
-  unsigned char  MSGFun83zone2MSGREG4;  ///<_AC2
-  unsigned char  MSGFun83zone2MSGREG5;  ///<_AC3
-  unsigned char  MSGFun83zone2MSGREG6;  ///<_AC4
-  unsigned char  MSGFun83zone2MSGREG7;  ///<_AC5
-  unsigned char  MSGFun83zone2MSGREG8;  ///<_AC6
-  unsigned char  MSGFun83zone2MSGREG9;  ///<_AC7
-  unsigned char  MSGFun83zone2MSGREGA;  ///<_CRT
-  unsigned char  MSGFun83zone2MSGREGB;  ///<_PSV
-
-  //EC LDN9 funtion 83 zone 3
-  unsigned char  MSGFun83zone3MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun83zone3MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun83zone3MSGREG2;  ///<_AC0
-  unsigned char  MSGFun83zone3MSGREG3;  ///<_AC1
-  unsigned char  MSGFun83zone3MSGREG4;  ///<_AC2
-  unsigned char  MSGFun83zone3MSGREG5;  ///<_AC3
-  unsigned char  MSGFun83zone3MSGREG6;  ///<_AC4
-  unsigned char  MSGFun83zone3MSGREG7;  ///<_AC5
-  unsigned char  MSGFun83zone3MSGREG8;  ///<_AC6
-  unsigned char  MSGFun83zone3MSGREG9;  ///<_AC7
-  unsigned char  MSGFun83zone3MSGREGA;  ///<_CRT
-  unsigned char  MSGFun83zone3MSGREGB;  ///<_PSV
-
-  //EC LDN9 funtion 85 zone 0
-  unsigned char  MSGFun85zone0MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun85zone0MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun85zone0MSGREG2;  ///<AL0 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone0MSGREG3;  ///<AL1 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone0MSGREG4;  ///<AL2 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone0MSGREG5;  ///<AL3 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone0MSGREG6;  ///<AL4 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone0MSGREG7;  ///<AL5 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone0MSGREG8;  ///<AL6 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone0MSGREG9;  ///<AL7 PWM level in percentage (0 - 100%)
-
-  //EC LDN9 funtion 85 zone 1
-  unsigned char  MSGFun85zone1MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun85zone1MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun85zone1MSGREG2;  ///<AL0 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone1MSGREG3;  ///<AL1 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone1MSGREG4;  ///<AL2 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone1MSGREG5;  ///<AL3 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone1MSGREG6;  ///<AL4 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone1MSGREG7;  ///<AL5 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone1MSGREG8;  ///<AL6 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone1MSGREG9;  ///<AL7 PWM level in percentage (0 - 100%)
-
-  //EC LDN9 funtion 85 zone 2
-  unsigned char  MSGFun85zone2MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun85zone2MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun85zone2MSGREG2;  ///<AL0 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone2MSGREG3;  ///<AL1 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone2MSGREG4;  ///<AL2 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone2MSGREG5;  ///<AL3 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone2MSGREG6;  ///<AL4 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone2MSGREG7;  ///<AL5 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone2MSGREG8;  ///<AL6 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone2MSGREG9;  ///<AL7 PWM level in percentage (0 - 100%)
-
-  //EC LDN9 funtion 85 zone 3
-  unsigned char  MSGFun85zone3MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun85zone3MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun85zone3MSGREG2;  ///<AL0 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone3MSGREG3;  ///<AL1 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone3MSGREG4;  ///<AL2 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone3MSGREG5;  ///<AL3 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone3MSGREG6;  ///<AL4 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone3MSGREG7;  ///<AL5 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone3MSGREG8;  ///<AL6 PWM level in percentage (0 - 100%)
-  unsigned char  MSGFun85zone3MSGREG9;  ///<AL7 PWM level in percentage (0 - 100%)
-
-  //EC LDN9 funtion 89 TEMPIN channel 0
-  unsigned char  MSGFun89zone0MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun89zone0MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun89zone0MSGREG2;  ///<At DWORD bit 0-7
-  unsigned char  MSGFun89zone0MSGREG3;  ///<At DWORD bit 15-8
-  unsigned char  MSGFun89zone0MSGREG4;  ///<At DWORD bit 23-16
-  unsigned char  MSGFun89zone0MSGREG5;  ///<At DWORD bit 31-24
-  unsigned char  MSGFun89zone0MSGREG6;  ///<Ct DWORD bit 0-7
-  unsigned char  MSGFun89zone0MSGREG7;  ///<Ct DWORD bit 15-8
-  unsigned char  MSGFun89zone0MSGREG8;  ///<Ct DWORD bit 23-16
-  unsigned char  MSGFun89zone0MSGREG9;  ///<Ct DWORD bit 31-24
-  unsigned char  MSGFun89zone0MSGREGA;  ///<Mode bit 0-7
-
-  //EC LDN9 funtion 89 TEMPIN channel 1
-  unsigned char  MSGFun89zone1MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun89zone1MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun89zone1MSGREG2;  ///<At DWORD bit 0-7
-  unsigned char  MSGFun89zone1MSGREG3;  ///<At DWORD bit 15-8
-  unsigned char  MSGFun89zone1MSGREG4;  ///<At DWORD bit 23-16
-  unsigned char  MSGFun89zone1MSGREG5;  ///<At DWORD bit 31-24
-  unsigned char  MSGFun89zone1MSGREG6;  ///<Ct DWORD bit 0-7
-  unsigned char  MSGFun89zone1MSGREG7;  ///<Ct DWORD bit 15-8
-  unsigned char  MSGFun89zone1MSGREG8;  ///<Ct DWORD bit 23-16
-  unsigned char  MSGFun89zone1MSGREG9;  ///<Ct DWORD bit 31-24
-  unsigned char  MSGFun89zone1MSGREGA;  ///<Mode bit 0-7
-
-  //EC LDN9 funtion 89 TEMPIN channel 2
-  unsigned char  MSGFun89zone2MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun89zone2MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun89zone2MSGREG2;  ///<At DWORD bit 0-7
-  unsigned char  MSGFun89zone2MSGREG3;  ///<At DWORD bit 15-8
-  unsigned char  MSGFun89zone2MSGREG4;  ///<At DWORD bit 23-16
-  unsigned char  MSGFun89zone2MSGREG5;  ///<At DWORD bit 31-24
-  unsigned char  MSGFun89zone2MSGREG6;  ///<Ct DWORD bit 0-7
-  unsigned char  MSGFun89zone2MSGREG7;  ///<Ct DWORD bit 15-8
-  unsigned char  MSGFun89zone2MSGREG8;  ///<Ct DWORD bit 23-16
-  unsigned char  MSGFun89zone2MSGREG9;  ///<Ct DWORD bit 31-24
-  unsigned char  MSGFun89zone2MSGREGA;  ///<Mode bit 0-7
-
-  //EC LDN9 funtion 89 TEMPIN channel 3
-  unsigned char  MSGFun89zone3MSGREG0;  ///<Thermal zone
-  unsigned char  MSGFun89zone3MSGREG1;  ///<Thermal zone
-  unsigned char  MSGFun89zone3MSGREG2;  ///<At DWORD bit 0-7
-  unsigned char  MSGFun89zone3MSGREG3;  ///<At DWORD bit 15-8
-  unsigned char  MSGFun89zone3MSGREG4;  ///<At DWORD bit 23-16
-  unsigned char  MSGFun89zone3MSGREG5;  ///<At DWORD bit 31-24
-  unsigned char  MSGFun89zone3MSGREG6;  ///<Ct DWORD bit 0-7
-  unsigned char  MSGFun89zone3MSGREG7;  ///<Ct DWORD bit 15-8
-  unsigned char  MSGFun89zone3MSGREG8;  ///<Ct DWORD bit 23-16
-  unsigned char  MSGFun89zone3MSGREG9;  ///<Ct DWORD bit 31-24
-  unsigned char  MSGFun89zone3MSGREGA;  ///<Mode bit 0-7
-
-  // FLAG for Fun83/85/89 support
-  unsigned short IMCFUNSupportBitMap;   ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
-} EC_struct;
-
-/** SBGPPPORTCONFIG - Southbridge GPP port config structure */
-typedef struct {
-  unsigned char   PortPresent;     /**< Port connection
-                                   *   @par
-                                   *    @li <b>0</b> - Port doesn't have slot. No need to train the link
-                                   *    @li <b>1</b> - Port connection defined and needs to be trained
-                                   */
-  unsigned char   PortDetected;    /**< Link training status
-                                   *   @par
-                                   *    @li <b>0</b> - EP not detected
-                                   *    @li <b>1</b> - EP detected
-                                   */
-  unsigned char   PortIsGen2;      /**< Port link speed configuration
-                                   *   @par
-                                   *    @li <b>00</b> - Auto
-                                   *    @li <b>01</b> - Forced GEN1
-                                   *    @li <b>10</b> - Forced GEN2
-                                   *    @li <b>11</b> - Reserved
-                                   */
-
-  unsigned char   PortHotPlug;     /**< Support hot plug?
-                                   *   @par
-                                   *    @li <b>0</b> - No support
-                                   *    @li <b>1</b> - support
-                                   */
-} SBGPPPORTCONFIG;
-
-/** CODECENTRY - Southbridge HD Audio OEM Codec structure */
-typedef struct _CODECENTRY {
-/** Nid - Reserved ?? */
-  unsigned char Nid;
-/** Byte40 - Reserved ?? */
-  unsigned int Byte40;
-} CODECENTRY;
-
-/** CODECTBLLIST - Southbridge HD Audio Codec table list */
-typedef struct _CODECTBLLIST {
-/** CodecID - Codec ID */
-  unsigned int   CodecID;
-/** CodecTablePtr - Codec table pointer */
-  CODECENTRY* CodecTablePtr;
-} CODECTBLLIST;
-
-/** Sata Controller structure */
-typedef struct _SATAST {
-  unsigned char   SataModeReg;               /** SataModeReg - Reserved 00-01-00*/
-  unsigned char   SataController;            /**< SataController 00-01-01
-                                        *   @par
-                                        * Sata Controller
-                                        *    @li <b>0</b> - disable
-                                        *    @li <b>1</b> - enable
-                                        */
-  unsigned char   SataIdeCombMdPriSecOpt;    /**< SataIdeCombMdPriSecOpt - Reserved 00-01-02*/
-  unsigned char   SataSetMaxGen2;            /**< SataSetMaxGen2 00-01-03
-                                        *   @par
-                                        * Sata Controller Set to Max Gen2 mode
-                                        *    @li <b>0</b> - disable
-                                        *    @li <b>1</b> - enable
-                                        */
-  unsigned char   SataIdeCombinedMode;       /**< SataIdeCombinedMode 00-01-04
-                                        *   @par
-                                        * Sata IDE Controller set to Combined Mode
-                                        *    @li <b>0</b> - disable
-                                        *    @li <b>1</b> - enable
-                                        */
-/** SataClkMode - Reserved 00-01-05 */
-  unsigned char   SataClkMode;              // 4:7
-} SATAST;
-
-/** _USBST Controller structure
- *
- * Usb Ohci1 Contoller is defined at BIT0
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 18 Func0) *
- * Usb Ehci1 Contoller is defined at BIT1
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 18 Func2) *
- * Usb Ohci2 Contoller is defined at BIT2
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 19 Func0) *
- * Usb Ehci2 Contoller is defined at BIT3
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 19 Func2) *
- * Usb Ohci3 Contoller is defined at BIT4
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 22 Func0) *
- * Usb Ehci3 Contoller is defined at BIT5
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 22 Func2) *
- * Usb Ohci4 Contoller is defined at BIT6
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 20 Func5) *
- */
-typedef struct _USBST {
-  unsigned char   UsbModeReg;               /** UsbModeReg - Reserved */
-  unsigned char  Ohci1;                      ///< Ohci0 controller - 0:disable, 1:enable
-  unsigned char  Ehci1;                      ///< Ehci1 controller - 0:disable, 1:enable
-  unsigned char  Ohci2;                      ///< Ohci2 controller - 0:disable, 1:enable
-  unsigned char  Ehci2;                      ///< Ehci2 controller - 0:disable, 1:enable
-  unsigned char  Ohci3;                      ///< Ohci3 controller - 0:disable, 1:enable
-  unsigned char  Ehci3;                      ///< Ehci3 controller - 0:disable, 1:enable
-  unsigned char  Ohci4;                      ///< Ohci4 controller - 0:disable, 1:enable
-} USBST;
-
-
-/** SATAPORTST - SATA PORT structure
- *
- */
-typedef struct _SATAPORTST {
-  unsigned char    SataPortPowerReg;         /** SataPortPowerReg - Reserved */
-  unsigned char  PORT0;                      ///< PORT0 - 0:disable, 1:enable
-  unsigned char  PORT1;                      ///< PORT1 - 0:disable, 1:enable
-  unsigned char  PORT2;                      ///< PORT2 - 0:disable, 1:enable
-  unsigned char  PORT3;                      ///< PORT3 - 0:disable, 1:enable
-  unsigned char  PORT4;                      ///< PORT4 - 0:disable, 1:enable
-  unsigned char  PORT5;                      ///< PORT5 - 0:disable, 1:enable
-  unsigned char  PORT6;                      ///< PORT6 - 0:disable, 1:enable
-  unsigned char  PORT7;                      ///< PORT7 - 0:disable, 1:enable
-} SATAPORTST;
-
-
-///< _SATAPORTMD - Force Each PORT to GEN1/GEN2 mode
-typedef struct _SATAPORTMD {
-  unsigned short   SataPortMode;             /** SataPortMode - Reserved */
-  unsigned short  PORT0;                     ///< PORT0 - set BIT0 to GEN1, BIT1 - PORT0 set to GEN2
-  unsigned short  PORT1;                     ///< PORT1 - set BIT2 to GEN1, BIT3 - PORT1 set to GEN2
-  unsigned short  PORT2;                     ///< PORT2 - set BIT4 to GEN1, BIT5 - PORT2 set to GEN2
-  unsigned short  PORT3;                     ///< PORT3 - set BIT6 to GEN1, BIT7 - PORT3 set to GEN2
-  unsigned short  PORT4;                     ///< PORT4 - set BIT8 to GEN1, BIT9 - PORT4 set to GEN2
-  unsigned short  PORT5;                     ///< PORT5 - set BIT10 to GEN1, BIT11 - PORT5 set to GEN2
-  unsigned short  PORT6;                     ///< PORT6 - set BIT12 to GEN1, BIT13 - PORT6 set to GEN2
-  unsigned short  PORT7;                     ///< PORT7 - set BIT14 to GEN1, BIT15 - PORT7 set to GEN2
-} SATAPORTMD;
-
-/**
- * _AZALIAPIN - HID Azalia or GPIO define structure.
- *
- */
-typedef struct _AZALIAPIN {
-  unsigned char   AzaliaSdinPin;             ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-  unsigned char   AzaliaSdin0;               /**< AzaliaSdin0
-                                        *   @par
-                                        * SDIN0 is defined at BIT0 & BIT1
-                                        *    @li <b>00</b> - GPIO PIN
-                                        *    @li <b>10</b> - As a Azalia SDIN pin
-                                        */
-  unsigned char   AzaliaSdin1;               /**< AzaliaSdin1
-                                        *   @par
-                                        * SDIN0 is defined at BIT2 & BIT3
-                                        *    @li <b>00</b> - GPIO PIN
-                                        *    @li <b>10</b> - As a Azalia SDIN pin
-                                        */
-  unsigned char   AzaliaSdin2;               /**< AzaliaSdin2
-                                        *   @par
-                                        * SDIN0 is defined at BIT4 & BIT5
-                                        *    @li <b>00</b> - GPIO PIN
-                                        *    @li <b>10</b> - As a Azalia SDIN pin
-                                        */
-  unsigned char   AzaliaSdin3;               /**< AzaliaSdin3
-                                        *   @par
-                                        * SDIN0 is defined at BIT6 & BIT7
-                                        *    @li <b>00</b> - GPIO PIN
-                                        *    @li <b>10</b> - As a Azalia SDIN pin
-                                        */
-} AZALIAPIN;
-
-/** AMDSBCFG - Southbridge CIMx configuration structure (Main) */
-typedef struct _AMDSBCFG {
-/** StdHeader - Standard header for all AGESA/CIMx services. */
-  AMD_CONFIG_PARAMS   StdHeader;
-
-/** BuildParameters - The STATIC platform information for CIMx Module. 00-00-00 */
-  BUILDPARAM BuildParameters;
-                                      //offset 90 bytes (32-121)
-  //MsgXchgBiosCimx                   //offset 8 bytes (122-129)
-  // SATA Configuration
-
-  union /**< union - Reserved 00-01-00 */
-  {  /**< SATAMODE - Sata Controller structure */
-/** SataModeReg - Reserved */
-    unsigned char   SataModeReg;
-/** SataMode - Reserved */
-    SATAST  SataMode;
-  } SATAMODE;
-/** S3Resume - Flag of ACPI S3 Resume. 00-02 Internal USED */
-  unsigned char   S3Resume;                   // 8
-/** RebootRequired - Flag of Reboot system is required. 00-03 Internal USED (retired) */
-  unsigned char   RebootRequired;             // 9
-/** SbSpiSpeedSupport - Reserved 00-04 (retired)*/
-  unsigned char   SbSpiSpeedSupport;   // 10
-/**< SpreadSpectrum 00-05-00
- *   @par
- *   Spread Spectrum function
- *    @li <b>0</b> - disable
- *    @li <b>1</b> - enable
- */
-  unsigned char   SpreadSpectrum;             // 11
-/** NbSbGen2 - Reserved 00-06-00 */
-  unsigned char   NbSbGen2;                   // 12 00-07
-  unsigned char   GppGen2;                    // 13 00-08
-  unsigned char   GppMemWrImprove;            // 14 00-09
-  unsigned char   S4Resume;                   // 15 00-10 Internal
-  unsigned char   FchVariant;                 //
-/**< SataClass - SATA Controller mode [2:0] 00-11
- *   @par
- *    @li <b>000</b> - Native IDE mode
- *    @li <b>001</b> - RAID mode
- *    @li <b>010</b> - AHCI mode
- *    @li <b>011</b> - Legacy IDE mode
- *    @li <b>100</b> - IDE->AHCI mode
- *    @li <b>101</b> - AHCI mode as 7804 ID (AMD driver)
- *    @li <b>110</b> - IDE->AHCI mode as 7804 ID (AMD driver)
- */
-  unsigned char   SataClass;                 // 2:0
-/**< SataIdeMode - Sata IDE Controller mode 00-12
- *   @par
- *    @li <b>0</b> - Legacy IDE mode
- *    @li <b>1</b> - Native IDE mode
- */
-  unsigned char   SataIdeMode;               // 3
-  unsigned char   sdConfig;        /**< sdMode 00-13
-                                   *   @par
-                                   *    SD Configuration
-                                   *    @li <b>00</b> - Disabled
-                                   *    @li <b>00</b> - AMDA,  set 24,18,16,  default
-                                   *    @li <b>01</b> - DMA clear 24, 16, set 18
-                                   *    @li <b>10</b> - PIO clear 24,18,16
-                                   *
-                                   */
-  unsigned char   sdSpeed;        /**< sdSpeed 00-14
-                                   *   @par
-                                   *    SD Configuration
-                                   *    @li <b>0</b> - Low speed clear 17
-                                   *    @li <b>1</b> - High speed, set 17, default
-                                   *
-                                   */
-  unsigned char   sdBitwidth;        /**< sdBitwidth 00-15
-                                   *   @par
-                                   *    SD Configuration
-                                   *    @li <b>0</b> - 32BIT clear 23
-                                   *    @li <b>1</b> - 64BIT, set 23,default
-                                   *
-                                   */
-/**< SataDisUnusedIdePChannel - Disable Unused IDE Primary Channel 00-16
- *   @par
- *    @li <b>0</b> - Channel Enable
- *    @li <b>1</b> - Channel Disable
- */
-  unsigned char   SataDisUnusedIdePChannel;
-/**< SataDisUnusedIdeSChannel - Disable Unused IDE Secondary Channel 00-17
- *   @par
- *    @li <b>0</b> - Channel Enable
- *    @li <b>1</b> - Channel Disable
- */
-  unsigned char   SataDisUnusedIdeSChannel;
-/**< IdeDisUnusedIdePChannel - Disable Unused IDE Primary Channel 00-18
- *   @par
- *    @li <b>0</b> - Channel Enable
- *    @li <b>1</b> - Channel Disable
- */
-  unsigned char   IdeDisUnusedIdePChannel;
-/**< IdeDisUnusedIdeSChannel - Disable Unused IDE IDE Secondary Channel 00-19
- *   @par
- *    @li <b>0</b> - Channel Enable
- *    @li <b>1</b> - Channel Disable
- */
-  unsigned char   IdeDisUnusedIdeSChannel;
-
-/**<  SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)  00-20
- *   @par
- *    @li <b> BIT0 </b> - PORT0 set as ESP port
- *    @li <b> BIT1 </b> - PORT1 set as ESP port
- *    @li <b> BIT2 </b> - PORT2 set as ESP port
- *    @li <b> BIT3 </b> - PORT3 set as ESP port
- *    @li <b> BIT4 </b> - PORT4 set as ESP port
- *    @li <b> BIT5 </b> - PORT5 set as ESP port
- *    @li <b> BIT6 </b> - PORT6 set as ESP port
- *    @li <b> BIT7 </b> - PORT7 set as ESP port
- */
-  union /**< union - Reserved */
-  { /**< SATAPORT - SATA Port Structure */
-  /** SataPortReg - Reserved */
-    unsigned char    SataPortReg;
-    SATAPORTST SataEspPort;           // 23:16
-  } SATAESPPORT;
-
-  union /**< union - Reserved  00-21*/
-  { /**< SATAPORT - SATA Port Structure */
-  /** SataPortPowerReg - Reserved */
-    unsigned char    SataPortPowerReg;
-    SATAPORTST SataPortPower;         // 31:24
-  } SATAPORTPOWER;
-
-  // SATA Debug Option                //offset 4 bytes (130-133)
-
-  union /**< union - Reserved  00-22*/
-  {
-/**< SataPortMode - Force Each PORT to GEN1/GEN2 mode
- *   @par
- *    @li <b> 0 </b> Auto for each PORTs
- *    @li <b> BIT0 = 1</b> - PORT0 set to GEN1
- *    @li <b> BIT1 = 1</b> - PORT0 set to GEN2
- *    @li <b> BIT2 = 1</b> - PORT1 set to GEN1
- *    @li <b> BIT3 = 1</b> - PORT1 set to GEN2
- *    @li <b> BIT4 = 1</b> - PORT2 set to GEN1
- *    @li <b> BIT5 = 1</b> - PORT2 set to GEN2
- *    @li <b> BIT6 = 1</b> - PORT3 set to GEN1
- *    @li <b> BIT7 = 1</b> - PORT3 set to GEN2
- *    @li <b> BIT8 = 1</b> - PORT4 set to GEN1
- *    @li <b> BIT9 = 1</b> - PORT4 set to GEN2
- *    @li <b> BIT10 = 1</b> - PORT5 set to GEN1
- *    @li <b> BIT11 = 1</b> - PORT5 set to GEN2
- *    @li <b> BIT12 = 1</b> - PORT6 set to GEN1
- *    @li <b> BIT13 = 1</b> - PORT6 set to GEN2
- *    @li <b> BIT14 = 1</b> - PORT7 set to GEN1
- *    @li <b> BIT15 = 1</b> - PORT7 set to GEN2
- */
-    unsigned short   SataPortMode;               //15:0
-    SATAPORTMD SataPortMd;
-  } SATAPORTMODE;
-/** SATAClkSelOpt - Reserved  00-23*/
-  unsigned char   SATAClkSelOpt;              //19:16  *Removed from coding side
-/** SataAggrLinkPmCap - Reserved  00-24*/
-  unsigned char   SataAggrLinkPmCap;          //20, 0:OFF   1:ON
-/** SataPortMultCap - Reserved  00-25*/
-  unsigned char   SataPortMultCap;            //21, 0:OFF   1:ON
-/** SataClkAutoOff - Reserved  00-26*/
-  unsigned char   SataClkAutoOff;             //22, AutoClockOff 0:Disabled, 1:Enabled
-/** SataPscCap - Reserved  00-27*/
-  unsigned char   SataPscCap;                 //23, 1:Enable PSC capability, 0:Disable PSC capability
-/** BIOSOSHandoff - Reserved  00-28*/
-  unsigned char   BIOSOSHandoff;              //24
-/** SataFisBasedSwitching - Reserved  00-29*/
-  unsigned char   SataFisBasedSwitching;      //25
-/** SataCccSupport - Reserved  00-30*/
-  unsigned char   SataCccSupport;             //26
-/** SataSscCap - Reserved  00-31*/
-  unsigned char   SataSscCap;                 //27, 1:Enable SSC capability, 0:Disable SSC capability
-/** SataMsiCapability - Reserved  00-32*/
-  unsigned char   SataMsiCapability;          //28  0:Hidden 1:Visible
-/** SataForceRaid - Reserved  00-33*/
-  unsigned char   SataForceRaid;              //29  0:No function 1:Force RAID
-/** SataInternal100Spread - Reserved  00-34*/
-  unsigned char   SataInternal100Spread;      //30
-
-  // SATA Debug Option (2)          //offset 4 bytes (134-137)
-
-/** SataTargetSupport8Device - Reserved  00-35*/
-  unsigned char   SataTargetSupport8Device;   // 0
-/** SataDisableGenericMode - Reserved  00-36*/
-  unsigned char   SataDisableGenericMode;     // 1
-/** SataAhciEnclosureManagement - Reserved  00-37 */
-  unsigned char   SataAhciEnclosureManagement; // 2
-/** SataSgpio0 - Reserved  00-38*/
-  unsigned char   SataSgpio0;                 // 3
-/** SataSgpio1 - Reserved  00-39*/
-  unsigned char   SataSgpio1;                 // 4
-/** SataPhyPllShutDown - Reserved  00-40*/
-  unsigned char   SataPhyPllShutDown;         // 5
-/** SataHotRemoveEnh - Reserved */
-  unsigned char   SataHotRemoveEnh;           // 6
-/**< SataHotRemovelEnh for each ports - Hot-removal enhancementEnable for portN
- *   @par
- *    @li <b> BIT0 </b> - PORT0 set as HotRemovelEnh port
- *    @li <b> BIT1 </b> - PORT1 set as HotRemovelEnh port
- *    @li <b> BIT2 </b> - PORT2 set as HotRemovelEnh port
- *    @li <b> BIT3 </b> - PORT3 set as HotRemovelEnh port
- *    @li <b> BIT4 </b> - PORT4 set as HotRemovelEnh port
- *    @li <b> BIT5 </b> - PORT5 set as HotRemovelEnh port
- *    @li <b> BIT6 </b> - PORT6 set as HotRemovelEnh port
- *    @li <b> BIT7 </b> - PORT7 set as HotRemovelEnh port
- */
-  union /**< union - Reserved  00-41*/
-  { /**< SATAPORT - SATA Port Structure */
-  /** SataHotRemovelEnh - Reserved */    // 31:24
-    unsigned char    SataHotRemovelEnh:8;
-    SATAPORTST SataHotRemoveEnhPort;
-  } SATAHOTREMOVALENH;
-
-//
-// USB Configuration                //offset 4 bytes (134-137)
-//
-
-/** USBDeviceConfig - USB Controller Configuration
- *
- * Usb Ohci1 Contoller is defined at BIT0
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 18 Func0) *
- * Usb Ehci1 Contoller is defined at BIT1
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 18 Func2) *
- * Usb Ohci2 Contoller is defined at BIT2
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 19 Func0) *
- * Usb Ehci2 Contoller is defined at BIT3
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 19 Func2) *
- * Usb Ohci3 Contoller is defined at BIT4
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 22 Func0) *
- * Usb Ehci3 Contoller is defined at BIT5
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 22 Func2) *
- * Usb Ohci4 Contoller is defined at BIT6
- *   - 0:disable 1:enable
- *                             (Bus 0 Dev 20 Func5) *
- */
-
-  union /**< union - Reserved */
-  {  /**< USBMODE - USB Controller structure */
-/** SataModeReg - Reserved  00-42*/
-    unsigned char   UsbModeReg;
-/** SataMode - Reserved */
-    USBST  UsbMode;
-  } USBMODE;
-
-/**< GecConfig  00-43
- *   @par
- *   InChip Gbit NIC
- *    @li <b>0</b> - disable
- *    @li <b>1</b> - enable
- */
-  unsigned char   GecConfig;                 //8
-/**< IrConfig  00-44
- *   @par
- *   Ir Controller
- *    @li <b>00 </b> - disable
- *    @li <b>01 </b> - Rx and Tx0
- *    @li <b>10 </b> - Rx and Tx1
- *    @li <b>11 </b> - Rx and both Tx0,Tx1
- */
-  unsigned char   IrConfig;                  //9:10
-  unsigned char   XhciSwitch;                 //11  00-45
-
-  //Azalia Configuration
-
-/**< AzaliaController - Azalia Controller Configuration  00-46
- *   @par
- *   Azalia Controller [0-1]
- *    @li <b>0</b> - Auto   : Detect Azalia controller automatically.
- *    @li <b>1</b> - Diable : Disable Azalia controller.
- *    @li <b>2</b> - Enable : Enable Azalia controller.
- */
-  unsigned char   AzaliaController;          //17:16
-/**< AzaliaPinCfg - Azalia Controller SDIN pin Configuration  00-47
- *   @par
- *    @li <b>0</b> - disable
- *    @li <b>1</b> - enable
- */
-  unsigned char   AzaliaPinCfg;              //18
-/**< AzaliaFrontPanel - Azalia Controller Front Panel Configuration  00-48
- *   @par
- *   Support Front Panel configuration
- *    @li <b>0</b> - Auto
- *    @li <b>1</b> - disable
- *    @li <b>2</b> - enable
- */
-  unsigned char   AzaliaFrontPanel;          //20:19
-/**< FrontPanelDetected - Force Azalia Controller Front Panel Configuration  00-49
- *   @par
- *   Force Front Panel configuration
- *    @li <b>0</b> - Not Detected
- *    @li <b>1</b> - Detected
- */
-  unsigned char   FrontPanelDetected;        //21
-/**< AzaliaSnoop - Azalia Controller Snoop feature Configuration  00-59
- *   @par
- *   Azalia Controller Snoop feature Configuration
- *    @li <b>0</b> - disable
- *    @li <b>1</b> - enable
- */
-  unsigned char   AzaliaSnoop;               //22
-/** AzaliaDummy - Reserved */
-  unsigned char   AzaliaDummy;               //23
-
-  union
-  {
-/**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration  00-51
- *
- * SDIN0 is defined at BIT0 & BIT1
- *   - 00: GPIO PIN
- *   - 01: Reserved
- *   - 10: As a Azalia SDIN pin
- *
- * SDIN1 is defined at BIT2 & BIT3
- *      * Config same as SDIN0
- * SDIN2 is defined at BIT4 & BIT5
- *      * Config same as SDIN0
- * SDIN3 is defined at BIT6 & BIT7
- *      * Config same as SDIN0
- */
-    unsigned char   AzaliaSdinPin;
-    AZALIAPIN  AzaliaConfig;
-  } AZALIACONFIG;
-
-/** AZOEMTBL - Azalia Controller OEM Codec Table Pointer  00-52
- *
- */
-  union
-  {
-    PLACEHOLDER  PlaceHolder;
-    CODECTBLLIST*  pAzaliaOemCodecTablePtr;  //offset 4 bytes (138-141)
-  } AZOEMTBL;
-
-/** AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer  00-53
- *
- */
-  union
-  {
-    PLACEHOLDER  PlaceHolder;
-    void*   pAzaliaOemFpCodecTablePtr;       //offset 4 bytes (142-145)
-  } AZOEMFPTBL;
-
-  //Miscellaneous Configuration      //offset 4 bytes (146-149)
-/** AnyHT200MhzLink - Reserved  00-54 */
-  unsigned char   AnyHT200MhzLink;             //0
-/**< HpetTimer - South Bridge Hpet Timer Configuration  00-56
- *   @par
- *    @li <b>0</b> - disable
- *    @li <b>1</b> - enable
- */
-  unsigned char   HpetTimer;                 //1
-/**< PciClks - PCI Slot Clock Control  00-57
- *   @par
- * PCI SLOT 0 define at BIT0
- *   - 00: disable
- *   - 01: enable
- *
- * PCI SLOT 1 define at BIT1
- *      * Config same as PCI SLOT0
- * PCI SLOT 2 define at BIT2
- *      * Config same as PCI SLOT0
- * PCI SLOT 3 define at BIT3
- *      * Config same as PCI SLOT0
- * PCI SLOT 4 define at BIT4
- *      * Config same as PCI SLOT0
- */
-  unsigned char   PciClks;                   //2:6
-/** MiscReserved1 - Reserved */
-  unsigned char   MiscReserved1;             //9:7, Reserved
-/** MobilePowerSavings - Debug function Reserved  00-58*/
-  unsigned char   MobilePowerSavings;        //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform
-/** ExternalRTCClock - Debug function Reserved  00-59*/
-  unsigned char   ExternalRTCClock;          //12, 0:Don't Shut Off, 1:Shut Off, external RTC clock
-/** NativePcieSupport - Debug function Reserved  00-60*/
-  unsigned char   NativePcieSupport;         //13, 0:Disabled, 1:Enable
-/** FlashPinConfig - Debug function Reserved  00-61*/
-  unsigned char   FlashPinConfig;            //14, 0:desktop mode 1:mobile mode
-/** UsbPhyPowerDown - Debug function Reserved  00-62*/
-  unsigned char   UsbPhyPowerDown;           //15
-/** PcibClkStopOverride - Debug function Reserved  00-63*/
-  unsigned short   PcibClkStopOverride;      //25:16
-/**< HpetMsiDis - South Bridge HPET MSI Configuration  00-64 (Retired)
- *   @par
- *    @li <b>1</b> - disable
- *    @li <b>0</b> - enable
- */
-  unsigned char   HpetMsiDis;                //26
-/**< ResetCpuOnSyncFlood - Rest CPU on Sync Flood  00-65 (Retired)
- *   @par
- *    @li <b>0</b> - disable
- *    @li <b>1</b> - enable
- */
-  unsigned char   ResetCpuOnSyncFlood;       //27
-
-  //DebugOptions                     //offset 4 bytes (150-153)
-/** PcibAutoClkCtr - Debug function Reserved  00-66*/
-  unsigned char   PcibAutoClkCtr;
-
-/**< OEMPROGTBL - ACPI MMIO register setting table OEM override  00-67
- *   @par
- *   OEM table for customer override ACPI MMIO register in their code.
- */
-  union
-  {
-    PLACEHOLDER OemProgrammingTablePtr;  //offset 4 bytes (154-157)
-    void   *OemProgrammingTablePtr_Ptr;
-  } OEMPROGTBL;
-
-  //Gpp Configuration                   //offset 24 bytes total (158-181)  00-68
-  union {
-    unsigned int           PORTCFG32;
-    SBGPPPORTCONFIG  PortCfg;
-  } PORTCONFIG[4];          //offset 16 bytes
-
-  unsigned char           GppLinkConfig;       /**< GPP_LINK_CONFIG = PCIE_GPP_Enable[3:0]  00-69
-                                         * @li  <b>0000</b> - Port ABCD -> 4:0:0:0
-                                         * @li  <b>0001</b> - N/A
-                                         * @li  <b>0010</b> - Port ABCD -> 2:2:0:0
-                                         * @li  <b>0011</b> - Port ABCD -> 2:1:1:0
-                                         * @li  <b>0100</b> - Port ABCD -> 1:1:1:1
-                                         */
-  unsigned char   GppFoundGfxDev;            ///< 3:0 If port A-D (mapped to bit [3:0]) has GFX EP detected  00-70
-  unsigned char   GppGen2Strap;              ///< 4   LC_GEN2_EN_STRAP  00-71 (internal used)
-  unsigned char   GppFunctionEnable;         ///< 5  00-72
-  unsigned char   GppUnhidePorts;            ///< 6  00-73
-  unsigned char   AlinkPhyPllPowerDown;      ///< 7  00-74
-  unsigned char   GppPortAspm;               /**< 9:8 ASPM state for all GPP ports  00-75
-                                         * @li   <b>01</b> - Disabled
-                                         * @li   <b>01</b> - L0s
-                                         * @li   <b>10</b> - L1
-                                         * @li   <b>11</b> - L0s + L1
-                                         */
-  unsigned char   GppLaneReversal;           ///< 10  00-76
-  unsigned char   GppPhyPllPowerDown;        ///< 11  00-77
-  unsigned char   GppDynamicPowerSaving;     ///< 12  00-78
-  unsigned char   PcieAER;                   ///< 13 Advanced Error Report: 0/1-disable/enable  00-79
-/** UmiDynamicSpeedChange - Reserved */
-  unsigned char   PcieRAS;                   // 14  00-80
-  unsigned char   GppHardwareDowngrade;      // 20:18: 0:Disable, 1-4: portA-D  00-83
-  unsigned char   GppToggleReset;            // 21  00-84
-  unsigned char   sdbEnable;                 // 22  00-85
-
-  //TempMMIO                            //offset 4 bytes (190-193)  00-86
-  unsigned int   TempMMIO;
-
-  // DebugOption2
-  unsigned char   GecPhyStatus;              //  00-86
-  unsigned char   GecDebugOptionDummy;       //  00-87
-  unsigned char   SBGecPwr;                  //  00-88
-  unsigned char   SBGecDebugBus;             //  00-89
-  unsigned char   SbPcieOrderRule;           //  00-90
-  unsigned char   AcDcMsg;                   //  00-91
-  unsigned char   TimerTickTrack;            //  00-92
-  unsigned char   ClockInterruptTag;         //  00-93
-  unsigned char   OhciTrafficHanding;        //  00-94
-  unsigned char   EhciTrafficHanding;        //  00-95
-  unsigned char   FusionMsgCMultiCore;       //  00-95A
-  unsigned char   FusionMsgCStage;           //  00-96
-  unsigned char   ALinkClkGateOff;           //  00-97
-  unsigned char   BLinkClkGateOff;           //  00-98
-  unsigned char   Sdb;                       //  00-99
-  unsigned char   SlowSpeedABlinkClock;      //  01-00
-  unsigned char   MtC1eEnable;               //  01-00
-  union
-  {
-    PLACEHOLDER DynamicGecRomAddressPtr;  //offset 4 bytes (194-201)  01-01
-    void   *DynamicGecRomAddress_Ptr;
-  } DYNAMICGECROM;
-//  unsigned int   UmiCommon;                   //offset 4 bytes (202-205)
-/** AbGppClockGating - Reserved */
-  unsigned char   AbClockGating;   // 01-02
-  unsigned char   GppClockGating;   // 01-03
-
-//  unsigned int   UmiDebug;
-
-/** L1TimerOverwrite - Reserved */
-  unsigned char   L1TimerOverwrite;     // 01-04
-/** UmiLinkWidth - Reserved */
-  unsigned char   UmiLinkWidth; // 4:3  01-05
-/** UmiDynamicSpeedChange - Reserved */
-  unsigned char   UmiDynamicSpeedChange;                 // 01-06
-/** PcieRefClockOverclocking - Reserved */
-  unsigned char   PcieRefClockOverclocking;                 // 9:6 01-07
-/** PcieRefClockOverclocking - Reserved */
-  unsigned char   SbAlinkGppTxDriverStrength;                 // 12:10 01-08
-  unsigned char   PwrFailShadow;               /**< PwrFailShadow = PM_Reg: 5Bh [3:0] 01-09
-                                         * @li  <b>00</b> - Always off
-                                         * @li  <b>01</b> - Always on
-                                         * @li  <b>10</b> - Always off
-                                         * @li  <b>11</b> - Use previous
-                                         */
-  unsigned char   StressResetMode;               /**< StressResetMode 01-10
-                                         * @li  <b>00</b> - Disabed
-                                         * @li  <b>01</b> - Io Write 0x64 with 0xfe
-                                         * @li  <b>10</b> - Io Write 0xcf9 with 0x06
-                                         * @li  <b>11</b> - Io Write 0xcf9 with 0x0e
-                                         */
-  EC_struct Pecstruct;  // 01-11 (Internal USED)
-  HWM_struct hwm;       // 01-12
-  IMC_struct imc;       // 01-13
-  unsigned char    Cg2Pll;      // 01-14
-  unsigned char    ClockRun;      // 01-15
-  unsigned char   Debug_Reg00;                 // 01-16
-  unsigned char   Debug_Reg01;                 // 01-17
-  unsigned char   Debug_Reg02;                 // 01-18
-  unsigned char   Debug_Reg03;                 // 01-19
-  unsigned char   Debug_Reg04;                 // 01-20
-  unsigned char   Debug_Reg05;                 // 01-21
-  unsigned char   EhciDataCacheDis;            // 01-22
-  unsigned char   EfuseByte [0x20];
-  unsigned char   EfuseRemainder ;
-  unsigned char   EfuseSum ;
-  unsigned char   L1ImmediateAck;
-} AMDSBCFG;
-
-/** SMMSERVICESTRUC- Southbridge SMI service structure */
-typedef  struct   _SMMSERVICESTRUC {
-/** enableRegNum - Reserved */
-  unsigned char enableRegNum;
-/** enableBit - Reserved */
-  unsigned char enableBit;
-/** statusRegNum - Reserved */
-  unsigned char statusRegNum;
-/** statusBit - Reserved */
-  unsigned char statusBit;
-/** *debugMessage- Reserved */
-  signed char *debugMessage;
-/** serviceRoutine - Reserved */
-  SMM_SERVICE_ROUTINE  serviceRoutine;
-} SMMSERVICESTRUC;
-
-#ifndef _NB_REG8MASK_
-
-/**
- *  - Byte Register R/W structure
- *
- */
-  typedef struct _Reg8Mask {
-/** bRegIndex - Reserved */
-    unsigned char bRegIndex;
-/** bANDMask - Reserved */
-    unsigned char bANDMask;
-/** bORMask - Reserved */
-    unsigned char bORMask;
-  } REG8MASK;
-#endif
-
-/**
- *  - SATA Phy setting structure
- *
- */
-typedef struct _SATAPHYSETTING {
-/** wPhyCoreControl - Reserved */
-  unsigned short wPhyCoreControl;
-/** dwPhyFineTune - Reserved */
-  unsigned int dwPhyFineTune;
-} SATAPHYSETTING;
-
-/**
- * _ABTblEntry - AB link register table R/W structure
- *
- */
-typedef struct _ABTblEntry {
-  /** regType  : AB Register Type (ABCFG, AXCFG and so on) */
-  unsigned char    regType;
-  /** regIndex : AB Register Index */
-  unsigned int   regIndex;
-  /** regMask  : AB Register Mask */
-  unsigned int   regMask;
-  /** regData  : AB Register Data */
-  unsigned int   regData;
-} ABTBLENTRY;
-
-/**
- * _AcpiRegWrite - ACPI MMIO register R/W structure
- *
- */
-typedef struct _AcpiRegWrite {
-  /** MmioBase     : Index of Southbridge block (For instance GPIO_BASE:0x01 SMI_BASE:0x02) */
-  unsigned char MmioBase;
-  /** MmioReg      : Register index */
-  unsigned char MmioReg;
-  /** DataANDMask  : AND Register Data */
-  unsigned char DataANDMask;
-  /** DataOrMask   : Or Register Data */
-  unsigned char DataOrMask;
-} AcpiRegWrite;
-
-/**
- * PCI_ADDRESS - PCI access structure
- *
- */
-#define PCI_ADDRESS(bus, dev, func, reg) \
-(unsigned int) ( (((unsigned int)bus) << 24) + (((unsigned int)dev) << 19) + (((unsigned int)func) << 16) + ((unsigned int)reg) )
-
-/**
- * CIM_STATUS - CIMx module function return code
- */
-typedef unsigned int    CIM_STATUS;
-/**
- * CIM_SUCCESS - Executed without error
- */
-#define CIM_SUCCESS 0x00000000
-/**
- * CIM_ERROR - call error
- */
-#define CIM_ERROR 0x80000000
-/**
- * CIM_UNSUPPORTED - function does not support
- */
-#define CIM_UNSUPPORTED 0x80000001
-
-#ifndef  LEGACY_BIOS_SUPPORT
-  #pragma pack (pop)
-#endif
-
-/**
- * DISABLED - Define disable in module
- */
-#define DISABLED   0
-/**
- * ENABLED - Define enable in module
- */
-#define ENABLED    1
-
-/// PCIE Reset Block
-typedef enum {
-  NbBlock,                        ///< Reset for NB PCIE
-  SbBlock                         ///< Reset for FCH GPP
-} RESET_BLOCK;
-
-/// PCIE Reset Operation
-typedef enum {
-  DeassertReset,                  ///< Deassert reset
-  AssertReset                     ///< Assert reset
-} RESET_OP;
-
-/**
- * SB_GPIO_INIT_ENTRY
- *
- */
-typedef struct _SB_GPIO_INIT_ENTRY {
-  unsigned char GpioPin;                  ///< Gpio Pin
-  unsigned char GpioMux;                  ///< Gpio Mux
-  unsigned char GpioOutEnB;               ///< Gpio Out EnB
-  unsigned char GpioOut;                  ///< Gpio Out
-} SB_GPIO_INIT_ENTRY;
-
-/**
- * SB_GPIO_CONTROL_ENTRY
- *
- */
-typedef struct _SB_GPIO_CONTROL_ENTRY {
-  unsigned char GpioPin;                  ///< Gpio Pin
-  unsigned char GpioControl;              ///< Gpio Control
-} SB_GPIO_CONTROL_ENTRY;
-
-/**
- * SB_SPREAD_SPECTRUM_ENTRY
- *
- */
-typedef struct _SB_SPREAD_SPECTRUM_ENTRY {
-  unsigned int P_40_25;                  ///< P_10_25_24
-  unsigned int P_18_15_5;              ///< P_10_25_24
-  unsigned int P_18_19_16;              ///< P_10_25_24
-  unsigned int P_10_23_8;              ///< P_10_25_24
-  unsigned int P_10_7_0;              ///< P_10_25_24
-  unsigned int P_1C_5_0;              ///< P_10_25_24
-  unsigned int P_08_31_28;              ///< P_10_25_24
-  unsigned int P_08_7;              ///< P_10_25_24
-  unsigned int P_08_8;              ///< P_10_25_24
-  unsigned int P_10_25_24;              ///< P_10_25_24
-} SB_SPREAD_SPECTRUM_ENTRY;
-#endif // _AMD_SBTYPE_H_
diff --git a/src/vendorcode/amd/cimx/sb900/Smm.c b/src/vendorcode/amd/cimx/sb900/Smm.c
deleted file mode 100644
index 51a4ccc6e1..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Smm.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/**
- * @file
- *
- * Southbridge SMM service function
- *
- * Prepare SMM service module for IBV call Southbridge SMI service routine.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-
-//
-// Declaration of local functions
-//
-
-/**
- * Southbridge SMI service module
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbSmmService (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  AMDSBCFG*   pTmp;      //lx-dummy for /W4 build
-  pTmp = pConfig;
-
-  TRACE ((DMSG_SB_TRACE, "CIMx - Entering SMM services \n"));
-
-  TRACE ((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n"));
-}
-
-/**
- * softwareSMIservice - Software SMI service
- *
- * @param[in] VOID Southbridge software SMI service ID.
- *
- */
-VOID
-softwareSMIservice (
-  IN       VOID
-  )
-{
-  TRACE ((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar));
-}
-
-
-
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/Usb.c b/src/vendorcode/amd/cimx/sb900/Usb.c
deleted file mode 100644
index 2d635ec9ee..0000000000
--- a/src/vendorcode/amd/cimx/sb900/Usb.c
+++ /dev/null
@@ -1,983 +0,0 @@
-/**
- * @file
- *
- * Config Southbridge USB controller
- *
- * Init USB features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      CIMx-SB
- * @e sub-project:
- * @e \$Revision:$   @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;     * Redistributions of source code must retain the above copyright
-;       notice, this list of conditions and the following disclaimer.
-;     * Redistributions in binary form must reproduce the above copyright
-;       notice, this list of conditions and the following disclaimer in the
-;       documentation and/or other materials provided with the distribution.
-;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-;       its contributors may be used to endorse or promote products derived
-;       from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-#include "Hudson-2.h"
-
-//
-// Declaration of local functions
-//
-VOID
-usbOverCurrentControl (
-  IN       AMDSBCFG* pConfig
-  );
-
-UINT32
-SetEhciPllWr (
-  IN       UINT32 Value,
-  IN       AMDSBCFG* pConfig
-  );
-
-/**
- * EhciInitAfterPciInit - Config USB controller after PCI emulation
- *
- * @param[in] Value Controller PCI config address (bus# + device# + function#)
- * @param[in] pConfig Southbridge configuration structure pointer.
- */
-VOID EhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);
-
-/**
- * OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation
- *
- * @param[in] Value  Controller PCI config address (bus# + device# + function#)
- * @param[in] pConfig Southbridge configuration structure pointer.
- */
-VOID OhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);
-
-#ifdef XHCI_SUPPORT
-  VOID XhciInitBeforePciInit (IN AMDSBCFG* pConfig);
-  VOID XhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-  VOID XhciInitLate (IN AMDSBCFG* pConfig);
-#endif
-/**
- * usbInitBeforePciEnum - Config USB controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usbInitBeforePciEnum (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT8     XhciEfuse;
-  // add Efuse checking for Xhci enable/disable
-  XhciEfuse = XHCI_EFUSE_LOCATION;
-  TRACE ((DMSG_SB_TRACE, "Entering PreInit Usb \n"));
-  // Disabled All USB controller
-  // RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0);
-  // Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
-  // Enable UsbResumeEnable (USB PME) * Default value
-  // In SB700 USB SleepCtrl set as BIT10+BIT9, but Hudson-2 default is BIT9+BIT8 (6 uframes)
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint16 | S3_SAVE, ~BIT2, BIT2 + BIT7 + BIT8 + BIT9);
-  // Overwrite EHCI bit by OHCI bit
-  pConfig->USBMODE.UsbModeReg = pConfig->USBMODE.UsbMode.Ohci1 \
-    + (pConfig->USBMODE.UsbMode.Ohci1 << 1) \
-    + (pConfig->USBMODE.UsbMode.Ohci2 << 2) \
-    + (pConfig->USBMODE.UsbMode.Ohci2 << 3) \
-    + (pConfig->USBMODE.UsbMode.Ohci3 << 4) \
-    + (pConfig->USBMODE.UsbMode.Ohci3 << 5) \
-    + (pConfig->USBMODE.UsbMode.Ohci4 << 6);
-
-  // Overwrite EHCI3/OHCI3 by XhciSwitch
-  if (pConfig->XhciSwitch) {
-    pConfig->USBMODE.UsbModeReg &= 0xCF;
-    pConfig->USBMODE.UsbModeReg |= 0x80;
-  } else {
-    pConfig->USBMODE.UsbModeReg &= 0x7F;
-#ifdef USB_LOGO_SUPPORT
-    if (pConfig->USBMODE.UsbMode.Ohci3) {
-      RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_Usbwakup2, AccWidthUint8, 0, 0x0B);
-    }
-#endif
-  }
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, 0, (pConfig->USBMODE.UsbModeReg));
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEE, AccWidthUint8, ~(BIT2), 0 );
-//  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, 0, (pConfig->USBMODE.UsbModeReg & ~( 0x15 << 1 )) + (( pConfig->USBMODE.UsbModeReg & 0x15 ) << 1 ) );
-
-//  if ( pConfig->XhciSwitch == 1 && pConfig->S3Resume == 0 && pConfig->S4Resume == 0  ) {
-//    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7) , BIT7);
-//    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5) , 0);
-//    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEE, AccWidthUint8, ~(BIT0 + BIT1 + BIT2), (BIT1 + BIT0 + BIT2) );
-//  }
-//  else {
-//    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7) , ~(BIT7));
-//  }
-//  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccWidthUint8, ~BIT6, 0);
-//  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + 0xF3, AccWidthUint8, ~BIT4, BIT4);
-//  SbStall (500);
-//  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + 0xF3, AccWidthUint8, ~BIT4, 0);
-
-#ifdef XHCI_SUPPORT
-#ifndef XHCI_INIT_IN_ROM_SUPPORT
-  if ( pConfig->XhciSwitch == 1 ) {
-    if ( pConfig->S3Resume == 0 ) {
-      XhciInitBeforePciInit (pConfig);
-    } else {
-      XhciInitIndirectReg ();
-    }
-  } else {
-    // for power saving.
-
-    // add Efuse checking for Xhci enable/disable
-    getEfuseStatus (&XhciEfuse);
-    if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
-      RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFBFF, 0x0);
-    }
-  }
-#endif
-#endif
-
-}
-
-/**
- * usbInitAfterPciInit - Config USB controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usbInitAfterPciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  if (IsSbA11 ()) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0x7F);
-  }
-
-  usb1EhciInitAfterPciInit (pConfig);
-  usb2EhciInitAfterPciInit (pConfig);
-  usb3EhciInitAfterPciInit (pConfig);
-  usb3OhciInitAfterPciInit (pConfig);
-  usb1OhciInitAfterPciInit (pConfig);
-  usb2OhciInitAfterPciInit (pConfig);
-  usb4OhciInitAfterPciInit (pConfig);
-  // Restore back
-  if (IsSbA11 ()) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, (pConfig->USBMODE.UsbModeReg));
-  }
-#ifdef XHCI_SUPPORT
-  if ( pConfig->XhciSwitch == 1 ) {
-    XhciInitAfterPciInit (pConfig);
-  }
-#endif
-
-  if ( pConfig->UsbPhyPowerDown ) {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, BIT0);
-  } else  {
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, 0);
-  }
-
-  if (IsSbA13Plus ()) {
-    //SB02643
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4, AccWidthUint8, ~BIT7, BIT7);
-    //RPR7.27 SB02686
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED, AccWidthUint8, ~BIT2, BIT2);
-  }
-}
-
-/**
- * usbOverCurrentControl - Config USB Over Current Control
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usbOverCurrentControl (
-  IN       AMDSBCFG* pConfig
-  )
-{
-
-#ifdef SB_USB1_OVER_CURRENT_CONTROL
-  RWPCI ((USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG58, AccWidthUint32 | S3_SAVE, 0xfff00000, SB_USB1_OVER_CURRENT_CONTROL & 0x000FFFFF);
-#endif
-
-#ifdef SB_USB2_OVER_CURRENT_CONTROL
-  RWPCI ((USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG58, AccWidthUint32 | S3_SAVE, 0xfff00000, SB_USB2_OVER_CURRENT_CONTROL & 0x000FFFFF);
-#endif
-
-#ifdef SB_USB3_OVER_CURRENT_CONTROL
-  RWPCI ((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG58, AccWidthUint32 | S3_SAVE, 0xffff0000, SB_USB3_OVER_CURRENT_CONTROL & 0x0000FFFF);
-#endif
-
-#ifdef SB_USB4_OVER_CURRENT_CONTROL
-  RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG58, AccWidthUint32 | S3_SAVE, 0xffffff00, SB_USB4_OVER_CURRENT_CONTROL & 0x000000FF);
-#endif
-
-#ifdef SB_XHCI0_OVER_CURRENT_CONTROL
-  RWXhci0IndReg ( SB_XHCI_IND_REG04, 0xFF00FFFF, (SB_XHCI0_OVER_CURRENT_CONTROL & 0xFF) << 16);
-#endif
-
-#ifdef SB_XHCI1_OVER_CURRENT_CONTROL
-  RWXhci1IndReg ( SB_XHCI_IND_REG04, 0xFF00FFFF, (SB_XHCI1_OVER_CURRENT_CONTROL & 0xFF) << 16);
-#endif
-
-}
-
-/**
- * usbInitLate - Config USB controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usbInitLate (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  if (pConfig->S4Resume) {
-    //RWPCI (0x9004, AccWidthUint8, 0, 0x10);
-    //RWPCI (0x9804, AccWidthUint8, 0, 0x10);
-    //RWPCI (0xA504, AccWidthUint8, 0, 0x10);
-    //RWPCI (0xB004, AccWidthUint8, 0, 0x10);
-    //RWPCI (0x903C, AccWidthUint8, 0, 0x12);
-    //RWPCI (0x983C, AccWidthUint8, 0, 0x12);
-    //RWPCI (0xA53C, AccWidthUint8, 0, 0x12);
-    //RWPCI (0xB03C, AccWidthUint8, 0, 0x12);
-  }
-#ifdef XHCI_SUPPORT
-  if ( pConfig->XhciSwitch == 1 ) {
-    XhciInitLate (pConfig);
-  }
-#endif
-  SbEnableUsbIrq1Irq12ToPicApic ();
-  usbOverCurrentControl (pConfig);
-}
-
-/**
- * usb1EhciInitAfterPciInit - Config USB1 EHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb1EhciInitAfterPciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddDeviceId;
-  ddDeviceId = (USB1_EHCI_BUS_DEV_FUN << 16);
-  EhciInitAfterPciInit (ddDeviceId, pConfig);
-}
-
-/**
- * usb2EhciInitAfterPciInit - Config USB2 EHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb2EhciInitAfterPciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddDeviceId;
-  ddDeviceId = (USB2_EHCI_BUS_DEV_FUN << 16);
-  EhciInitAfterPciInit (ddDeviceId, pConfig);
-}
-
-/**
- * usb3EhciInitAfterPciInit - Config USB3 EHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-
-VOID
-usb3EhciInitAfterPciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddDeviceId;
-  ddDeviceId = (USB3_EHCI_BUS_DEV_FUN << 16);
-  EhciInitAfterPciInit (ddDeviceId, pConfig);
-}
-
-
-VOID
-EhciInitAfterPciInit (
-  IN       UINT32 Value,
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddBarAddress;
-  UINT32  ddVar;
-  UINT32  ddDrivingStrength;
-  UINT32  ddPortDrivingStrength;
-  UINT32  portNumber;
-  UINT32  port;
-  ddDrivingStrength = 0;
-  portNumber = 0;
-  //Get BAR address
-  ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);
-  if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
-    //Enable Memory access
-    RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
-    if (pConfig->BuildParameters.EhciSsid != 0 ) {
-      RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid);
-    }
-    //USB Common PHY CAL & Control Register setting
-    ddVar = 0x00020F00;
-    WriteMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
-    // RPR IN AND OUT DATA PACKET FIFO THRESHOLD
-    // EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
-    RWMEM (ddBarAddress + SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
-    // RPR EHCI Dynamic Clock Gating Feature
-    // RPR Enable Global Clock Gating (BIT14)
-    RWMEM (ddBarAddress + SB_EHCI_BAR_REGBC, AccWidthUint32, ~(BIT12 + BIT14), BIT12 + BIT14);
-    RWMEM (ddBarAddress + SB_EHCI_BAR_REGB0, AccWidthUint32, ~BIT5, BIT5);
-    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint16, ~BIT12, BIT12);
-    // RPR Enable adding extra flops to PHY rsync path
-    // Step 1:
-    //  EHCI_BAR 0xB4 [6] = 1
-    //  EHCI_BAR 0xB4 [7] = 0
-    //  EHCI_BAR 0xB4 [12] = 0 ("VLoad")
-    //  All other bit field untouched
-    // Step 2:
-    //  EHCI_BAR 0xB4[12] = 1
-    //RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~(BIT6 + BIT7 + BIT12), 0x00);
-    //RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12);
-
-    // RPR7.8 USB 2.0 Ports Driving Strength
-    // Step1 is done by default
-    // Add support USBx_EHCI_DRIVING_STRENGTH port4 is at [19:16] and  port0 is [3:0]; 4 bits for per port, [3] is enable,[2:0] is driving strength.
-    // For Cobia, USB3_EHCI_DRIVING_STRENGTH = 0x00CC
-#ifdef USB1_EHCI_DRIVING_STRENGTH
-    if (Value == (USB1_EHCI_BUS_DEV_FUN << 16)) {
-      ddDrivingStrength = USB1_EHCI_DRIVING_STRENGTH;
-      portNumber = 5;
-    }
-#endif
-#ifdef USB2_EHCI_DRIVING_STRENGTH
-    if (Value == (USB2_EHCI_BUS_DEV_FUN << 16)) {
-      ddDrivingStrength = USB2_EHCI_DRIVING_STRENGTH;
-      portNumber = 5;
-    }
-#endif
-#ifdef USB3_EHCI_DRIVING_STRENGTH
-    if (Value == (USB3_EHCI_BUS_DEV_FUN << 16)) {
-      ddDrivingStrength = USB3_EHCI_DRIVING_STRENGTH;
-      portNumber = 4;
-    }
-#endif
-    if (portNumber > 0) {
-      for (port = 0; port < portNumber; port ++) {
-        ddPortDrivingStrength = (ddDrivingStrength >> (port * 4)) & 0x0F;
-        if (ddPortDrivingStrength & BIT3) {
-          ddPortDrivingStrength &= 0x7;
-          RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~ (BIT16 + BIT15 + BIT14 + BIT13 + BIT12 + BIT2 + BIT1 + BIT0), (port << 13) + ddPortDrivingStrength);
-          RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12);
-        }
-      }
-    }
-    // Step2
-    RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12);
-    // Step3
-    if (IsSbA11 ()) {
-      RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, (UINT32) (~ 0x00000f00), 0x00000000);
-      RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, (UINT32) (~ 0x0000ff00), 0x00001500);
-    } else {
-      RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, (UINT32) (~ 0x00000f00), 0x00000200);
-      RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, (UINT32) (~ 0x0000ff00), 0x00000f00);
-    }
-    //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support
-    RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x01 << 6)), (0x01 << 6));
-    //RPR 7.13 EHCI Async Park Mode
-    //Set EHCI_pci_configx50[11:8]=0x1
-    //Set EHCI_pci_configx50[15:12]=0x1
-    //Set EHCI_pci_configx50[17]=0x1
-    RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x0F << 8)), (0x01 << 8));
-    RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x0F << 12)), (0x01 << 12));
-    RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x01 << 17)), (0x01 << 17));
-    //RPR Enabling EHCI Async Stop Enhancement
-    //Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement
-    RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x01 << 29)), (0x01 << 29));
-    //RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFF7F0FFF, 0x20221140);
-    // RPR recommended setting "EHCI Advance PHY Power Savings"
-    // Set EHCI_pci_configx50[31]='1'
-    // Fix for EHCI controller driver  yellow sign issue under device manager
-    // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1
-    RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFF, BIT15);
-    // ENH246436: Disable USB data cache to resolve USB controller hang issue with Lan adaptor.
-    // EHCI PCI config register 50h bit 26 to `1'.
-    if (pConfig->EhciDataCacheDis) {
-      RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFF, BIT10);
-    }
-
-    if (IsSbA13Plus ()) {
-      //RPR 7.25  SB02674
-      RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint16 | S3_SAVE, (UINT16)0x5FFF, BIT13 + BIT15);
-      //RPR 7.26  SB02684
-      RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, ~ (BIT3), BIT3);
-      //RPR 7.26  SB02687
-      RWPCI ((UINT32) Value + SB_EHCI_REG54 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFC, BIT0 + BIT1);
-      //RPR 7.28  SB02700
-      RWPCI ((UINT32) Value + SB_EHCI_REG54 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFB, BIT2);
-      //RPR 7.29  SB02703
-      RWPCI ((UINT32) Value + SB_EHCI_REG54 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFF7, BIT3);
-    }
-
-    // RPR USB Delay A-Link Express L1 State
-    // RPR PING Response Fix Enable EHCI_PCI_Config  x54[1] = 1
-    // RPR Enable empty list mode. x54[3]
-    // RPR Enable "L1 Early Exit" functionality. 0x54 [6:5] = 0x3 0x54 [9:7] = 0x4
-    // RPR EHCI PING Response Fix Enable 0x54 [1] = 0x1
-    RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT0, 0x0000026b);
-    if ( pConfig->BuildParameters.UsbMsi) {
-      RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~BIT6, 0x00);
-    }
-    if (IsSbA12Plus ()) {
-      // RPR 7.24 Long Delay on Framelist Read Causing EHCI DMA to Address 0 - Fix
-      // RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT13, BIT13);
-      // RPR 7.25 LS connection can't wake up system from S3/S4/S5 when EHCI owns the port - Fix
-      RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT4, BIT4);
-      // RPR 7.30 EHCI lMU Hangs when Run/Stop is Set First and PDC is Enabled Near End uFrame 7 - Fix Enable
-      RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT11, BIT11);
-    }
-    // ENH244924: Platform specific Hudson-2/3 settings for all Sabine Platforms
-    // EHCI_PCI_Config 0x50[21]=1
-    // EHCI_PCI_Config 0x54[9:7] = 0x4
-    if ( IsGCPU () ) {
-      RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x01 << 21)), (0x01 << 21));
-      RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x07 << 7)), (0x04 << 7));
-    }
-//    RWMEM (ddBarAddress + SB_EHCI_BAR_REGB0, AccWidthUint32, ~BIT5, BIT5);
-  } else {
-    // Fake Bar
-    ddBarAddress = 0x58830000;
-    WritePCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);
-    //Enable Memory access
-    RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
-    // RPR Enable Global Clock Gating (BIT14)
-    RWMEM (ddBarAddress + SB_EHCI_BAR_REGBC, AccWidthUint32, ~(BIT12 + BIT14), BIT12 + BIT14);
-    RWMEM (ddBarAddress + SB_EHCI_BAR_REGB0, AccWidthUint32, ~BIT5, BIT5);
-    RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, 0);
-//    RWMEM (ddBarAddress + SB_EHCI_BAR_REGB0, AccWidthUint32, ~BIT5, BIT5);
-  }
-}
-
-/**
- * usb1OhciInitAfterPciInit - Config USB1 OHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb1OhciInitAfterPciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddDeviceId;
-  ddDeviceId = (USB1_OHCI_BUS_DEV_FUN << 16);
-  OhciInitAfterPciInit (ddDeviceId, pConfig);
-  RWPCI ((USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG78, AccWidthUint32 | S3_SAVE, 0xffffffff, BIT28 + BIT29);
-}
-
-/**
- * usb2OhciInitAfterPciInit - Config USB2 OHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb2OhciInitAfterPciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddDeviceId;
-  ddDeviceId = (USB2_OHCI_BUS_DEV_FUN << 16);
-  OhciInitAfterPciInit (ddDeviceId, pConfig);
-}
-
-/**
- * usb3OhciInitAfterPciInit - Config USB3 OHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb3OhciInitAfterPciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddDeviceId;
-  ddDeviceId = (USB3_OHCI_BUS_DEV_FUN << 16);
-  OhciInitAfterPciInit (ddDeviceId, pConfig);
-}
-
-/**
- * usb4OhciInitAfterPciInit - Config USB4 OHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb4OhciInitAfterPciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddDeviceId;
-  ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
-  OhciInitAfterPciInit (ddDeviceId, pConfig);
-  if (pConfig->BuildParameters.Ohci4Ssid != 0 ) {
-    RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid);
-  }
-}
-
-VOID
-OhciInitAfterPciInit (
-  IN       UINT32 Value,
-  IN       AMDSBCFG* pConfig
-  )
-{
-#ifdef SB_USB_BATTERY_CHARGE_SUPPORT
-  RWPCI ((UINT32) Value + SB_OHCI_REG40 + 6, AccWidthUint8 | S3_SAVE, 0xFF, 0x1F);
-#endif
-  // Disable the MSI capability of USB host controllers
-  RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
-  if ((IsSbA11 ()) || (IsSbA12 ())) {
-    RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~(BIT0 + BIT5 + BIT12), 0);
-  } else {
-    RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~(BIT0 + BIT5 + BIT12), BIT0);
-  }
-  // RPR USB SMI Handshake
-  RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00);
-  if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
-    if ( pConfig->BuildParameters.OhciSsid != 0 ) {
-      RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid);
-    }
-  }
-  //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
-  //OHCI 0_PCI_Config 0x50[30] = 1
-  RWPCI ((UINT32) Value + SB_OHCI_REG50 + 3, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);
-  // RPR L1 Early Exit
-  // RPR Set OHCI Arbiter Mode.
-  // RPR Set Enable Global Clock Gating.
-  RWPCI ((UINT32) Value + SB_OHCI_REG80, AccWidthUint8 | S3_SAVE, ~(BIT0 + BIT4 + BIT5 + BIT6 + BIT7), BIT0 + BIT4 + BIT7);
-  //   SB02698
-  RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~BIT0, 0);
-  // RPR 7.21 OHCI Arbiter Mode
-  // A13 Remove Arbitor Reset
-  if ( IsSbA12Plus () ) {
-    RWPCI ((UINT32) Value + SB_OHCI_REG80, AccWidthUint16 | S3_SAVE, ~(BIT4 + BIT5 + BIT8), (BIT4 + BIT5 + BIT8));
-  } else {
-    RWPCI ((UINT32) Value + SB_OHCI_REG80, AccWidthUint16 | S3_SAVE, ~(BIT4 + BIT5), (BIT4));
-  }
-  // RPR Enable OHCI SOF Synchronization.
-  // RPR Enable OHCI Periodic List Advance.
-  RWPCI ((UINT32) Value + SB_OHCI_REG50 + 2, AccWidthUint8 | S3_SAVE, ~(BIT3 + BIT4), BIT3 + BIT4);
-  if ( pConfig->BuildParameters.UsbMsi) {
-    RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);
-    RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5);
-  }
-  //7.23  USB1.1 full-speed false crc errors detected. Issue - fix enable
-  if ( IsSbA12Plus () ) {
-    RWPCI ((UINT32) Value + SB_OHCI_REG80, AccWidthUint32 | S3_SAVE, (UINT32) (~(0x01 << 10)), (UINT32) (0x01 << 10));
-  }
-}
-
-
-UINT32
-SetEhciPllWr (
-  IN       UINT32 Value,
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT32  ddRetureValue;
-  UINT32  ddBarAddress;
-  UINT16  dwVar;
-  UINT16  dwData;
-  UINT8  portSC;
-  ddRetureValue = 0;
-  dwData = 0;
-  // Memory, and etc.
-  //_asm { jmp $};
-  RWPCI ((UINT32) Value + 0xC4, AccWidthUint8, 0xF0, 0x00);
-  RWPCI ((UINT32) Value + 0x04, AccWidthUint8, 0xFF, 0x02);
-  // Get Bar address
-  ReadPCI ((UINT32) Value + 0x10, AccWidthUint32, &ddBarAddress);
-  for (portSC = 0x64; portSC < 0x75; portSC += 0x04 ) {
-    // Get OHCI command registers
-    ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwVar);
-    if ( dwVar & BIT6 ) {
-      ddRetureValue = ddBarAddress + portSC;
-      RWMEM (ddBarAddress + portSC, AccWidthUint16, ~BIT6, 0);
-      for (;;) {
-        SbStall (5);
-        ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwData);
-        if (dwData == 0x1005) break;
-      }
-      dwData = 0;
-    }
-  }
-  return ddRetureValue;
-}
-
-#ifdef XHCI_SUPPORT
-/*
-VOID
-XhciInitIndirectReg (
-  )
-{
-  UINT32 ddDrivingStrength;
-  UINT32 port;
-  ddDrivingStrength = 0;
-  port = 0;
-#ifdef SB_USB_BATTERY_CHARGE_SUPPORT
-  RWXhciIndReg ( 0x40000018, 0xFFFFFFFF, 0x00000030);
-#endif
-//
-// RPR SuperSpeed PHY Configuration (adaptation mode setting)
-//
-  RWXhciIndReg ( SB_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021);
-  RWXhciIndReg ( SB_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021);
-//
-// RPR SuperSpeed PHY Configuration (CR phase and frequency filter settings)
-//
-  RWXhciIndReg ( SB_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A);
-  RWXhciIndReg ( SB_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A);
-
-//
-// RPR BLM Meaasge
-//
-  RWXhciIndReg ( SB_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000);
-
-#ifdef USB3_EHCI_DRIVING_STRENGTH
-//
-// RPR 8.13 xHCI USB 2.0 PHY Settings
-// Step 1 is done by hardware default
-// Step 2
-  for (port = 0; port < 4; port ++) {
-    ddDrivingStrength = (USB3_EHCI_DRIVING_STRENGTH >> (port * 4)) & 0xF;
-    if (ddDrivingStrength & BIT3) {
-      ddDrivingStrength &= 0x07;
-      if (port < 2) {
-        RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0E78, (port << 13) + ddDrivingStrength);
-        RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
-      } else {
-        RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0E78, ((port - 2) << 13) + ddDrivingStrength);
-        RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
-      }
-    }
-  }
-#endif
-
-#ifdef USB_LOGO_SUPPORT
-//for D3 USB LOGO [6:0]= 4; [8:7] = 3; [12] = 0; [16:13] port;
-  for (port = 0; port < 4; port ++) {
-    if (port < 2) {
-      RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0E00, (port << 13) + 0x184 );
-    } else {
-      RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0E00, ((port - 2) << 13) + 0x184 );
-    }
-  }
-#endif
-
-// Step 3
-  if (IsSbA11 ()) {
-    RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x00 << 8)));
-    RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x15 << 8)));
-  } else {
-    RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)));
-    RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)));
-  }
-}
-*/
-
-VOID
-XhciA12Fix (
-  VOID
-  )
-{
-//
-// 8.14 PLUG/UNPLUG of USB 2.0 devices make the XHCI USB 2.0 ports unfunctional - fix enable
-// ACPI_USB3.0_REG 0x20[12:11] = 2'b11
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~((UINT32) (0x3 << 11)), (UINT32) (0x3 << 11));
-//
-// 8.15 XHC 2 USB2 ports interactional issue - fix enable
-// ACPI_USB3.0_REG 0x20[16] = 1'b1
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16));
-//
-// 8.16 xHCI USB 2.0 Ports Suspend Enhancement
-// ACPI_USB3.0_REG 0x20[15] = 1'b1
-//
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~((UINT32) (0x1 << 15)), (UINT32) (0x1 << 15));
-//
-// 8.17 XHC HS/FS IN Data Buffer Underflow issue - fix enable
-// ACPI_USB3.0_REG 0x20[20:18] = 0x7
-//
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~((UINT32) (0x7 << 18)), (UINT32) (0x7 << 18));
-//
-// 8.18 Allow XHCI to Resume from S3 Enhancement
-// ACPI_USB3.0_REG 0x98[19] = 1'b1
-//
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccWidthUint32, ~((UINT32) (0x1 << 19)), (UINT32) (0x1 << 19));
-//
-// 8.19 Assign xHC1 ( Dev 16 function 1) Interrupt Pin register to INTB#
-// ACPI_PMIO_F0[18] =1
-//
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint32, ~((UINT32) (0x1 << 18)), (UINT32) (0x1 << 18));
-//
-// 8.20 Allow B-Link Clock Gating when EHCI3/OHCI3 is only Controller Enabled
-// ACPI_PMIO_F0[13] =1
-//
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint32, ~((UINT32) (0x1 << 13)), (UINT32) (0x1 << 13));
-//
-// 8.21 Access register through JTAG fail when switch from XHCI to EHCI/OHCI - Fix enable
-// ACPI_PMIO_F0[17] =1
-//
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint32, ~((UINT32) (0x1 << 17)), (UINT32) (0x1 << 17));
-//
-// 8.22 USB leakage current on differential lines when ports are switched to XHCI - Fix enable
-// ACPI_PMIO_F0[14] =1
-//
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint32, ~((UINT32) (0x1 << 14)), (UINT32) (0x1 << 14));
-//  RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_xHC0Pme, AccWidthUint16, 0, 0x0B0B);
-//
-// 8.26 Fix for Incorrect Gated Signals in xhc_to_s5
-// ACPI_PMIO_F0[16] =1
-//
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16));
-}
-
-VOID
-XhciInitBeforePciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  UINT16  BcdAddress;
-  UINT16  BcdSize;
-  UINT16  AcdAddress;
-  UINT16  AcdSize;
-  UINT16  FwAddress;
-  UINT16  FwSize;
-  UINTN   XhciFwStarting;
-  UINT32  SpiValidBase;
-  UINT32  RegData;
-  UINT16  i;
-
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0x00000000, 0x00400700);
-  SbStall (20);
-//
-// Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
-//
-  GetRomSigPtr (&XhciFwStarting);
-
-  if (XhciFwStarting == 0) {
-    return;
-  }
-
-  XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
-  if (IsLpcRom ()) {
-  //XHCI firmware re-load
-    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, ~BIT2, (BIT2 + BIT1 + BIT0));
-    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, 0x00000FFF, (UINT32) (XhciFwStarting));
-  }
-//
-// RPR Enable SuperSpeed receive special error case logic. 0x20 bit8
-// RPR Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
-// Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
-//
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, 0xFFFFF8FF, 0x00000700);
-//
-// RPR SuperSpeed PHY Configuration (adaptation timer setting)
-//
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
-  //RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
-
-//
-// Step 1. to enable Xhci IO and Firmware load mode
-//
-#ifdef XHCI_SUPPORT_ONE_CONTROLLER
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000001);
-#else
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000003);
-#endif
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xEFFFFFFF, 0x10000000);
-
-//
-// Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
-//
-
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccWidthUint32, 0x00000000, (SPI_HEAD_LENGTH << 16));
-
-  BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
-  BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccWidthUint16, 0x0000, BcdAddress);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccWidthUint16, 0x0000, BcdSize);
-
-  AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
-  AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccWidthUint16, 0x0000, AcdAddress);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccWidthUint16, 0x0000, AcdSize);
-
-  SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccWidthUint32, 0x00000000, SpiValidBase);
-
-    //
-    // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
-    //
-  for (i = 0; i < SPI_HEAD_LENGTH; i++) {
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + i));
-  }
-
-  for (i = 0; i < BcdSize; i++) {
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + i));
-  }
-
-  for (i = 0; i < AcdSize; i++) {
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + i));
-  }
-
-//
-// Step 3. to enable the instruction RAM preload functionality.
-//
-  FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
-  FwAddress += 2;
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccWidthUint16, 0x0000, FwAddress);
-
-  FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccWidthUint16, 0x0000, FwSize);
-
-    //
-    // Set the starting address offset for Instruction RAM preload.
-    //
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccWidthUint16, 0x0000, 0);
-
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, BIT29);
-
-  for (;;) {
-    ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
-    if (RegData & BIT30) break;
-  }
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, 0);
-
-//
-// Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
-//
-
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PLL_RESET, 0); //Release U3PLLreset
-  for (;;) {
-    ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
-    if (RegData & U3PLL_LOCK) break;
-  }
-
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PHY_RESET, 0); //Release U3PHY
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3CORE_RESET, 0); //Release core reset
-
-// RPR 8.8 SuperSpeed PHY Configuration, it is only for A11.
-  if (IsSbA11 ()) {
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
-  }
-
-  XhciInitIndirectReg ();
-
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5), 0); // Disable Device 22
-  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7), BIT7); // Enable 2.0 devices
-  if (!(pConfig->S4Resume)) {
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI
-  }
-//
-// Step 5.
-//
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18);
-
-// Step 5.
-  if (IsSbA12Plus ()) {
-    XhciA12Fix ();
-  }
-  //8.22 UMI Lane Configuration Information for XHCI Firmware to Calculate the Bandwidth for USB 3.0 ISOC Devices
-  if (!(IsUmiOneLaneGen1Mode ())) {
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~(BIT25 + BIT24), BIT24);
-  }
-}
-
-VOID
-XhciInitAfterPciInit (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  // RPR8.12 Block Write to DID & SID to pass DTM
-  RWXhciIndReg ( SB_XHCI_IND_REG04, ~BIT8, BIT8);
-
-  if (IsSbA13Plus ()) {
-    //8.23 FS/LS devices not functional after resume from S4 fix enable (SB02699)
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~(BIT22), BIT22);
-  }
-  //8.24 XHC USB2.0 Hub disable issue fix enable (SB02702)
-  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint32, ~(BIT20), BIT20);
-}
-
-VOID
-XhciInitLate (
-  IN       AMDSBCFG* pConfig
-  )
-{
-  //OBS221599: USB 3.0 controller shows bang in Windows Device Manager
-  UINT8  Data;
-  if ( IsSbA11 () ) {
-    Data = 0xB5; //
-    WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
-    Data = 0x12; //
-    WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
-  }
-  if (pConfig->S4Resume) {
-    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI
-    SbFlashUsbSmi ();
-  }
-}
-#endif
author	Arthur Heymans <arthur@aheymans.xyz>	2022-03-23 22:03:24 +0100
committer	Arthur Heymans <arthur@aheymans.xyz>	2022-05-11 05:59:06 +0000
commit	e2ffcc6068cb278689fc656742fa61a38ebe9fe4 (patch)
tree	e8c3917de38c3fe8ee01f5e0f8a4479f4ad3d318 /src
parent	3a077965dedfc757d05ee88561012981da591677 (diff)