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Change-Id: I6d161e9e44ebd284e229ea38b6e23d571aa7bf1e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Change-Id: I5caa6163e5471feda170600c21320821f4286c65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch also add new SKL PCH-H device id's in soc platform reporting and
common lpc driver.
BUG=None
TEST=Booted kabylake RVP11 with HM175 SKL PCH-H and verified the device id
in serial logs.
Change-Id: I8c04bf8d9c27caad800427a5c29da869da1d445d
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ storm after S3 resume and hence
configuring GPP_D9 and GPP_D10 to use PLTRST.
BUG=b:119202293
TEST=none
Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29538
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPP_C11 (FPMCU_INT_L) was set to DEEP, causing problems with S3.
Changed GPP_C11 configuration to use PLTRST instead.
BUG=b:114196791
TEST=Build, flash, boot nocturne, log in to kernel and execute
the following two commands and verify it passes :
echo 0 > /var/lib/power_manager/suspend_to_idle && restart powerd
sudo suspend_stress_test -c 2
Change-Id: I008532fce963c51a435378001440ac72b5ebfffc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure
PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default
100ms to 10ms to improve cold boot and S3 resume performance.
BUG=b:118676361
CQ-DEPEND=CL:*703187
TEST=Verified system_resume_firmware_ec time reduction.
Change-Id: I41b8268c752573d828e31a1d94d3f175aa3cc145
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29485
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure
PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default
100ms to 10ms to improve cold boot and S3 resume performance.
BUG=b:118676361
CQ-DEPEND=CL:*703187
TEST=Verified system_resume_firmware_ec time reduction.
Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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add the memory parts as ram id 10:
hynix_dimm_H5ANAG6NAFR-UHC
BUG=b:113983573
BRANCH=Nami
TEST=emerge-nami coreboot chromeos-bootimage
Change-Id: I137259b88f39779768a58959a2dcc565645eee6d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change allows to redirect coreboot console output to COM2 by
setting appropriate UART index in Console menu in Kconfig.
Change is helpful for users which would like to use COM1 port for
other purposes, because COM1 is the only port with hardware flow
control.
Change-Id: I39f88d7e7794f603775a985afe07fef349172e5f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/29255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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In case the function pointer isn't set return an error.
Change-Id: I9de300f651ac93889dafa7377c876bf5ae2c50cc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/29531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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VB2_LIB will be used across all stages to hash data. Add it to postcar
stage sources so that it is compiled if postcar exists. In this way the
new function tpm_measure_region() introduced in commit
61322d7 (security/tpm: Add function to measure a region device)
can be used in every stage.
Change-Id: I933d33b0188d1b123bb4735722b6086e7786624f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/29465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Fixes building vb2lib for postcar. Since postcar is an x86ism, add the
Kconfig options only for x86.
Change-Id: Ib92436bc7270c24689dcf01a47f0c6fe7661814b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29395
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Icelake specific CPU, System Agent, PCH, IGD device IDs.
Change-Id: I2c398957ffbc9bb0e5b363740d99433075ca66a3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This mainboard is based on mc_apl1. In a first step, it concerns a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl4 mainboard will follow in separate commits.
Change-Id: I3dfdccc8198f3a23a45d319ede6080803a46f7f6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This mainboard variant requires GPIO adaptations to match the hardware.
Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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It's not Python 3 compatible.
Change-Id: Ibaad2c31bb6494652ce650ab7c1064728ec5fe80
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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* Move all implementations to into common folder.
* Add rtc.c for rtc based functions
Allows all Intel based platforms to use VBOOT_VBNV_CMOS.
Change-Id: Ia494e6d418af6f907c648376674776c54d95ba71
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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RCBA address numbers in comments looks wrong and confusing. Let's fix
them.
This is a cosmetic change since no actual data is added or removed.
Change-Id: I0e521acdac17959586bc0af7d8a2f7182f1e6721
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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See also commit 4ad1446b with Change-Id
I036208a111d009620d8354fa9c97688eb4e872ad ("Fix non-local header treated
as local").
Change-Id: Idea19b52198e6f46b0da6022558a46246a52f2e7
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29501
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia997c5188aef0c18d871658209c2d5f718ee2a19
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This structure was defined but never used. Let's use it.
Change-Id: I73baf428a7300e64fa486699e82ef62c6a53ea60
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Disable I2C7 because there is no device connected.
Change-Id: Ie9877d40b06f4a849163a873fd308ff03995fcdc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Enable all PCIe root ports for this mainboard.
Change-Id: I62c7ba5048b4c2288bb502a78b9621edda333f2a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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There is no device on I2C0 which requires a lower clock rate.
Change-Id: Ib9ad4d9026267d2079e95245994d84c163b28dbb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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All PCIe root ports of this mainboard do not have an associated CLKREQ
signal. Therefore the ports are marked with "CLKREQ_DISABLED".
Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This mainboard variant requires GPIO adaptations to match the hardware.
Change-Id: I4ba475e7d387f46ed5f41b7a691c7933edbc50c5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This change adds a sku_id() function that returns a static value to
differentiate the sarien and arcada boards.
Change-Id: I1fecc675573a6aece7188aae9370733068d45dbf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29486
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There some files that do have at least 1 line over the 80 characters limit.
Find and fix them.
BUG=b:117950052
TEST=Build grunt.
Change-Id: I1083a7559919e05a3e3a2dac99f571c161bb4c27
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Refer to CL:1043916
BUG=none
BRANCH=none
TEST=none
Change-Id: I3fbbbcac334646f68b8b9fd38fbb529d9e833581
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Kabylake RVP11 uses FSPT to support Intel security features like
bootguard verify boot and measured boot.
This patch add FSP CAR support for kabylake by programming tempraminit
parameters in fspcar.c and also add FSP_T_XIP default if FSP_CAR is
selected in order to relocate FSPT binary while adding it in CBFS so that
it can be executed in place.
BUG=None
TEST=Build and Boot to UEFI payload on kabylake RVP11 board and verified
for successful FSP CAR setup.
Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.
BUG=b:118484178
TEST=Build AMD Bettong.
Change-Id: I4167c7eeb9339937b064e81e615ceb65f4689082
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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generation
This changes uses drivers/intel/wifi chip for CNVi device to ensure that:
1. Correct device name shows in ACPI name space
2. Correct wake up shows in cat /proc/acpi/wakeup
3. Remove cnvi.asl from soc/intel/cannonlake
Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change provides an interface for apollolake to set TCC before
BIOS reset complete happens in romstage.
With this change, we can add code to update Tcc in devicetree.
BUG=b:117789732
TEST=Match the result from TAT UI
Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Change-Id: I2b3168c600a81502f9cd1ff3203c492cf026e532
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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A very common pattern in drivers is that we need to wait for a condition
to become true (e.g. for a lock bit in a PLL status register to become
set), but we still want to have a maximum timeout before we treat it as
an error. coreboot uses the stopwatch API for this, but it's still a
little verbose for the most simple cases. This patch introduces two new
helper macros that wrap this common application of the stopwatch API in
a single line: wait_ms(XXX, YYY) waits for up to XXX milliseconds to see
if the C condition 'if (YYY)' becomes true. The return value is 0 on
failure (i.e. timeout expires without the condition becoming true) and
the amount of elapsed time on success, so it can be used both in a
boolean context and to log the amount of time waited.
Replace the custom version used in an MTK ADC driver with this new
generic version.
Change-Id: I6de38ee00673c46332ae92b8a11099485de5327a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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If remaining charge is more than x% of the full capacity, the
remaining charge is raised to the full capacity before it's
reported to the rest of the system.
Some batteries don't update full capacity timely or don't update it
at all. On such systems, compensation is required to guarantee
the remaining charge will be equal to the full capacity eventually.
On some systems, Rohm charger generates audio noise when the battery
is fully charged and AC is plugged. A workaround is to do charge-
discharge cycles between 93 and 100%. On such systems, compensation
was also applied to mask this cycle from users.
This used to be done in ACPI, thus, all software components except EC
was able to see the compensated charge. This patch is part of the
effort of moving the logic to EC. With this and the EC changes, EC
can see what the rest of the system sees, thus, can control LEDs
synchronously (to the display percentage).
Another rationale of this move is EC can perform more granular and
precise compensation than ACPI since it has more knowledge about the
battery and the charger.
CQ-DEPEND=CL:1312204
BUG=b:109954565,b:80270446,chromium:899120
BRANCH=none
TEST=Verify charge LED changes to white (full) on Sona synchronously
to the display percentage.
TEST=Verify charge LED changes to blinking white (low) on Sona
within 30 seconds synchronously to the display percentage.
Change-Id: I0b51911b90dc2e7fcf5c730c54d9fda1fea76aa9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/29441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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It's more theoretical, but lest somebody calls extract_string()
with too large a length...
Change-Id: I3934bd6965318cdffe5c636b01b3e0c4426e8d1d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #1374795
Reviewed-on: https://review.coreboot.org/28659
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are functions within heapmanager.c that have a space between the
function name and open parenthesis. Remove these spaces.
BUG=b:117950051
TEST=build grunt.
Change-Id: I2120d9d5f663453b6201d1872f29c6dc4abd6191
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29230
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since S3 resume sometimes breaks when trying to find the wakeup vector,
it is useful to log whether it errors or not. Since it is an error,
print it as such.
Change-Id: Ib006c4a213c0da180018e5fbf7a47d6af66f8bc4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Some variants of nami will have a fingerprint MCU.
BUG=b:118503113
BRANCH=Nami
TEST=None (build and boot, but no hw yet)
Change-Id: I446dc09cdf7f84a801723cb403d2de80e0997c65
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TEST=Make the printk reachable, check with
`strings build/cbfs/fallback/romstage.elf | grep lowest`
that this patch changes "MHzas" to "MHz as".
Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/29346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Marvell is the chip company, Marvel makes comic books.
Change-Id: I437ac0d4fc706fbb62a0a74ca74a197dba4499fb
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/29347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.
BUG=b:118484178
TEST=Build and boot grunt.
Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF#
set to high more than 10 ms, so force RESET#(GPP_D21) to low at
bootblock stage to match the sequence.
BUG=N/A
TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB
devices through lsusb.
Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: I42a33ffb66ffa2f938f85484ffc3a0d3788816b3
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/28837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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soc_rtc_init() is executed in ramstage
The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC
init from ramstage to romstage.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/29397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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PCH ISH enabled/disabled in FSP memory init UPD, it will be match the
setting in ISH device on/off in devicetree.cb.
BUG=N/A
TEST=Build and pass on whiskey lake rvp platform.
Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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This change removes the function defintions from variant
so that the weak definition in baseboard can be used.
Refer to CL:813944.
BUG=none
BRANCH=master
TEST=Build and boot on DUT
Change-Id: I561414fcc94e3c812bb88730df9b94e332c61781
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Update GPP_D9 to fix audio jack can't detect issue.
BUG=b:118393646
BRANCH=master
TEST=Verify audio jack can auto detect.
Change-Id: I87d24ed294c1ddc59bbd6ba9194c76d1f66413f3
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This Phase #2 follows the CL done on Phase #1 (Change-Id: I0236e0960cd)
Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29369
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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IORR MTRR definitions renamed to avoid collision
between <cpu/amd/mtrr.h> and <AGESA.h>.
Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29352
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use GPIO_134 as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.
BRANCH=none
BUG=crbug:896347, b:118443377
CQ-DEPEND=CL:1298699
TEST=verify sensor events coming in on a reworked board
with companion EC and kernel patches
Change-Id: I41333cabe97bc8b0d59e19d84366f2ea2a59e026
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/29278
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Several FSP silicon init UPD have been moved to memory init stage, modify
the coreboot accordingly. The UPDs below are affected:
SkipMpInit
VtdBaseAddress
VtdDisable
X2ApicOptOut
BUG=N/A
TEST=Build pass with FSP revision 7.0.47.50.
Change-Id: Ic0416dcd9ea1fe063cdd0c2f27257cd4cb4ba7e8
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29260
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
SBI is runtime service for OS. For an introduction, please refer to
https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md
Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Each stage performs some basic initialization (stack, HLS etc) and then
call smp_pause to enter the single-threaded state. The main work of each
stage is executed in a single-threaded state, and the multi-threaded
state is restored by call smp_resume while booting the next stage.
Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
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See https://doc.coreboot.org/arch/riscv/ we know that we need to execute
smp_pause at the start of each stage and smp_resume at the end of each
stage.
Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
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Add option for Nanya NT6CL256T32CM-H1 part.
Add comments to indicate total memory size for convenience.
BUG=b:118624505
BRANCH=master
TEST=none
Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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|
Change-Id: Ic08b191ee4dbcc56eb482601aa268394545936ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29292
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29285
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29103
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After a {break,return}, "else" is generally not needed.
Change-Id: I6145424ef8ffe6854c18c1d885f579d37853a70c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29267
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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After a {break,return}, "else" is generally not needed.
Change-Id: Id55af179f63316f7218e93978628cbe05e94e0aa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Using a conditional statement to return 0 or 1 depending on a logic
value is unnecessarily complex.
Change-Id: I449ce2b71b72374de5ec4986f9cc9f91a67856ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29265
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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There are some small mistakes in these recently-added mainboards:
- board_info.txt: Lists board socket incorrectly.
- cmos.default: Loglevel was decreased some time ago.
- devicetree.cb: Spelling mistake.
- Kconfig: Mainboard name does not have a hyphen.
Change-Id: I08d9b06e79683acd3994b84647bce401ed6741e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Get board id from AUXIN4 and RAM code from AUXIN3.
BUG=b:80501386
BRANCH=none
TEST=AUXIN4 is 0.074v and AUXIN3 is 0.212v on P0.
AUXIN4 is 0.212v and AUXIN3 is 0.212v on P1.
Change-Id: I50533e851d2fae66ae8c5e4e1aa36708d9058e94
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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We plan to get board id and RAM code from AUXADC on Kukui. Add AUXADC
driver to support it.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I121a6a0240f9c517c0cbc07e0c18b09167849ff1
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/29061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The Sarien mainboard uses the newly added Wilco EC.
- enable CONFIG_EC_GOOGLE_WILCO
- add the device and host command ranges to the devicetree
- have the mainboard SMI handlers call the EC handlers
- add EC and SuperIO devices to the ACPI DSDT
- call the early init hook for serial setup
Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a variant of the Sarien board called Arcada. This is currently
very similar to Sarien with differences in PCIe, USB, and GPIO usage.
Change-Id: I432d2ba99558e960d4e775c809cc8bf6aa1a56bf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29410
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sarien is a new board using Intel Whiskey Lake SOC. It also uses
the newly added Wilco EC, enabled in a separate commit.
Sarien is not a true reference board, it is just one variant of
a very similar design. For that reason it is not considered the
baseboard but rather a standalone variant.
Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Add a way for the mainboard to provide a wake pin that the EC
will use to wake the system. This defines a _PRW object.
Change-Id: I94954104bbb8226683c37abc8c0465fe3c62a693
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29408
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable GPIO functionality in verstage so platforms can read a
PCH GPIO in verstage to determine recovery mode.
Change-Id: Icd4344c4d66dbe21fda9dc27e61a836c1dd9be07
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29407
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the `PCI_DEVICE_ID_HSW_*` constants are no longer used, remove
them.
Change-Id: I84f1f069faa6a4165cf289f2e6c40889a49cad1d
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Enable the radium touchscreen support
BUG=b:117960394
BRANCH=master
TEST=
1. emerge-nami coreboot chromeos-bootimage
2. boot up on ekko DUT to check touchscreen device by evtest
/dev/input/event3: Raydium Touchscreen
Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5f2d9548b8e2c7b1d154b7bad126ec7b1052231a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Modify flash layout to match ICL-IFWI layout for early SoC PO support
Flash Reg 0: Descriptor [0x0 - 0xFFF]
Flash Reg 1: BIOS [0x400000 - 0xFFFFFF]
Flash Reg 2: IFWI (consist of ME primary & secondary partition and PMC FW)
[0x81000 - 0x3FFFFF]
Flash Reg 8: EC (applicable for Intel RVP with internal EC support)
[0x1000 - 0x80FFF]
Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29316
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The function `acpi_fill_madt()` is identical among all the Lynx Point
boards and sb/intel/bd82x6x, so share a common function between them.
Earlier Intel platforms have similar implementations of this function.
The common implementation might only need minor alterations to support
them.
Tested on an ASRock H81M-HDS and Google Peppy (variant of Slippy). No
issues arose from this patch.
Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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If the file `southbridge/intel/lynxpoint/nvs.h` is included in a file
that does not already include <stdint.h>, compilation errors result.
Adding the necessary <stdint.h> inclusions fixes compilation for an
ASRock H81M-HDS.
Change-Id: Id0d14705282cc959146e00dd47754ee8a2e8e825
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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The platform.asl file is copied from sb/intel/bd82x6x, and also matches
the contents deleted from each mainboard's platform.asl.
Tested on an ASRock H81M-HDS and a Google Peppy board (variant of
Slippy). No issues arose from this patch.
Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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On an ASRock H81M-HDS neither libgfxinit, nor Linux, is able to
initialise the display when lanes are not configured to be shared
between DDI A and DDI E.
Intel's reference manual [1] states that the decision to share lanes
between DDI A and DDI E is "based on board configuration". Hence, add a
new field to the devicetree that boards can set. All existing Haswell
boards have this unset, thus taking a value of 0, so there is no change
to existing behaviour.
[1]: Intel Open Source Graphics Programmer's Reference Manual (PRM)
Volume 2c: Command Reference: Registers (Haswell)
https://01.org/linuxgraphics/documentation/hardware-specification-prms/2013-intel-core-processor-family
Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29385
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On my system (Pentium G3258, ASRock H81M-HDS), changing the the slow
ramp rate during `initialize_vr_config()` results in the following
exception, causing the system to hang.
CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
Code: 0 eflags: 00010006 cr2: 00000000
eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90
So, only change this setting for Haswell ULT CPUs, as suggested by the
BIOS Writer's guide.
Change-Id: I79b10139295741d298ac6c77c4f7272ac151ad90
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When the Haswell-specific monotonic timer is used on an ASRock H81M-HDS
with a Pentium G3258, the following exception is generated, causing the
system to hang.
CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
Code: 0 eflags: 00010006 cr2: 00000000
eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90
The exception occurs when trying to read `MSR_COUNTER_24_MHz`, located
at 0x637. This MSR only exists on Haswell-ULT CPUs.
So, allow boards to use the TSC monotonic timer instead. They can do
this by placing `select TSC_MONOTONIC_TIMER` in the mainboard Kconfig.
Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
The super I/O setup needs to be done after the LPC is enabled. For
Lynx Point, configuring the super I/O in `mainboard_romstage_entry()`
is too early to get a serial console output. To remedy this, add a
function `mainboard_config_superio()` that will be called at the
appropriate time, and can be overridden by mainboard code.
Change-Id: Iaf4188a17533c636e7b0c7efa220bc6a25876dda
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch is based on a8a9f34e9b7b ("sb/intel/i82801{g,j}x:
Automatically generate ACPI PIRQ tables")
Tested on an ASRock H81M-HDS. The generated _PRT object looks correct,
and the system doesn't show any issue when running. The following
assignments occur:
ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1
ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=7
ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2
Also tested on a Google Peppy board. The following assignments occur:
ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=1
A diff of the _PRT object for the Google Peppy board is below. The code
used in the diff has been modified for clarity, but the semantics remain
the same. To summarise the diff:
* The disabled PCIe root ports are no longer included.
* The LPC controller is no longer included, as it has no interrupt pin.
The pins for the remaining LPC devices are each one less. Perhaps the
original _PRT object was incorrect?
* The SDIO device is no longer included, as it is disabled.
* The Serial IO devices are no longer included, but that is due to a
separate issue I am having with this system (the devices don't show up
under Linux regardless of this patch). In short: their omission is not
a fault of this patch.
--- pre/_PRT
+++ post/_PRT
@@ -1,301 +1,157 @@
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
- Return (Package (0x12)
+ Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x10
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x10
},
Package (0x04)
{
0x0014FFFF,
Zero,
Zero,
0x12
},
Package (0x04)
{
0x001BFFFF,
Zero,
Zero,
0x16
},
Package (0x04)
{
0x001CFFFF,
Zero,
Zero,
0x10
},
- Package (0x04)
- {
- 0x001CFFFF,
- One,
- Zero,
- 0x11
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x02,
- Zero,
- 0x12
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x03,
- Zero,
- 0x13
- },
-
Package (0x04)
{
0x001DFFFF,
Zero,
Zero,
0x13
},
Package (0x04)
{
0x001FFFFF,
Zero,
Zero,
0x16
},
Package (0x04)
{
0x001FFFFF,
One,
Zero,
0x12
},
Package (0x04)
{
0x001FFFFF,
0x02,
Zero,
0x11
- },
-
- Package (0x04)
- {
- 0x001FFFFF,
- 0x03,
- Zero,
- 0x10
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- Zero,
- Zero,
- 0x14
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- One,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x02,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x03,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0017FFFF,
- Zero,
- Zero,
- 0x17
}
})
}
Else
{
- Return (Package (0x12)
+ Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
Zero,
^LPCB.LNKA,
Zero
},
Package (0x04)
{
0x0003FFFF,
Zero,
^LPCB.LNKA,
Zero
},
Package (0x04)
{
0x0014FFFF,
Zero,
^LPCB.LNKC,
Zero
},
Package (0x04)
{
0x001BFFFF,
Zero,
^LPCB.LNKG,
Zero
},
Package (0x04)
{
0x001CFFFF,
Zero,
^LPCB.LNKA,
Zero
},
- Package (0x04)
- {
- 0x001CFFFF,
- One,
- ^LPCB.LNKB,
- Zero
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x02,
- ^LPCB.LNKC,
- Zero
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x03,
- ^LPCB.LNKD,
- Zero
- },
-
Package (0x04)
{
0x001DFFFF,
Zero,
^LPCB.LNKD,
Zero
},
Package (0x04)
{
0x001FFFFF,
Zero,
^LPCB.LNKG,
Zero
},
Package (0x04)
{
0x001FFFFF,
One,
^LPCB.LNKC,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x02,
^LPCB.LNKB,
Zero
- },
-
- Package (0x04)
- {
- 0x001FFFFF,
- 0x03,
- ^LPCB.LNKA,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- Zero,
- ^LPCB.LNKE,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- One,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x02,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x03,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0017FFFF,
- Zero,
- ^LPCB.LNKH,
- Zero
}
})
}
}
Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Tested on a Pentium G3258.
Change-Id: Ibf020c034c00b3bf3a7b0cda8bd3a7d40c4c13bd
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The PCI ID was taken from the output of `lspci` on an ASRock H81M-HDS.
Change-Id: I3679d1ab0ae08726bff04c5985d6d93437b2fb81
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The PCI ID was taken from the output of `lspci` on an ASRock H81M-HDS.
Change-Id: Ie162cb7a27e313ffe612659e8444657a3772d3c9
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Romstage is where DRAM comes online. Therefore, allow
raw CAR_GLOBAL object access in all cache-as-ram stages
that are not romstage. In practice, this should be a nop.
However, the explicit check for romstage is clearer.
Change-Id: I31454c05029140a946ef663b8fa1b2fa6a788154
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/29401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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For platforms utilizing CONFIG_NO_CAR_GLOBAL_MIGRATION there's
no need to automatically migrate globals. Because of this it's
possible to automatically allow for uninitialized global variables
which reside in the .bss section without needing to decorate those
objects with CAR_GLOBAL.
Change-Id: Icae806fecd936ed2ebf0c13d30ffa07c77a95150
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/29359
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PCI ID was taken from the output of `lspci` on an ASRock H81M-HDS.
Change-Id: Idc222392a0973f9ea62b943d18dd762b48c76d17
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The PCI IDs were taken from the Intel Lynx Point datasheet [1].
[1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub
(PCH) Datasheet, revision 003, document number 328904.
Change-Id: Ie4a264e9325d185334c3d7f7d2ed3c394ac33059
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change the variant name from kalista to karma.
According to the CL:1298319, the baseboard name is kalista
and the board name is karma.
BUG=none
BRANCH=master
TEST=emerge-kalista coreboot chromeos-bootimage
Change-Id: Idea295cc14249721a6dc0fc4e2ef6470d43e16eb
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29314
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia669b25683c138d96be00db90d01cf406db4c2eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29404
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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In commit 41baf0c3ff (soc/amd/stoneyridge: Remove dev_find_slot where
possible), the register being read was changed accidentally from
HT_DEV (Device 18h, Func 0) to NB_DEV (Device 18h, Func 5)
This doesn't return the correct value, and causes Grunt to reboot.
BUG=b:118721473
TEST=Boot grunt
Change-Id: I7b73358a074dd27639aafead7c8b39f0fad5685f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The function domain_read_resources() didn't have any code to actually
reserve any resources - it was just creating an empty resource entry.
I looked at fixing it to actually reserve the space, but the values in
the registers at the point when this runs aren't the final values that
we want to reserve anyway, they're temp values with a range much larger
than we want to reserve.
I next looked at moving the amd_initcpuio() function earlier so that we
could get the correct values for the registers, but even that doesn't
give us what we really want.
Ultimately removing this whole function seems to be the right thing.
BUG=None
TEST=Verify that the only resource that changes is the empty resource:
PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 1080
Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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The speakers start up muted, and the EC must be told by the BIOS
to unmute it. This helps prevent popping noises on boot/resume.
Change-Id: I693f1d01e46e19362ef8fd0d5b3f4930967b5a12
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI devices for the basic SuperIO functionality provided by the EC
for PS/2 keyboard, PS/2 mouse (trackpad emulation), and legacy UART.
The specific defines to enable these devices should be declared by the
mainboard before including this ASL, the same as the Chrome EC behavior.
Change-Id: I910940ebf26b8758ab12d695e1eba9c668c640c6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add methods to handle ACPI EC events at runtime. Currently only
some common events are handled like lid switch and battery info,
and the event status is printed for debug on other events.
Change-Id: Ic0bd070940c8a2dfa6a251f3464301418bdb69c1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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