diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-10-25 09:29:10 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-05 09:06:49 +0000 |
| commit | fe701ee3982f8c921390aacc45d50871dc86d119 (patch) | |
| tree | 228bd8598a5b34c064bf5420551232e941882606 /src | |
| parent | f41cb17fe29923fca898b39d343ccc71c193bea7 (diff) | |
soc/intel/cannonlake: Enable ISH from device
PCH ISH enabled/disabled in FSP memory init UPD, it will be match the
setting in ISH device on/off in devicetree.cb.
BUG=N/A
TEST=Build and pass on whiskey lake rvp platform.
Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 3cfa2819c2..8506214425 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -25,6 +25,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) { unsigned int i; uint32_t mask = 0; + const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH); /* Set IGD stolen size to 64MB. */ m_cfg->IgdDvmt50PreAlloc = 2; @@ -55,6 +56,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif + /* If ISH is enabled, enable ISH elements */ + if (!dev) + m_cfg->PchIshEnable = 0; + else + m_cfg->PchIshEnable = dev->enabled; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |