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2021-12-13mb/google/guybrush/var/dewatt: Add Synaptics touchpadKenneth Chan
Add Synaptics S9831 touchpad for dewatt. BUG=b:208182457 TEST=emerge-guybrush coreboot chromeos-bootimage. Tested with Synaptics S9831 touchpad. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Id3e0636dd0ce5b80c2044c1dfca20ca7eac87fc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-13mb/google/octopus: add ALC5682I-VS to be supported in the SSFCPaul Huang
Add ALC5682I-VS codec support. ALC5682I-VD/ALC5682I-VS load different hid name depending on SSFC. BUG=b:198722640 BRANCH=octopus TEST=Set CBI SSFC BIT9-11 to select codec, and test audio works Change-Id: I80be12d88e100ce8586371fc49b36447859e24f8 Signed-off-by: Paul Huang <paul2_huang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-12-13mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VSKane Chen
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:198689479 BRANCH=zork TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59558 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-13soc/amd/cezanne: Don't select CPU_INFO_V2 explicitlyNico Huber
It's already implied by PARALLEL_MP now. Change-Id: Ia76f1a925b2c0ebbba0bf20b094e716708d540c2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-13soc/intel/alderlake: Implement function to map physical port to EC portMAULIK V VAGHELA
Currently coreboot and EC had different logic to interpret TCSS port number which would break retimer update functionality since coreboot would pass wrong port information to EC. To correct this, coreboot has implemented function which converts coreboot physical port mapping to EC's abstract port mapping. Each SoC needs to implement this weak function since only SoC will have correct physical port mapping data. This function should resolve issue of port mismatch since coreboot will count only enabled ports and provide correct EC port number in return. BUG=b:207057940 BRANCH=None TEST=Check if retimer update works on Redrix and correct port information is passed to EC. Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13drivers/intel/usb4/retimer: Add function to correct EC port mappingMAULIK V VAGHELA
Currently coreboot interprets TCSS port number as per physical port number while EC abstracts port number and provides indices as port number. For example, if TCSS port 1 and 3 are enabled on the board, coreboot will interpret port numbers as 0 and 2, but since only 2 ports are enabled in the system EC will assign port numbers as 0 and 1. This creates a port number mismatch while communicating between EC and coreboot. This patch addresses issue where SoC can implement function to map correct EC port as per port enabled in mainboard. BUG=b:207057940 BRANCH=None TEST=Check if code compiles successfully. Functionality will work once function is implemented in SoC code. Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3Tim Wawrzynczak
For additional power savings during RTD3, the PMC can power-gate the ModPHY lanes that are used by the PCH PCIe root ports. Therefore, using the previous PCIe RP-type detection functions, implement ModPHY PG support for the PCH PCIe RPs. This involves: 1) Adding a mutex so only one power resource accesses the PMC registers at a time 2) OperationRegions to access the PMC's PG registers 3) Adding ModPHY PG enable sequence to _OFF 4) Adding ModPHY PG disable sequence to _ON BUG=b:197983574 TEST=50 S0ix suspend/resume cycles on brya0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59855 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-13soc/intel/alderlake: Define soc_get_pcie_rp_typeTim Wawrzynczak
In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Alder Lake. While we're here, add PCIe RP group definitions for PCH-M chipsets. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-13soc/intel/tigerlake: Define soc_get_pcie_rp_typeTim Wawrzynczak
In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Tiger Lake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-13drivers/intel/mipi_camera: Add ACPI entry to provide silicon type infoSugnan Prabhu S
Add entry in ACPI table under IPU device to provide silicon type information to IPU driver. IPU kernel driver can decide the type of firmware to load based on this information. BUG=b:207721978 BRANCH=none TEST=Check for the ACPI entry in the SSDT after booting to kernel Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f Cq-Depend: chromium:3319905 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13src/arch/x86/exit_car: Fix regression on x86_64Patrick Rudolph
The commit d023909b "treewide: Disable R_AMD64_32S relocation support" clflush the address stored in _cbmem_top_ptr, which is the same address cbmem_top() returns, instead of clflush _cbmem_top_ptr itself. Fix that by providing the correct address to clflush. Change-Id: If74591e7753cd9c3c097516430a212d416f53e4d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-13soc/intel/cannonlake: Configure common FSP memory settings only onceFelix Singer
`meminit_memcfg()` does common memory configuration, which is not specific to each DIMM. Thus, move it out of the for-loop and call it once. Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-13vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02Ronak Kanabar
The headers added are generated as per FSP v2471_02. Previous FSP version was v2422_01. Changes Include: - UPDs description update in FspsUpd.h - Adjust UPD Offset in FspmUpd.h and FspsUpd.h BUG=b:208336249 BRANCH=None TEST=Build and boot brya Change-Id: I4d04652c06a1c1823d3859be209710c273a2ae8c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-12-13lib: Add __fls() (Find Last Set)Jianjun Wang
Implement __fls() as an alias for log2(), and remove the duplicate definitions in commonlib/storage/sdhci.c. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-12mainboard: Drop `SataMode` setting from Tiger Lake devicetreesFelix Singer
All Tiger Lake mainboards use the default value for the setting `SataMode`. Thus, drop it from their devicetree. Change-Id: I291048250bc82552fde7c71a1dcda4894a61d465 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59890 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-12mainboard: Drop `SataMode` setting from Cannon Lake devicetreesFelix Singer
All Coffee Lake mainboards use the default value for the setting `SataMode`. Thus, drop it from their devicetree. Change-Id: Ibb329eb8b752c2220bb25f14fb6ae92dd8a308d6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59889 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-12mainboard: Drop `SataMode` setting from Skylake devicetreesFelix Singer
All Skylake mainboards use the default value for the setting `SataMode`. Thus, drop it from their devicetree. Change-Id: I9be5eca93cac65afc4cc30ceb64d9a5b7e5cd514 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59888 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-12soc/intel/elkhartlake: Hook up public microcodeArthur Heymans
Change-Id: I1d975713129d0a7bce823232d225ed17ee28a04d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-12soc/intel/jasperlake: Hook up public microcodeArthur Heymans
Change-Id: I9e511de5e5b79936ed09538b3877655f78de15a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-12soc/intel/cannonlake: Rename SA_DEV_SLOT_DSPFelix Singer
Device 4 was introduced with a wrong name, since it is the SA Thermal Subsystem and it does nothing have to do with DSP. Thus, rename it accordingly. Change-Id: I8edc764413df5f323098e60d0a3f0f87a7e656cb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60049 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-11vendorcode/intel: Add edk2-stable202111 supportSubrata Banik
This patch includes (edk2/edk2-stable202111) all required headers for edk2-stable202111 EDK2 tag from EDK2 github project using below command: >> git clone -b edk2-stable202111 https://github.com/tianocore/edk2.git commit hash: bb1bba3d776733c41dbfa2d1dc0fe234819a79f2 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Note: edk2-stable202111 tag is required to adopt FSP 2.3 specification. - Need to add ExtendedImageRevision in FSP_INFO_HEADER structure. - Need to add FSP_NON_VOLATILE_STORAGE_HOB2 header. Change-Id: I786cc05f9a638ac6226ebc8c0eaf1dc8189a4ca4 Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-12-10cpu/x86/mp_init.c: Make it work for !CONFIG_SMPArthur Heymans
With very little changes this code can be used to initialize systems without SMP. The linker will remove most of the code. Change-Id: Ia0e8fdf8ed7bc2e0e4ff01be8d3e3c3cb837e6c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-10mb/google/brya/var/taeko: Fix PLD group order (W/A)Kevin Chang
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI table), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table") BUG=b:209723556 BRANCH=none TEST=build coreboot and boot into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ia4cf2d735de524ae721800600536923d1d47f04b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-10soc/intel/{skylake/cannonlake}: Fix bug in vr_configAngel Pons
The `cpu_get_power_max()` function returns the TDP in milliwatts, but the vr_config code interprets the value in watts. Divide the value by 1000 to fix this. This also fixes an integer overflow when `cpu_get_power_max()` returns a value greater than 65535 (UINT16_MAX). Change-Id: Ibe9e0db6762eee5cc363f8b371c8538eb92f6308 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-10mb/siemens/mc_ehl: Enable TPM in bootblockWerner Zeh
Enable TPM init in bootblock so that all further stages and other CBFS files are directly measured into PCRs immediately instead of being logged into a buffer and replayed to the TPM in ramstage. Change-Id: Ib3ac29aa72abe8e967660ae7e8416aeb8812de26 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-12-10vendorcode/intel: Rework UDK binding KconfigSubrata Banik
coreboot code currently supports different UDK binding as per underlying FSP requirement, example: ICL and TGL uses UDK_2017_BINDING while ADL uses UDK_202005_BINDING Kconfig. These UDK binding Kconfigs are being used to choose the correct UDK_VERSION. This patch introduces `UDK_BASE` Kconfig option so UDK_VERSION if clause don't need to add specific UDK binding Kconfig everytime with introduction of newer UDK bindings in future. Tested with BUILD_TIMELESS=1, Hatch remains identical. Change-Id: I64c51aa06a14f0ce541537363870ac3925b79a68 Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-10mb/intel/adlrvp: Add support for external clock bufferSubrata Banik
ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are connected on the platform, an external differential buffer chip needs to be placed at the platform level. A mainboard designer can choose to add an external clock chip, and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER. CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete buffer for further distribution to platform. TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot. localhost ~ # dmesg | grep mmc [ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA [ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa [ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB [ 5.494268] mmcblk0: p1 Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-10mb/var/gimble4es: Set PsysPmax to 143 WMark Hsieh
This patch adds the setting of PsysPmax to 143 W according to gimble board design. BUG=b:206990759 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I851e0871461a9a9769c6b84f7d8287d989c23f06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-10soc/intel/cse: config to enable oem key manifestRavindra N
CB change will enable the CSE region sub-partition OEMP, where the OEMP binary will be stitched. OEM KM has Audio FW's key hash. So, CSE uses this information to authenticate Audio FW. BUG=b:207820413 TEST: Boot to kernel and check for the audio authentication is successful localhost ~ # aplay -l **** List of PLAYBACK Hardware Devices **** card 0: sofrt5682 [sof-rt5682], device 0: max357a-spk (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 1: Headset (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 2: HDMI1 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 3: HDMI2 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 4: HDMI3 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 5: HDMI4 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 Cq-Depend: chrome-internal:4286038 Signed-off-by: Ravindra N <ravindra@intel.corp-partner.google.com> Change-Id: I3620adb2898efc002104e0ba8b2afd219c31f230 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2021-12-09mb/google/guybrush/var/nipperkin: Configure Smart Card in normal modeKarthikeyan Ramasubramanian
As per the schematics, smart card is expected to operate in normal mode by default. So configure the SOC_SC_PWRSV gpio accordingly. BUG=b:202992077 TEST=Build and boot to OS in Nipperkin board version 2. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8e12600ad45734b144a30c868f0e4f323aa056f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-09mb/google/guybrush/var/nipperkin: Override SPI fast speedKarthikeyan Ramasubramanian
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=None TEST=Build and boot to OS in Nipperkin board version 2. Perform 250 iterations of warm and cold reset each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id973acb939b69e0beda26252e57a278892f2f57d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-09mb/google/brya4es: sync change from brya0 (CB:58374)YH Lin
CB:58374 (for mb/google/brya0) was merged before brya4es is available (CB:59728). And since brya4es is forked from brya0, brya0's change need to be brought into brya4es as well. BUG=b:203014972 TEST=build Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I97489343b8f7a5b9457cd6f4a61cc37cd10ab450 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Drop unused SataEnable settingFelix Singer
`SataEnable` is set by some boards, but it doesn't have any effect since its related FSP option is hooked up to the devicetree state. Thus, drop it. Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-09mb/starlabs/labtop: Enable SMBus in Device TreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8bc3025331bb25b02712b5d2b654f7997f0aba4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/brya/var/brask: Configure the ISOLATE pin of LANAlan Huang
1. Copy the default configuration from Puff. 2. Update the 'stop_gpio' to GPP_H22. BUG=b:193750191 BRANCH=None TEST=Update kernel for 8125 outbox driver and test with command suspend_stress_test. Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/brya/var/redrix4es: sync change from redrixYH Lin
The original change was for mb/google/redrix (commit 0167f5adbb), "The ChromeOS kernel platform driver is adding support for a ChromeOS privacy screen device, and in order to locate that device, the driver uses the GOOG0010 reserved HID for this" But it was merged before redrix4es is available. As redrix4es is forked from redrix, relevant change in redrix need to be brought into redrix4es as well. BUG=b:206850071 TEST=build Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I5ac90c249273bf4e75cccb5889844a7f196f56fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEMFrans Hendriks
CONFIG_ONBOARD_SAMSUMG_MEM was used to force Samsung memory. CPLD returns different values for every board revision. Use this value to determine the memory type. BUG = N/A TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4 Change-Id: I21b5ddc430410a1e8b3e9012d0c07d278880ff47 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-09soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0Tim Wawrzynczak
The macro was defined using PCH_DEV_SLOT_CPU_1, which doesn't exist, so replace it with the correct value of SA_DEV_SLOT_CPU_1. Change-Id: If6d294d681907c51ac5678c9251364d4d6df4329 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-09mb/google/brya: keep the same TPM I2C for 4ES variantsYH Lin
Since 4ES variants were forked from their own original variants, use the same TPM I2C as well. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09cpu/amd/agesa/Kconfig: select NO_SMM for Family 14hMichał Kopeć
Move the SMM Kconfig options to the specific agesa cpu families. Select NO_SMM for family14 since since no Fam14h platform uses SMM. Leave SMM_ASEG enabled for family15tn and family16kb for now. TEST=Boot Debian 11 on PC Engines apu1 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I09bbe036a88dada847219606ec79c68e7ca8e5cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-12-09soc/amd/stoneyridge: use common fch_spi_early_initFelix Held
All SPI interface setup related functionality that Stoneyridge implemented in its southbridge code is already present in the common AMD SoC code, so use that code instead. The common fch_spi_early_init function requires the SPI controller's base address to be set, so call lpc_set_spibase(SPI_BASE_ADDRESS) right before it. fch_spi_early_init then calls lpc_enable_spi_rom and lpc_enable_spi_prefetch which can be removed from the board code now. Next it calls fch_spi_configure_4dw_burst which does the same as the now removed sb_disable_4dw_burst function when SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST is set to n which is the default. This option can also only be set to y for SoCs that aren't Stoneyridge. Finally fch_spi_early_init calls fch_spi_config_modes which configures the SPI mode and speed settings according to the Kconfig settings and the settings in the amdfw part. On Kahlee this was done by calls to sb_read_mode and sb_set_spi100 before. The previous patch added the remaining Kconfig settings, so the resulting register values don't change in the non-EM100 case. In the EM100 case the TPM speed is changed from 64 to 16 MHz. TEST=Both the non-EM100 mode with a real SPI flash and the EM100 mode with a first-generation EM100 results in Google/Barla reaching the payload and the show_spi_speeds_and_modes call in bootblock prints the expected settings: relevant bootblock console output in non-EM100 case: SPI normal read speed: 33.33 MHz SPI fast read speed: 66.66 Mhz SPI alt read speed: 66.66 Mhz SPI TPM read speed: 66.66 Mhz SPI100: Enabled SPI Read Mode: Dual IO (1-2-2) relevant bootblock console output in EM100 case: SPI normal read speed: 16.66 MHz SPI fast read speed: 16.66 MHz SPI alt read speed: 16.66 MHz SPI TPM read speed: 16.66 MHz SPI100: Enabled SPI Read Mode: Normal Read (up to 33M) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-09mb/google/kahlee/Kconfig: add remaining SPI speed settingsFelix Held
Before this patch only the SPI settings that will also end up in the amdfw part of the firmware were specified in the board's Kconfig. This patch adds the settings from Kahlee's bootblock.c to the Kconfig file which will be needed in subsequent patches. Also add a comment about the EM100 case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie42feb9b41f435c329bf1c78471e65ef5a3fb783 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-09soc/amd/common/block/psp: add psp_efs.c to build for both PSP GEN1&2Felix Held
The PSP EFS code to get the SPI mode and speed from the amdfw part of the firmware image also works for Stoneyridge which is the one SoC that selects SOC_AMD_COMMON_BLOCK_PSP_GEN1. Also amdblocks/psp_efs.h already handles the SOC_AMD_STONEYRIDGE case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibddd3f9237e561d9f0f6b4ad70f59cce1f956986 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-09mb/google/corsola: Pass reset gpio parameter to BL31Rex-BC Chen
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=build pass BUG=b:202871018 Cq-Depend: chromium:3188686 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I48d8d004ea92e950d0040a11133c57c121b86af3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-09soc/mediatek/mt8186: Enable ARM Trusted Firmware integrationRex-BC Chen
Enable configuration to build with MT8186 arm-trusted-firmware drivers. TEST=build pass BUG=b:202871018 Cq-Depend: chromium:3189573 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib23b112a0bf3d056b932a87b86aaff79508ef50c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-09mb/google/corsola: correct NOR flash configuration in GPIO setRex-BC Chen
The reference design has changed to use GPIO SET1 for NOR flash. There are no devices already built using SET0 so we can safely change the implementation without conditional configs. Reference document: kingler_mt8186_mt6366_lpddr4x_e.pdf, page 11. crab_proto 0_2021112.pdf, page 11. BUG=b:202871018 TEST=flash verify pass on kingler on bootblock stage Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-09mb/google/corsola: get SKU IDRex-BC Chen
Retrieve the SKU ID for Corsola via CBI interface. If that failed (or no data found), fallback to ADC channels for SKU ID. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08soc/intel/common/pch: Fix return value documentation for CHIPSET_LOCKDOWNJingle Hsu
Fixed according to the declaration in soc/intel/common/block/include/intelblocks/cfg.h. Change-Id: I50dbc00806fefda8f4dac8bfa21dc714a9504566 Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-08mb/google/dedede/var/magolor: Add fw_config probe for multi codec andTyler Wang
amplifier Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB" BUG=b:208912135 TEST=ALC5682I-VD and ALC1015Q-VB can work normally Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Id661280061ede3fbb63c962dee8fb18a2053ad66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-08mb/google/guybrush: Combine mem_parts_used.txtRob Barnes
Combine guybrush mem_parts_used.txt across guybrush variants. Guybrush reference memory parts is used as the base, then Nipperkin memory parts were appended, followed by DeWatt memory parts. Duplicates were removed. The memory id mapping was not affected on guybrush reference and Nipperkin. DeWatt memory id mapping was affected, DeWatt boards will need to be adjusted. This works around a limitation in APCB, which currently only supports one set of memory SPDs. BUG=b:209486790, b:204151079 BRANCH=None TEST=Boot guybrush and nipperkin Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-08soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resumeRaul E Rangel
According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware_Specification.html#pm1-event-grouping > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI > only platforms (where SCI_EN is always set), when transitioning from > either the mechanical off (G3) or soft-off state to the G0 working > state this register is cleared prior to entering the G0 working state. This means we don't want to clear the PM1 register on resume. By clearing it the linux kernel can't correctly increment the wake count when the power button is pressed. The AMD platforms implement the _SWS ACPI methods, but the linux kernel doesn't actually use these methods. BUG=b:172021431 TEST=suspend zork and push power button and verify power button wake_count increments. Verified other wake sources still work. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-08soc/amd/stoneyridge/southbridge: drop ENV_X86 checkFelix Held
Stoneyridge selects ARCH_X86 unconditionally and all coreboot code will run on the x86 cores. On Picasso and later, the Chromebooks run verstage on the PSP which is an ARM V7 core which needs some special handling cases in the code, but this doesn't apply to Stoneyridge. TEST=Timeless build results in an identical image for Google/Careena. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I013efd13b56c0191af034a8c4b58e9b26a31c6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPIRaul E Rangel
According to https://uefi.org/specs/ACPI/6.4/16_Waking_and_Sleeping/sleeping-states.html?highlight=power%20states# > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit. This change makes sure we clear the PM/GPE blocks are cleared before enabling the SCI_EN bit. BUG=b:172021431 TEST=Boot guybrush and morphius to OS and verify suspend resume still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-08mb/google/brya/var/primus: Fix PLD group orderScott Chao
In ec/google/chromeec: Add PLD to EC conn in ACPI table(667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. BUG=b:209568644 BRANCH=none TEST=build coreboot and system boot into OS. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: If5ce6ca061d9d56ba0bbb1f157b2ba278d3fa9c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59953 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-08sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLEFelix Held
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities. Haven't checked the reference code, but the register descriptions suggested that the register in Mullins behaves similar to the one in Stoneyridge. Right now this code is unused, but it's probably still a good idea to fix it. TEST=Booting Debian 11 with kernel 5.10 on apu2 still works when adding a call to hudson_set_spi100 with this patch applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifbd960a9509542b28f03326a3066995540260bef Tested-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-12-08soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100Felix Held
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for Stoneyrige also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLEFelix Held
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for both Picasso and Cezanne also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=Verified that Mandolin still boots. It didn't show any signs of possibly related instabilities before though, so this test doesn't say much. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71c2ec1729d5cb4cdff6444b637af29caaa6f1c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/common/block/include/spi: update fch_spi_early_init descriptionFelix Held
commit 90ac882a32075b44435aa19ea664b89b79cac76e (soc/amd/common/block/ spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST) introduced a Kconfig option to enable/disable the 4DW burst support in the SPI flash data prefetcher, but missed to update the documentation above the fch_spi_early_init prototype, so update the outdated documentation now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I07c4b0b02251da63d34a172e2636894e99845d6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08mb/google/corsola: Configure TPMRex-BC Chen
Initialize SPI bus 2 for TPM control. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I8ede68d6eb594890195e8464151c1c0f88aeee43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08mb/google/corsola: implement get_ec_is_trustedRex-BC Chen
Set VB2_CONTEXT_EC_TRUSTED in verstage_main. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If2837f5db52f91f5418d222d4dcd1af2aebcc105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08mb/google/corsola: Enable Chrome ECRex-BC Chen
Initialize SPI bus 1 for Chrome EC control. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7d032d595f7ca1dbed3de4dfe308ff4be64333cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08soc/mediatek/mt8186: Correct SPI_HZ for PLLRex-BC Chen
The SPI speed is 218.4MHz, so correct the value of SPI_HZ. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I6e8ba10a851e1507405cdd41939a176462734487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08soc/mediatek/mt8186: revise SPI NOR GPIO selectionRex-BC Chen
The setting of SPI NOR GPIOs should be: CS: pull up. CLK/IO0/IO1: pull down. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ideacb797a1dc9999ab6ba00cf33adbbbc24213dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08cpu/amd/pi/Kconfig: select NO_SMMMichał Kopeć
Disable SMM_ASEG and select NO_SMM since the platforms do not use SMM. TEST=Boot Debian 11 on PC Engines apu3 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I47237421c3dd5bd043447831263d72c9956cdaf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-08lib: Fix log2_ceil() for 0xffffffffYu-Ping Wu
Current log2_ceil(x) is defined as log2(x * 2 - 1). When x is larger than (1 << 31), (x * 2 - 1) won't fit in u32, leading to incorrect result. Therefore, correct it as (log2(x - 1) + 1). Also add unit tests for inline functions in lib.h. BUG=none TEST=make tests/lib/lib-test BRANCH=none Change-Id: If868f793b909a6ad7fc48a7affac15e2c714fa2e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-08mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_initRaul E Rangel
These functions can't be weak, because they actually need to configure the GPIOs for eSPI and the TPM. With this change zork boots again. I also noticed that zork doesn't use the early table in bootblock. This means that zork will only boot if psp_verstage is enabled. BUG=b:209465425 TEST=boot zork to ramstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-08soc/amd: use KiB and MiB definitionsFelix Held
Use KiB and MiB instead of multiplying/dividing with/by the numeric value when doing region size calculations. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I56c380190b11aa3214cce31b82974327e3d15000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-07northbridge/amd/pi/00730F01/northbridge.c: remove unneeded global variablesMichał Kopeć
Remove global variables `sblink` and `node_nums` and add function `get_node_nums()` which reads from PCI config once and returns a static variable. TEST=Boot Debian 11 on PC Engines apu3 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I20a47f967093ef91355377c164656cabadc30fe6 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-12-07mb/google/brya: add list of gpios to lockNick Vaccaro
Add a list of gpios to lock for brya. This currently includes GPIOs connected to the FPMCU. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Change-Id: Idea42a58575c280be0770d38f934acdf5508c45d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-07soc/intel/alderlake: enable gpio lockingNick Vaccaro
This change supplies a list of ADL gpios that are connected to non-host (x86) controllers and should be locked after initial configuration. Set SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS to enable GPIO locking. BUG=b:210430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-07soc/intel/common: add generic gpio lock mechanismNick Vaccaro
For added security, there are some gpios that an SoC will want to lock once initially configured, such as gpios attached to non-host (x86) controllers, so that they can't be recofigured at a later point in time by rogue code. Likewise, a mainboard may have some gpios connected to secure busses and/or devices that they want to protect from being changed post initial configuration. This change adds a generic gpio locking mechanism that allows the SoC to export a list of GPIOs to be locked down and allows the mainboard to export a list of GPIOs that it wants locked down once initialization is complete. Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to enable this feature. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify brya0 boots successfully to kernel. Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06mb/google/brya/var/gimble: Configure Acoustic noise mitigationMark Hsieh
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 16 BUG=b:206704930 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59535 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-06soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR configCurtis Chen
We only have ADL-P 6+8+2 (45W) VR configuration now. Based on the power map, fill in correct ADL-P 6+8+2 (28W) VR configuration. BUG=b:202486131 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/mediatek/mt8195: complete devapc settingsNina Wu
In previous patch (CB:56764), only basic settings were added. Now complete devapc settings on MT8195. 1. Update permission setting 2. Updtate master domain setting: - domain 1: PCIE0, PCIE1 - domain 2: SPM, SSPM, CPU_EB 3. Set domain remap - MMSYS (4-bit to 2-bit) - TINYSYS (4-bit to 3-bit) - TINYSYS (3-bit to 4-bit) - TINYSYS to EMI (3-bit to 4-bit) - INFRA2 (3-bit to 4-bit) 4. Set SCP domain and ADSP domain - domain 3: SCP - domain 4: ADSP BUG=b:204347737 TEST=sanity test pass Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59746 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-06soc/intel/alderlake: Add support for ADL-N CPU TypeUsha P
Add Alder Lake-N case for adl_cpu_type and get_supported_lpm_mask. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-12-06northbridge/amd/pi/00730F01: enable PARALLEL_MPMichał Kopeć
Disable LEGACY_SMP_INIT to enable PARALLEL_MP. Also remove a large amount of APIC code that is now unnecessary. TEST=Boot on PC Engines apu3 Boot time reduced from 1.707 seconds to 1.620 seconds average across 5 coldboots. Inspired by CB:59693 Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-12-06x86_64 assembly: Don't touch %gsPatrick Rudolph
With CPU_INFO_V2 enabled %gs holds the pointer to the cpu_info struct, so don't clobber it. Backup and restore %gs where possible. Fixes a crash in MPinit seen after calling FSP-S. Change-Id: If9fc999b34530de5d8b6ad27b9af25fc552e9420 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-12-06security/intel: Use defines for segment registersPatrick Rudolph
Change-Id: I6f11039bafa3800d59d61defa8824ae962224c9b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59763 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-06cbfs: Remove deprecated APIsJulius Werner
This patch removes all remaining pieces of the old CBFS API, now that the last straggling use cases of it have been ported to the new one (meaning cbfs_map()/cbfs_load()/etc... see CB:39304 and CB:38421). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-12-06mb/google/brya/var/redrix: Swap TPM I2C with touchscreen I2CWisley Chen
According to the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:205648040 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I3a8339c23522019da884944246427512170510b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratioSridhar Siricilla
The patch refectors cpu_set_p_state_to_max_non_turbo_ratio(). The function is updated to use cpu_get_max_non_turbo_ratio(). TEST=Build the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If73df17faaf7b870ae311460a868d52352683c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/intel/common: Add CPU related APIsSridahr Siricilla
The patch defines below APIs : cpu_is_hybrid_supported() : Check whether CPU is hybrid CPU or not. cpu_get_bus_frequency() : Get CPU's bus frequency in MHz cpu_get_max_non_turbo_ratio() : Get CPU's max non-turbo ratio cpu_get_cpu_type() : Get CPU type. The function must be called if executing CPU is hybrid. TEST=Verified the APIs on the Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06mb/var/gimble: Set PsysPmax to 143 WChia-Ling Hou
This patch adds the setting of PsysPmax to 143 W according to gimble board design. BUG=b:206990759 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: Id6a203f05ecfcc1020a422850d35fa3fa64e01d0 Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ryan Lin <ryan.lin@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.hTim Wawrzynczak
This enum is useful to have around for more than just the one file, so move it to a common header file, and while we're there, also add an option for UNKNOWN. TEST=boot test on brya0 Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-06acpi: Add #define for Mutex "no timeout" valueTim Wawrzynczak
Some acpigen code may use mutexes, and it is a common idiom to pass a value for the Timeout field of 0xffff, which is interpreted by OSPM to mean "no timeout". Therefore add a macro for this value. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I16bc9f3f04dd1e3dc0f3eca3e56377e6f48132b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-06mb/google/brya/var/felwinter: Correct garage wake eventEric Lai
Eject event is high. Set wake event to active high. The polarity of the SCI and the wakeup_event_action for the pen ejection feature were both backwards, and was causing the system to fail to enter sleep states because the event was always asserted. BUG=b:208937710 TEST=only release switch can wake system. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I568e9175c7a66599f7a525c32e4def7a79b55a0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLERArthur Heymans
Fixes commit 29c7622 ("cpu/x86/mp_init.c: Fix building with no smihandler") broke SMM init because is_smm_enable() was called before smm_enable. Rework the code a little to make it clear what codepaths are used with CONFIG_HAVE_SMI_HANDLER. TESTED: now prodrive/hermes boots again. Change-Id: If4ce0dca2f29754d131dacf2da63e946be9a7b6d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59912 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-05mb/google/hatch: Remove stryke mainboardTim Wawrzynczak
The stryke project/mainboard never ended up being built and was cancelled early on, therefore remove it from the tree. Change-Id: I4d91fbd4ba0abe0cf599e8e75f04398ef9ff5222 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-03soc/intel/adl: Add override skip_cse_sub_part_update() for alderlakeKrishna Prasad Bhat
Check the Alderlake CPU ID to determine if cse sub-paritition update is required or not. BUG=b:202143532 Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/common: Add support for CSE IOM/NPHY sub-parition updateKrishna Prasad Bhat
This patch adds the following support to coreboot 1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B partition of BIOS 2. Helper functions to support update. Pre-requisites to enable IOM/NPHY FW Update: 1. NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and FW_MAIN_B through board configuration files. CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path 2. Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition NPHY/IOM update. coreboot follows below procedure to update NPHY and IOM: NPHY Update: 1. coreboot will navigate through the CSE region, identify the CSE’s NPHY FW version and BIOS NPHY version. 2. Compare both versions, if there is a difference, CSE will trigger an NPHY FW update. Otherwise, skips the NPHY FW update. IOM Update: 1. coreboot will navigate through the CSE region, identify CSE's IOM FW version and BIOS IOM version. 2. Compares both versions, if there is a difference, coreboot will trigger an IOM FW update.Otherwise, skip IOM FW update. Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only if CSE boots from CSE RO Boot partition. Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then triggers update of NPHY and IOM FW in the CSE Region(RO and RW). coreboot triggers NPHY/IOM update procedure in all ChromeOS boot modes(Normal and Recovery). BUG=b:202143532 BRANCH=None TEST=Build and verify CSE sub-partitions IOM and NPHY are getting updated with CBFS IOM and NPHY blobs. Verified TBT, type-C display, NVMe, SD card, WWAN, Wifi working after the update. Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/common: Add check before sending HMRFPO_ENABLE commandSridhar Siricilla
This patch adds a check to determine if the CSE's current operation mode is ME_HFS1_COM_SECOVER_MEI_MSG or not before sending HMRFPO_ENABLE command to CSE. If CSE is already in the ME_HFS1_COM_SECOVER_MEI_MSG, coreboot skips sending HMRFPO_ENABLE command to CSE to unlock the CSE RW partition. TEST=Verify sending HMRFPO_ENABLE command on Brya system. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/common: Rename compare_cse_version() function nameSridhar Siricilla
The patch renames the compare_cse_version() function to the cse_compare_sub_part_version(). It makes the function generic so that it can be used to compare version of any CSE sub-partition like IOM, NPHY etc. TEST=Verified build for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I88a44a3c0ba2ad8a589602a35ea644dab535b287 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59689 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03soc/intel/alderlake: Add support for ADL-N PCHUsha P
Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to specify the correct amount of PCIe I/O. Document number 645550 indicates that Alder Lake-N has 12 PCH root ports and no CPU root ports. Document number 645548 indicates ADL-N has 5 clock sources and 5 clock request signals. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03cbfs | tspi: Join hash calculation for verification and measurementJulius Werner
This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT is enabled from the lookup step into the code where a file is actually loaded or mapped from flash. This has the advantage that CBFS routines which just look up a file to inspect its metadata (e.g. cbfs_get_size()) do not cause the file to be measured twice. It also removes the existing inefficiency that files are loaded twice when measurement is enabled (once to measure and then again when they are used). When CBFS verification is enabled and uses the same hash algorithm as the TPM, we are even able to only hash the file a single time and use the result for both purposes. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I70d7066c6768195077f083c7ffdfa30d9182b2b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-03mb/google/brya/var/felwinter: Add WiFi SAR table for felwinterIan Feng
Add WiFi SAR table for felwinter. BUG=b:206901900 TEST=emerge-brya chromeos-config chromeos-config-bsp-private coreboot-private-files-baseboard-brya coreboot chromeos-bootimage and checked SAR table can load by WiFi driver. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0de710f4447302ee545a67cbd79373bdd2077637 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-12-03mb/google/brya: Update camera NVM parametersBernardo Perez Priego
Change HID name from INT3499 to PRP0001 along with size and address width. Size decreased from 10K to 2K, address width decreased from 14 to 8. BUG=b:203014972 Test= Boot board and issue commands: `cat /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom > ./brya_imx208_eeprom.bin` `hexdump -C brya_imx208_eeprom.bin > brya_imx208_eeprom_dump.log` You should see the result in brya_imx208_eeprom_dump.log to be same as module nvm file by vendor provided or meet the Intel nvm calibration format. (e.g. first 4 bytes be 0x01, 0x03, 0x01, 0x00) Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/dedede/var/drawcia: Generate new SPD ID for new memory partsRobert Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Samsung K4U6E3S4AA-MGCL BUG=b:204014463 TEST=run part_id_gen to generate SPD id Change-Id: Icb0f211508450b16b2e5d214ae6adc9852718a59 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-03region: Rename rdev_readat_full to rdev_read_fullJulius Werner
The 'at' part of the name refers to starting to read from a specific offset, so it doesn't make sense for the 'full' version of the function. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I60d595f0cbd161df171eaa4a76c7a00b6377e2b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59820 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 05:56:17 +0000