diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-12-05 07:29:17 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2021-12-12 16:06:10 +0000 |
| commit | 178153dc45896c9c82a3f1b5b10a0c1bad768fe8 (patch) | |
| tree | 50301d5c9f585fe0d1fa3d16a4efd0f165fa920a /src | |
| parent | ed8081cdddfee888b84a94a4efa8eaf9f4fa7983 (diff) | |
mainboard: Drop `SataMode` setting from Skylake devicetrees
All Skylake mainboards use the default value for the setting `SataMode`.
Thus, drop it from their devicetree.
Change-Id: I9be5eca93cac65afc4cc30ceb64d9a5b7e5cd514
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59888
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
16 files changed, 0 insertions, 16 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 5950dec685..ac1b45d4eb 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "1" - register "SataMode" = "0" # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 8ea6539bec..c7310052db 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -37,7 +37,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index e79f7044fa..ceca5f14ce 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -66,7 +66,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 65e1014992..a200cfb8bd 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 62dd1f5099..39b7d9f9e0 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -44,7 +44,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index ebbb12f973..4d145e18e7 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 34163efc51..6d7541e4d7 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 098216d3c5..068a031f1d 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 0d9c5bd033..e4e01585bd 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -37,7 +37,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index f2dc5b6b3b..ff06d6acfe 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -44,7 +44,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 745d72ce32..9be000f0d3 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 47df4e1026..5dc62aafc8 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -56,7 +56,6 @@ chip soc/intel/skylake device pci 16.3 off end # ME KT device pci 16.4 off end # MEI #3 device pci 17.0 on # SATA - register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ [0] = 1, diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 0cf8abef65..d047f76349 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 3ef4250353..a264c6b276 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -29,7 +29,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 5efb1e2aed..dfa894b3d4 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -42,7 +42,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 42ee0c7971..3d311a3dd4 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -23,7 +23,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "0" |