| Age | Commit message (Collapse) | Author |
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Clean up redundant `struct pad_func` and `PAD_*` definitions. This patch
also refactors the PAD_* macros by,
- Repurposing PAD_FUNC and dropping PAD_FUNC_SEL.
- Adding PAD_FUNC_DOWN and PAD_FUNC_UP to avoid the implicit
initialization.
BUG=none
TEST=emerge-{elm, kukui, asurada, cherry, corsola, geralt, rauru} coreboot
Change-Id: I12b8f6749015bff52988208a7c3aa01e952612c6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84222
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove PL4 value modification based on PsysPL3 value.
BUG=None
BRANCH=None
TEST=Built and boot on brox system
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: Ic7fbc6386769aa9f76a8665a742c97dfd790fd1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83662
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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With the release 20240910 of the Intel microcode repository, it also
includes the updated microcode file with version 0x129, which makes the
one from the coreboot blobs repo superfluous. Thus, use the one from the
Intel repository again.
Change-Id: I7fb58874719a8373072419e34b3f8923f7db927d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84295
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct the number of NID entries.
BUG=b:349996984
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: I5f5553a5d8014f957d6b89ac4c1039594817bf32
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84184
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable ASPM of CPU PCIe4 for SSD to improve power consumption.
BUG=b:364441213
BRANCH=None
TEST="sh -c 'lspci -vvnn || lspci -nn'"
01:00.0 Non-Volatile memory controller
LnkCtl: ASPM L1 Enabled
Change-Id: I4380bb8748f2847b1824e20edb19578c7aedfe4f
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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These identifiers are not included in the GPU list from Intel [1].
At the same time, 0x9B44 is not PCI DID of graphics device at all:
8086:9B44 - 10th Gen Core Processor Host Bridge/DRAM Registers [2].
[1] https://web.archive.org/web/20240731152818/https://
dgpu-docs.intel.com/devices/hardware-table.html
[2] https://web.archive.org/web/20231004011832/https://devicehunt.com/
view/type/pci/vendor/8086/device/9B44
Change-Id: I8ff7b062f930cb63ffd9caf240874742bd53fc23
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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According to the Intel GPU list [1], these devices have the following
IDs:
8086:9BA8 - Comet Lake-S GT1 [UHD Graphics 610] [2]
8086:9BA5 - Comet Lake-S GT1 [UHD Graphics 610]
8086:9BA4 - Comet Lake-H GT1 [UHD Graphics 610] [3]
8086:9BA2 - Comet Lake-H GT1 [UHD Graphics 610]
Allows coreboot to correctly initialize IGD (8086:9ba8) in Intel Celeron
G5905 CPU (ID a0653, Cometlake-H/S G1 (6+2), ucode: 000000f9).
This can also be verified using devicehunt.com [2,3].
[1] https://web.archive.org/web/20240731152818/https://
dgpu-docs.intel.com/devices/hardware-table.html
[2] https://web.archive.org/web/20240731150632/https://devicehunt.com/
view/type/pci/vendor/8086/device/9BA8
[3] https://web.archive.org/web/20230928015210/https://devicehunt.com/
view/type/pci/vendor/8086/device/9BA4
Change-Id: I776f434f3627d6fbd046a92eb736b1ffcac8274a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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According to the Intel GPU list[1], 0x3E9B is DID of "Intel UHD Graphics
630" for the Coffee Lake processor family and has already been added to
the pci_ids.h as PCI_IDE_INTEL_CFL_H_GT2.
At the same time, the real PCI DID for Comet Lake-H GT2 is 0x9BC2 [1],
which is missing in the file.
[1] https://web.archive.org/web/20240731152818/https://
dgpu-docs.intel.com/devices/hardware-table.html
Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84158
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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lpss_s0ix_enable is already defined as boolean:
`git grep lpss_s0ix_enable $(find -type f -name "*.h")
src/soc/intel/apollolake/chip.h: bool lpss_s0ix_enable;`
Change-Id: I34bd568defe202daaad6136b9c184bc292a226b3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Should make the sorting order of the paths more obvious.
Change-Id: Ie73e717f37f80a11a903e99cc094ea4d76e1ca1f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83827
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Alder Lake "Client" FSP paths have been replaced by symlinks to
Raptor Lake in the FSP repo. Hence we get the same files anyway and
can spare us to maintain the individual paths.
Change-Id: Ia9b256ce1940894e2cf31acaa4a83ea39f6723b6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Check that lnkCap supports ASPM L1, so set it to ASPM_L1
to avoid excessive power consumption.
BUG=b:364484621, b:361828368
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
w/o this CL -
```
lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl"
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+
```
w/ this CL -
```
lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl"
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
```
Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84241
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7050a4d12efd65c7026abf3e45961e2061b7170a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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These aren't used so remove them
Change-Id: I340b3474fba1bc7fbde520138ae99c3e355882bf
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I63612af7320dfdbe57029b898b4cf07e9d6f13b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Reporting the battery serial number to ACPI causes Windows to say
there isn't a battery present. As the serial number is as useful as
waterproof towel, don't do it.
Change-Id: I97a28b1d8d7bb45ea4790c8125cd3c1bc52ee5f9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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As the merlin EC supports both the IT8987 and IT5570, move the
check into the code so the same variant directory can be used
for both chips.
Change-Id: I8c43a367e42f7e56ddd26b1c8fe7bf4b275d4ac3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83632
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that the USB configs are in the devicetree, only the
bootblock_mainboard_early_init function remains in early_init.c. It is
identical between every variant except the E6230, which enabled fewer
decode ranges in the LPC_EN register. Enabling the additional decode
ranges probably shouldn't cause issues, so go with the majority.
TEST=Timeless builds do not change with the exception of the E6230.
Change-Id: Ic43915888f5893652991b7402ebab3bd3a2cf278
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Update eMMC DLL tuning values for improved initialization reliability.
BUG=b:361013271
TEST=Cold reboot stress test over 2500 cycles
Change-Id: Icd1f9c7bdec2bc99152a13ac4ce0724a26718a52
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84248
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Joxer experienced error messages during developer mode entry due to
failed USB-C1 probing.
This patch adds the `DB_USB DB_1C` probe directive to the `conn1`
device in the overridetree, ensuring USB-C1 is only probed when
`FW_CONFIG` supports the applicable hardware SKU.
This should resolve the error flood seen during dev mode entry on
Joxer.
BUG=b:364240631
TEST=Able to build and boot google/joxer to OS without any error.
w/o this patch:
send_packet: CrosEC result code 9
send_packet: CrosEC result code 3
Failed to get PD_MUX_INFO port1 ret:-3
update_all_tcss_ports_states: port C1: get_usb_pd_mux_info failed
send_packet: CrosEC result code 9
send_packet: CrosEC result code 3
Failed to get PD_MUX_INFO port1 ret:-3
w/ this patch:
No error reported during dev mode entry
Change-Id: I8cdefa01409d5a8a75032f30dacde40057e064dd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I3ac96786b4bbf7c8b3a8b57f58df396b1b754bd3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83953
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I991ce1e264c3ca01bc34904b5efe758a3eb58806
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83952
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<commonlib/bsd/compiler.h> is automatically included.
Change-Id: I653f6c6099512c6e5ab64207f99e7813e4403f05
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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The `!FSP_USE_REPO` is most specific, if we're not using the FSP repo,
we can ignore all the FSP-repo paths. Hence put these first.
Having `FSP_TYPE_IOT` selected is also more specific, we can ignore all
the "Client" paths then. This makes sure that we don't catch a "Client"
by accident (otherwise we'd have to add a `!FSP_TYPE_IOT` for those).
Change-Id: Ibe9931d8f964a337c46fde31a3bc22c69d40eded
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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BUG=none
TEST=emerge-{asurada, cherry, corsola, geralt, rauru} coreboot
Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84221
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Extracted from NDA spec #56995:
"The A/B recovery scheme formally separates the SPI flash space into
different partitions; a primary, “A” and secondary, “B”, which hold
the same set of system firmware. Under this scheme, the partitions A
and B can hold identical contents initially, but each partition can be
updated individually.
Normally the system boots from partition A, but if the A partition is
found to be corrupted, the system will switch to partition B and
boot. The OEM BIOS can then choose to continue the boot from partition
B, or repair partition A using contents from partition B."
The Cezanne platform supports both A/B recovery and no recovery
method. It needs this flag passed to amdfwtool to enable the A/B
recovery layout.
Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add a Kconfig choice to select the IGD UMA allocation, which selects a
precompiled ACPB binary with the corresponding UMA value set. Default
to the previous value (128MB) for non-ChromeOS builds, and 64MB for
ChromeOS as that is the value used there.
TEST=build/boot google/morphius, verify UMA size changes with selection
via dxdiag tool under Windows.
Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84237
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Xeon-SP supports MMIO high range, a.k.a. MMIO range above 4G. FSP will
assign domain MMIO high windows from this range.
However, there will be unassigned parts among these high windows for
non-domain device usage (e.g. misc devices belonging to an IIO stack
but not belonged to any PCIe domains under that stack). This will cause
segmentation in MTRR UC coverage.
For example, in SPR-XCC where only CPM0/HQM0 are supported and
instantiated to PCIe domains, MMIO ranges are still reserved for
CPM1/HQM1. See more at src/soc/intel/xeon_sp/spr/ioat.c.
Reserve MMIO high range as a whole under domain0/00:0.0. During MTRR
calculation, this reservation will connect the discontinued domain MMIO
high windows together to form one continuous range, and save MTRR
register usage from inadequacy.
This change is initially raised for SPR but could be effective for GNR
as well.
TESTED = Build and boot in intel/archercity CRB, MTRR register usage
decreases from 7 to 3 in 2S system.
TESTED = Only setting MTRR for below 4GB ranges test fails with
LinuxBoot on SPR (through x86_setup_mtrrs_with_detect_no_above_4gb)
tsc: Detected 2000.000 MHz processor
last_pfn = 0x2080000 max_arch_pfn = 0x10000000000
x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT
WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM.
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9
...
Call Trace:
? 0xffffffff8f600000
? setup_arch+0x4bb/0xaed
? printk+0x53/0x6a
? start_kernel+0x55/0x507
? load_ucode_intel_bsp+0x1c/0x4d
? secondary_startup_64_no_verify+0xc2/0xcb
random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0
---[ end trace 0e56686fd458f0c5 ]---
update e820 for mtrr
modified physical RAM map:
modified: [mem 0x0000000000000000-0x0000000000000fff] reserved
...
modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved
last_pfn = 0x6354e max_arch_pfn = 0x10000000000
Memory KASLR using RDRAND RDTSC...
x2apic: enabled by BIOS, switching to x2apic ops
Using GB pages for direct mapping
...
Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff]
DMA zone: 28769 pages in unavailable ranges
DMA32 zone: 19122 pages in unavailable ranges
BUG: unable to handle page fault for address: ff24b56eba60cff8
BAD
Oops: 0000 [#1] SMP NOPTI
CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2
...
Call Trace:
? set_pte_vaddr_p4d+0x24/0x35
? __native_set_fixmap+0x21/0x28
? map_vsyscall+0x35/0x56
? setup_arch+0xa00/0xaed
? printk+0x53/0x6a
? start_kernel+0x55/0x507
? load_ucode_intel_bsp+0x1c/0x4d
? secondary_startup_64_no_verify+0xc2/0xcb
CR2: ff24b56eba60cff8
---[ end trace 0e56686fd458f0c6 ]---
RIP: 0010:fill_pud+0xa/0x62
...
Kernel panic - not syncing: Attempted to kill the idle task!
---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---
Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83538
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use the AZALIA_PIN_DESC macro from include/device/azalia_device.h
instead of magic numbers, as well as the enums for each of the register
field values. The macros were generated by running util/hda-decoder
against the original azalia logs used for the original board ports.
TEST=Timeless builds for all variants did not change between main
and this patch
Change-Id: If5ecee39efbddbba101f820dead82efcb848b6bc
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84099
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Add a Kconfig choice to select the IGD UMA allocation. Default to the
previous value (32MB).
TEST=build/boot google/liara, verify UMA size changes with selection.
Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84235
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add definitions for the GPIO pins on Panther Lake SoC,
as well as GPIO IRQ routing information and defines for ACPI ASL.
For now, add the following GPIO communities and GPIO groups:
Comm. 0: GPP_V, GPP_C
Comm. 1: GPP_F, GPP_E
Comm. 3: CPUJTAG, GPP_H, GPP_A, VGPIO3
Comm. 4: GPP_S
Comm. 5: GPP_B, GPP_D, VGPIO
ref doc:
- PT EDS vol2
- Panther Lake H GPIO Implementation Summary (#817954)
BUG=b:348678529
TEST=Verify on Intel Silicon platform for PTL using google/fatcat
mainboard. Note that these GPIO changes cannot be verified along as
they are merely data structure and defines for the SOC. With the
GPIO ASL, we should see the following GPIO instances under
/sys/bus/acpi/devices when booting to OS:
INTC10BC:00/ INTC10BC:01/ INTC10BC:02/ INTC10BC:03/ INTC10BC:04/
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Based on DOC #767454 (public) version 1.2. Allows to boot the
HARDKERNEL ODROID H4+ with N97 SoC. Without this patch the MCH ID
was not recognized and the SA driver did not pick up the stolen
ranges, causing the PCI MMIO allocation to be placed in the stolen
areas.
TEST=Boot HARDKERNEL ODROID H4+ with N97 SoC to Ubuntu 23.04.
Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84212
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add a Kconfig choice to select the default IGD memory allocation, for
users/boards which do not use an option table to set it.
TEST=build/boot google/link, verify IGD size changes with selection.
Change-Id: I83d57cf4657cfccbb21416c5da05eeff9e95a44f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Reduce resume time.
BUG=b:361728839
TEST=emerge-dedede coreboot chromeos-bootimage
& test touchscreen function on awasuki DUT
Change-Id: I32b2b1c709ecab964a0e449d416c5d0ee2c1d97d
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84196
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Move the `BUILDING_WITH_DEBUG_FSP` Kconfig option from SoC-specific
files to the FSP2_0 driver Kconfig to avoid duplication. Also slightly
improves the option's prompt and help text.
TEST=Built and booted google/rex successfully.
Change-Id: I5c3dce59c396f6c1665a3ed1b8c1bb5df0f5a8d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds a new Kconfig option `FSP_PUBLISH_MBP_HOB` to
control the creation of the ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
Disabling this option can improve boot time on platforms that
do not utilize the MBP HOB, such as ChromeOS devices.
The option is disabled by default on ChromeOS and enabled
by default on other platforms.
On ADL-P based platforms, this option is forced to be enabled
as ADL-P FSP relies on MBP HOB for ChipsetInit version for
ChipsetInit sync.
Removed SoC specific implementation of `FSP_PUBLISH_MBP_HOB` config
from MTL and TGL config file.
TEST=Tested on ADL-P and ADL-N platforms. Verified that MBP HOB is
created when `FSP_PUBLISH_MBP_HOB` is enabled and not created when
it is disabled.
Also verified that the system boots successfully in both cases.
Change-Id: I21da00259c0b9bcca6f545291a6259e9cce8d900
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Signing is performed with test keys by default, set
CONFIG_SIGNING_KEYS_DIR to a non-empty value to use other keys.
Depending on the version of the Talos II firmware this alone might not
allow booting because coreboot replaces only part of the stock firmware
and its newer versions enable secure boot by default (not to be confused
with SecureBoot in EFI). The signing performed in this commit is still
a prerequisite and might as well be done on its own. Fixing operation
with newer stock firmware will be done in a follow-up change.
Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 22.04
* Manjaro 22
No known issues.
https://starlabs.systems/pages/byte-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idff2d883a8c29f0fee9d633708aac92061a45132
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Add specific virtual wire mapping structure for:
- First pad group does not starts with bit position 0.
- vw_index and position are not continuous in between groups within a
community.
BUG=
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I986d4f4fe59b110e5075cab8742dfe8b336d034b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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According to the Intel OPS spec, the DC power from display is
12~19V@8A max. It can't set PsysPmax by unknown voltage, so get
voltage by ec command "ectool adcread 4" then calculate PsysPmax value.
The OPS display can supply 90W power, configure psys_pl2 to limit
the system power to 90W.
BUG=b:329037849
BRANCH=firmware-brya-14505.B
TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk
intel-rplfsp intel-adlfsp coreboot chromeos-bootimage
Check adcread value by ectool adcread 4. If get 19540, PsysPmax
should be 19540 * 8000 ~= 156 W.
Check FSP debug log have the following message.
PsysPmax = 156W
Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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This patch skips event logging for current boot information at ramstage
if CSE sync is scheduled at payload. Given that CSE sync could initiate
a system reset, resulting in redundant boot information logs, the
payload should handle the logging of boot information following CSE
sync.
BUG=b:360082747
TEST=Verified elog boot info is not logged at ramstage
Change-Id: Ia29ec350facc6850c04bb988027ecb146e648a50
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84120
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support to configure GPIOs to pull for external interrupts (EINT).
BUG=b:334723688
TEST=Talk with Ti50 TPM using IRQ flow.
Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84026
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add control for the 1.2V enable pin in VCM to comply the mipi camera
power sequence.
2.8V enable --> 1.2V enable --> reset
BUG=b:362386165
TEST=Run ITS test
Change-Id: I495b2e266ee3d24ed3334bb9c173b3993d095e8e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84211
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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$ build/cbfstool build/coreboot.rom print
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs_master_header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 18495 LZ4 (30096 decompressed)
fallback/ramstage 0x4940 stage 24288 LZMA (61240 decompressed)
config 0xa880 raw 1324 LZMA (3308 decompressed)
revision 0xae00 raw 726 none
build_info 0xb100 raw 122 none
(empty) 0xb1c0 null 347108 none
header_pointer 0x5fdc0 cbfs header 4 none
Change-Id: I8541aa6f1429ed6143830ed11c47c150183ddf0d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67064
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings.
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84198
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Power consumption according to RTS5227 datasheet section 6.4, L0s is not supported, so set it to ASPM_L1.
lspci -vvvv -s 01:00 to verify LnkCtl: ASPM L1 Enabled.
BUG=b:359409425
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: I87bb0d195566d273951dee6eeb54c9b388dd7607
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84177
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update PL1 Min value from 6W to 15W based on the brox thermal cooling
capacity and hardware design.
BUG=None
BRANCH=None
TEST=Build and boot on brox board
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are one too many acpigen_pop_len calls in the code
to generate the ROTM; remove one to fix an EMERG warning:
[EMERG] ASSERTION_ERROR: file `src/acpi/acpigen.c`, line 38
The extra acpigen_pop_len() call was added commit
45d2c3d5436e ("i2c/drivers/generic: Return ROTM in a package").
Change-Id: I913022144813f7f65eac1bcb7c97656f2c513c0b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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iasl refuses to perform an arithmetic computation in a QWordMemory
parameter and fails with the following error.
dsdt.asl 2149: 0x4010800000, ((0x4010800000 + 0x10000) - 1), 0x0,
Error 6051 - ^ Address Min is greater than Address Max
This commit replaces the arithmetic with the result to define
IOM_BASE_ADDR_MAX.
BUG=b:348678529
TEST=Build for google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f16
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84216
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When world-facing camera is absent, coreboot need to enable
GPP_R6(DMIC_WCAM_CLK) and GPP_R7(DMIC_WCAM_DATA) for 3rd dmic support
BUG=b:333973512
TEST=Boot google/riven to OS and verify 3rd dmic working properly.
Change-Id: I6c8780ce37b5d3987f5cdf6e6e6d0b4896b33230
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84141
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Change-Id: I62d0e324329fdde599e67efb23f813e3b3c650ef
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84199
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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With `probe unprovisioned` fw_config rule, there is no need to define an
explicit STORAGE_UNKNOWN option. Hence remove it.
BUG=None
TEST=Build Jubilant FW image.
Change-Id: I4f6ace4b39a1ee0b63486d3872b20c8da719ae4a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84095
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block.
This will include GPE1 blocks to FADT with their info.
BUG=362310295
TEST=boot to OS and check that FADT table include GPE1.
FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Introduces the BIT_FLAG_32(x) macro to create a 32-bit mask with the
designated bit set. This ensures compatibility with the 32-bit
'GEN_PMCON_A' register on 64-bit systems, where 1ul is 64 bits wide and
could potentially cause an overflow when shifted beyond 31 bits.
Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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This patch refactors ITSS related SoC specific macros by consolidating
them into a common itss.h file. This improves code maintainability and
reduces redundancy as each SoC previously defined the same macros.
Specific changes include:
- Move SoC specific ITSS macros into intelblocks/itss.h.
- SoC code now includes intelblocks/itss.h instead of the SoC-local
soc/itss.h.
- Drop soc/itss.h from static ASL files.
- Delete soc/itss.h from all SoC locals except Apollo Lake and
Sky Lake.
TEST=Able to build and boot google/hatch, google/xol and google/karis.
Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Tune I2C2 timing:
Set falling time to 250ns from 400ns to meet spec: "THIGH>0.6us"
BUG=b:362685374
TEST= Build jubilant firmware
Measure the i2c signal on jubilant to meet spec:
I2C2 THIGH from 0.494 us to 0.76 us
Change-Id: I42a60edc0b361bfabacf5376ef89f436efedb356
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84143
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Details:
- Add (POWER_CTL) – Offset 0x1fc required bits.
Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Details:
- Add (TM1_TM2_EMTTM_ENABLE_BIT) - Offset 0x1a0 required bits
- Add (IA32_PACKAGE_THERM_INTERRUPT) – Offset 0x1b2 required bits
Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84174
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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This patch removes the GPIO_IRQ_START and GPIO_IRQ_END definitions
from itss.h for Alder Lake, Cannon Lake, Elkhart Lake, Jasper Lake,
Meteor Lake and Tiger Lake. These definitions are no longer needed.
TEST=Able to build and boot google/xol and google/karis.
Change-Id: I60a08ba2c894fd1c1af6c6aef3ddc4a33ec63e76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84182
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change removes the unused pch_handle_sideband() function from the
Meteor Lake platform code.
TEST=Able to build and boot google/rex.
Change-Id: Idd14748aa1d917d6e88d738541a737c04a2c6a15
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Change-Id: I41a877ed7f5f3d02904dc939b32996a7f6d45373
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I80ad02ca016ad2c8d0bfeb33e8309002dfe723c0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: If1cb63847ffbfed9bb09679931cfb23289bf59f0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I569b9a69add341bcefe6bd5356b01a95a4e97286
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
|
|
Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Generate RAM IDs of lp5 memory:
1)Hyinx 4GB*4 H58G56BK8BX068
2)SAMSUNG 4GB*4 K3KL8L80CM-MGCT
BUG=None
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I6b6e351ceaacfd65eae7b1db14c195b34359689a
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
|
|
Modify the FP IRQ pin to GPP_D13 from GPP_F15 from HW change on EVT.
The design change to follow the brox's GPE0 routing, and the
FP wake source can be routed.
BUG=b:363166664
TEST= Build jubilant firmware
Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84124
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add initial support for the LattePanda Mu board, which features:
- Intel Alder Lake-N N100 processor
- Samsung K3LK7K70BM-BGCP, 8GB LPDDR5 memory
- Samsung KLMCG2UCTA-B041, 64GB eMMC storage
- SO-DIMM 260-pin connector for function expansion
This commit includes:
- Basic board configuration
- Memory initialization
- Essential I/O setup
- Used UEFITool NE alpha 68 (Nov 4 2023) to extract data.vbt file
from original BIOS
- BIOS download link: https://github.com/LattePandaTeam/LattePanda-Mu
located at "./Softwares/BIOS/DFLT/LP-BS-S70NC1R200-SR-A.bin.zip"
Test Environment:
- Carrier Board: Lite
- Payload: mrchromebox/edk2
- EDK2 Version: uefipayload_202309
Test result
Passed:
- Windows 11 boot from eMMC
- Install Ubuntu 24.04 on NVMe SSD
- Ubuntu 24.04 boot from NVMe SSD
- USB 3.0/2.0 functionality
- Realtek RTL8111H-CG-RH Ethernet
- HDMI Display
- Audio over HDMI work in Ubuntu 24.04
Known Issues:
- S3 sleep mode non-functional
- Power-on after shutdown requires power removal
- SuperIO UART not detected in Windows 11
- Audio over HDMI not work in Windows 11
- Windows 11 BSOD occurs with NVMe SSD installed:
- Stop code: Machine Check Exception
- NVMe SSD not working on Windows 11, except when:
- KDNet Debugging enabled on NIC during boot
- SSD becomes functional in this scenario
Change-Id: I79696bdd837a221860b32f54629212c3346dca66
Signed-off-by: KunYi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
GCC LTO found this.
Change-Id: I2d5a9a86dbb91a5505891a30c6e9072b1b4dfc92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84056
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
De-assert PERST# at romstage to reduce the waiting time in ramstage.
Before
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries)
```
After
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST#
[DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST#
[INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries)
```
BUG=none
TEST=boot from NVMe
Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Even we assert PRSET# early to save the delay between PERST# assertion
and de-assertion. MediaTek PCIe driver still takes 47ms waiting for PCIe
link up. (1ms delay for each try)
```
[INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries)
```
Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIe
reset. So we can de-assert PERST# at early stage to improve the boot
time.
BUG=b:361728592
TEST=emerge-cherry coreboot
Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84117
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
|
|
Add support for creating a DSM Method for Intel Bluetooth that
is outlined in Intel's connectivity integrated guide (which has
no document number).
It supports two GUIDs:
Set Tile Activaction (2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9)
BIT(0) Indicates whether the device supports other functions
BIT(1) Set Tile Activation
Check/Set Reset Delay (aa10f4e0-81ac-4233-abf6-3b2ac50e28d9)
BIT(0) Indicates whether the device supports other functions
BIT(1) Set Bluetooth reset timing
Change-Id: Icc18f867604876b27ced2ee4356e47b3aa6b4f74
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84133
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
On the non-vboot boot path, eSPI is configured as part of
fch_pre_init(), and we need to ensure that the mainboard sets the
eSPI GPIOs properly before the common SoC code performs eSPI init.
Use the mb_set_up_early_espi() function to set the eSPI GPIOs at
the correct time.
TEST=build/boot google/zork (morphius), verify keyboard functional.
Change-Id: I03efe6def37a018c3de410523be21bf008174e94
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84148
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now that zork can boot without vboot, ensure that the GPIOs set in
verstage are programmed in bootblock on the non-vboot path.
The eSPI GPIOs will be set in a subsequent patch using
mb_set_up_early_espi() since setting them in
bootblock_mainboard_early_init() would be too late given when the
SoC eSPI init takes place.
TEST=build/boot google/zork (morphius) w/o vboot
Change-Id: I0bb49678b2d913c447d5bc761a6f0e00fca6334f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add a new fw config field for wifi category as WIFI_6_8852, which is
PCIe based. Also, enable WIFI_6_8852 for existing PCIe based wifi port
as well as bluetooth port.
BUG=b:356434907
BRANCH=NONE
TEST=Verified Wifi6 module detection
Change-Id: Ib6ba641c23cce7f1253022c9bb78b986b323bcaa
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84138
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login
screen, it is because it inserts 12 blank frames if it receives the
unmute in VB-ID.
Always override the mute in VB-ID to avoid Tcon EC detected the
audiomute_flag change.
BUG=b:360243615
BRANCH=firmware-nissa-15217.B
TEST:Verfied on Teliks and cannot reproduce the issue
Change-Id: Iff488f6844c717ef24069c7176e7b8dfb07d8abc
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84137
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
|
|
Change-Id: Ida4461de6275bdd314f5cba441d3ff631d570305
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
CAPID_A, BDSM and BGSM registers may not exist on specific platform,
this patch add `HAVE_CAPID_A_REGISTER` and `HAVE_BDSM_BGSM_REGISTER`
to select them.
Change-Id: I4d1197b8b1071aefc2ea1ed2f707d769aabab5e4
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
Add EARLY_INIT_PCIE_RESET for early PERST# de-assertion.
BUG=b:361728592
TEST=emerge-cherry coreboot
Change-Id: I7ab85694e85a4c3f77fefc22efe16734c347a716
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
|
|
mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c.
BUG=b:361728592
TEST=emerge-cherry coreboot
Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Use clr/setbits32p to make code cleaner.
BUG=none
TEST=emerge-cherry coreboot
Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
|
|
Currently pcie.c is built into ramstage only, where DEVTREE_CONST is an
empty macro, so there's no problem with that. However, if we would like
to include that file in pre-ramstage, then DEVTREE_CONST would be
'const', leading to the following build error:
```
src/soc/mediatek/common/pcie.c:104:26: error: assignment discards
'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
104 | root_dev = pcidev_path_on_root(devfn);
| ^
```
BUG=none
TEST=emerge-cherry coreboot
Change-Id: Ia7c95424019ec0dca50bbc6be7f81b6180d06d6e
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84113
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Bluetooth driver in kernel requires reset-gpio in current resource
settings (_CRS) and device specific data (_DSD) ACPI objects. Hence
remove ACPI Power Resource for Bluetooth device so that the concerned
ACPI objects get populated.
BUG=b:362817900
TEST=Build Brox Firmware image and boot to OS. Ensure that the _CRS and
_DSP ACPI objects are filled in the SSDT with the required data.
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x004D
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"reset-gpio",
Package (0x04)
{
\_SB.PCI0.XHCI.RHUB.HS10,
Zero,
Zero,
One
}
}
}
})
Change-Id: If6e679aa3f4181e7963ac53d0847b1512959b3a7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84135
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
|
Update dptf settings from thermal design:
1) Remove fan control and active policy,
since fan is controlled by EC.
2) Modify TSRs to 0:DRAM, 1:SOC, 2:Charger
3) Update Pl2 min&max values
BUG=None
TEST= Build jubilant firmware
Generate and check ACPI SSDT.dsl
$ cat /sys/firmware/acpi/tables/SSDT > SSDT
$ iasl -d SSDT
Change-Id: I2d59eedea9fb25565709e118abc1a14b4c2a64e7
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
|
|
Change-Id: I46021accacbb911d7a7ecfdbb52973a7da78f36e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The cw-al-4l-v1.0 mainboard has two USB2 ports on a 2x5 pin header on
the mainboard and likely also routes one USB2 port to the m.2 E key slot
which is typically used for Bluetooth support when an E key m.2 WIFI +
Bluetooth card is installed.
This is untested, since I only have the cw-al-4l-v2.0 mainboard, but
from looking at the documentation of the version 1 and looking at how
things are done on the version 2 this should be correct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7059a3f2d9cde0086382a4484c09d5ef33dc906d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83910
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
- Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID.
- Change cpu_port field to 16-bit width if the Kconfig is set.
BUG=none
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field. The bit 15:8 of the returned port ID value should be 0xF2
instead of zero.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83981
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1) Add all required changes for eSOL support.
2) Select MAINBOARD_USE_EARLY_LIBGFXINIT for Trulo.
The CSOT (MNC207QS1-1) panel is used for the devicetree.
BUG=b:362895813
TEST=On-screen text message seen during MRC training on Trulo SKU1.
MRC: no data in 'RW_MRC_CACHE'
bootmode is set to: 0
DP PHY mode status not complete
DP PHY mode status not complete
DP PHY mode status not complete
...
Informing user on-display of memory training
Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84128
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
|
|
Previously, `early_graphics_stop()` was skipped unconditionally if
`CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` was enabled. This led
to overlapping screens when CSE sync was not triggered in ramstage,
as both the eSOL message and the firmware splash screen would be
displayed.
This change refactors the condition for calling `early_graphics_stop()`
to ensure it is only skipped if a CSE firmware update is actually
required *and* `CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` is set.
This allows eSOL to display its message during CSE sync, but tears
down early graphics programming in other cases to prevent overlapping
screens.
Additionally, this change ensures that `early_graphics_stop()` is the
last function called by the romstage to guarantee proper cleanup.
BUG=b:362895813
TEST=Able to boot google/tivviks_ufs without overlapping screens.
Change-Id: Idc01bfc8963d65fcb0441300e7c9267eaaefefb9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
|
Update verb table provided by Realtek on 20240710.
Restults: SNR > 90 (spec>=90).
BUG=b:349996984
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: Ic4f03d09010efa7e32713b2697d5832255f64317
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83920
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
src/acpi/sata.c: In function 'generate_sata_ssdt_ports':
src/acpi/sata.c:27:29: error: initializer-string for array of 'char' is too long [-Werror=unterminated-string-initialization]
27 | char port_name[4] = "PR00";
| ^~~~~~
Change-Id: Ie80c2329c4a2698bd9e72ba1b36c1c05e37b214b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Sumeet Pawnikar <sumeet4linux@gmail.com>
|
|
Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Icc01852dc5bd04cfa151e8fa7c5bcc160ed978c6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84156
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
How it approximately works:
(During a normal system run):
1. OS puts a capsule into RAM and calls UpdateCapsule() function of EFI
runtime
2. If applying the update requires a reboot, EFI implementation creates
a new CapsuleUpdateData* EFI variable pointing at the beginning of
capsules description (not data, but description of the data) and does
a warm reboot leaving capsule data and its description in RAM to be
picked by firmware on the next boot process
(After DEV_INIT:)
3. Capsules are discovered by checking for CapsuleUpdateData* variables
4. Capsule description in memory and capsule data is validated for
sanity
5. Capsule data is coalesced into a continuous piece of memory
(On BS_WRITE_TABLES via dasharo_add_capsules_to_bootmem() hook:)
6. Buffer with coalesced capsules is marked as reserved
(On BS_WRITE_TABLES via lb_uefi_capsules() hook:)
7. coreboot table entry is added for each of the discovered capsules
(In UEFI payload:)
8. CapsuleUpdateData* get removed
9. coreboot table is checked for any update capsules which are then
applied
Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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By default, QEMU bails when trying to use bigger images mounted with
'-drive if=pflash', which is required to make use of writable flash
introduced in CB:82555. This changes both default size in Kconfig as
well as FMAP layouts.
Since QEMU 5.0.0 it is possible to change the limit of firmware size
with `max-fw-size` machine configuration option, up to 16 MiB, as bigger
sizes would overlap with IO APIC memory range. Default is still 8 MiB,
so it makes sense to have identical default in coreboot.
Error thrown by QEMU when trying to use too big ROM:
qemu-system-x86_64: combined size of system firmware exceeds 8388608 bytes
Change-Id: If36cb754a8e75e23bce49ff568dd88e5db279bb8
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82639
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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qemu-system-x86_64 uses AMD64 SMM save state format, despite emulating
Intel chipset. In addition, even though it implements SMI_STS register,
QEMU never sets any bits in it. As there is little emulated hardware
that can be generating SMI, assume that all SMIs come from APM. This
source is used e.g. to disable ACPI (which wasn't working until now on
QEMU) and SMMSTORE.
Tested by invoking SMMSTORE commands from the payload with SMM logging.
Change-Id: I2fc7b74bdc13be8d76bc536283ab5a14fffec45f
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82558
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To support Widevine DRM, enable VBOOT_DEFINE_WIDEVINE_COUNTERS.
BUG=b:357976379
TEST=emerge-rauru coreboot
BRANCH=none
Change-Id: I3760c30b175338165f8e11b59c7cfa830070a19e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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GCC with LTO caught this.
Change-Id: I9f78b9973729bdedb40bd63b8989e94c9c498814
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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