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| author | Arthur Heymans <arthur@aheymans.xyz> | 2024-08-23 11:19:20 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2024-08-30 07:37:29 +0000 |
| commit | c1ca6588bd1bdf85e69a9e61013135ec0750ee62 (patch) | |
| tree | 7ed3233c8531f16763d39083bae9ebbb7ea7045c /src | |
| parent | bf4e28484a5c8d1da2f90fba983a5e763946bcb0 (diff) | |
nb/intel/sandybridge: Fix uninitialised variable
GCC with LTO caught this.
Change-Id: I9f78b9973729bdedb40bd63b8989e94c9c498814
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 8a8bd8310b..d5e1a7c09a 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -340,7 +340,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; spd_ddr3_raw_data spds[4]; - size_t mrc_size; + size_t mrc_size = 0; ramctr_timing *ctrl_cached = NULL; timestamp_add_now(TS_INITRAM_START); |