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2024-08-10device/dram/spd: Add missing <smbios.h>Elyes Haouas
Use of smbios_memory_type needs <smbios.h>. Change-Id: Iacab6171c61abd047c09ff7e20313a455bd8414f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-10soc/mediatek/common: Refactor EINT driverYidi Lin
Refactor EINT driver by - Move `pos_bit_calc_for_eint` to `common/gpio_eint_v1.c` and rename to `gpio_calc_eint_pos_bit`. - Implement `gpio_get_eint_reg` to obtain EINT base address. This change is prepared for the driver change in MT8196. BUG=b:334723688 TEST=EINT works on Geralt Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83703 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-10soc/intel/common/block/gpio/gpio.c: Improve GPIO debug infosYuchi Chen
1. print host software ownership, SMI enable and NMI enable registers after configuring 2. read and print GPIO configuration dword registers after writing 3. use %zu to print size_t values according to CI reporting. Change-Id: I8820956f6db91c7bcc26b46a4361da3dfa8f77b5 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83316 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09soc/amd/*: pass PSP RPMC NVRAM base and size to amdfwtoolFelix Held
Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa and Stoneyridge which don't use/support this. If a mainboard has an section named 'PSP_RPMC_NVRAM' in its FMAP file, the start and length of it in the flash will be passed to amdfwtool which then adds the base and length to the corresponding type 0x54 PSP directory table entry. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9f8a7eec68a5222be63e46173132f1c4a461b4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/83815 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-09mb/lenovo/t520: Add USB port config into devicetreePuFF1k
Devicetree for lenovo/520 is missing USB ports config, hence they don't work. This change introduces USB port config. Tests performed: - Can select a boot media using a USB keyboard from any port. - Can boot from each port except usb@1:1.1. - Measured read speed from a thumb drive on each port 24.5-28.9 MiB/s. Change-Id: I96dba153a563e0e290b96b837fdca39d7598ef17 Signed-off-by: PuFF1k <exopuf@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-09mb/emulation/qemu-q35: Move QEMU specific macros to "q35.h"Elyes Haouas
As `qemu-q35/memmap.c` includes `qemu-q35/q35.h`, move macros into q35.h file. Change-Id: I0bf13def8bc4510053f6bb44e043bbcb0b958b01 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-09vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compileSaurabh Mishra
Details: - Skeleton files to compile google/fatcat mainboard. BUG=b:348678529 TEST=Build verified on with using PTL SOC and google/fatcat mainboard. Change-Id: I4c069ba64f487259ce746dc52296618d91209602 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83732 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-08-09device/pci_ids: Add new Intel PTL device IDs for TracehubBora Guvendik
This patch adds new North Peak PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the tracehub driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Boot to OS using PTL Silicon, verify if above 4GB IMR region is reserved. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ifa1a0a57c504e06d686e7e0826547251b456cc8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83786 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09mb/google/brox/jubilant: Add Fn key scancodeMorris Hsu
The Fn key on jubilant emits a scancode of 94 (0x5e). BUG=b:324079605 TEST=Flash jubilant, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I963b0aa85598097fea69ec34d1e79ec0bbec3db3 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83821 Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09superio/ite: Remove custom ITE GPIO drivers and codeMichał Żygowski
Since a generic ITE GPIO driver is available and in use, the existence of chips-specific drivers no longer make sense. Remove the dead code in favor of generic GPIO driver. Change-Id: I7e031d12192af4bd47923d87c1d02c64f9c851a2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83497 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09superio/ite,mb: Switch to new ITE GPIO driverMichał Żygowski
Refactor mainboards' code to use the new GPIO driver. TEST=Put Google Jecht to S3 sleep and check if the LED blinks. Change-Id: I707ee090ee2551b4935847e12ade678d36ff9302 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-09mb/google/brox/var/jubilant: Add SAR sensor SX9324Ren Kuo
Add SAR Sensor SX9324 for WWAN: - Apply DRIVERS_I2C_SX9324 - Config GPP_H19 for IRQ - Add SX9324 registers settings based on tuning value from SEMTECH. Refer to datasheet: https://chromeos.google.com/partner/dlm/avl/component/3624/ BUG=b:345327104 TEST=Build and verify on jubilant Change-Id: I629117f20ca513dc0c8eaa91744ad33e162ba4bb Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83779 Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-09mb/google/brox/var/lotso: Enable wifi sarKun Liu
wifi.SetTXPower test fail, so enable wifi sar. BUG=b:351698478 TEST=emerge-brox coreboot Change-Id: Ibf5425e72eddc45e376ef4e2d077180dab502200 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-09vc/intel/raptorlake: Update header files from 4435_00 to 5045_00Kulkarni, Srinivas
Update header files for FSP for Raptor Lake refresh platform to version 5045_00, previous version being 4435_00. FSPM: 1. Add IgdGsm2Size UPD 2. Comment added for Offset 0x0AB6 FSPS: 1. Add CepEnable UPD 2. Offset size updated for UPD ReservedCpuPostMemProduction 2. Comment added for Offset 0x104C MemInfoHob: 1. Structure updated BUG=b:355384183 Kit:https://www.intel.com/content/www/us/en/secure/design/confidential/ software-kits/kit-details.html?kitId=815173 Cq-Depend: chrome-internal:7554984 Change-Id: I80cccb6aaa8f3a97d860a1e7908bfac0435b1aec Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-09mb/google/nissa/var/riven: Add G2 touchscreen supportDavid Wu
This change adds the necessary configuration for the G2 Touchscreen(GTCH7503) device, connected to I2C bus 40. It includes settings for: * HID descriptor * Device description * IRQ configuration * Detection * Reset and enable GPIOs with their respective delays * Power resource handling * HID descriptor register offset BUG=b:350844195 TEST=emerge-nissa coreboot boot with G2 TS, make sure G2 TS is functional. Change-Id: If17367cd62eb69a1237efe4aa3ca1a0c9640ba4c Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83823 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09mb/google/trulo: Enable EC MKBP deviceAmanda Huang
MKBP device is required for passing events from input sources to AP. Input sources include buttons (power, volume); switches (lid, tablet mode) and sysrq. BUG=b:357521411 TEST=Build coreboot and switch tablet mode on orisa. Change-Id: Ic712f53fb4063347c38df05167f0100afc06f979 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83819 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-09soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSIONSubrata Banik
This change adds support for specifying the CSE_RW_VERSION directly in Kconfig. * If `CONFIG_SOC_INTEL_CSE_RW_VERSION` is defined, its value will be used directly as the CSE_RW version. * Otherwise, the version will be extracted from the CSE_RW binary file as before. Platform prior to Intel Meteor Lake still requires to override the CSE RW version using CONFIG_SOC_INTEL_CSE_RW_VERSION config rather reading the CSE RW version from CSE RW partition. BUG=b:327842062 TEST=CSE RW update successful on Karis with this patch using below recipe: 1. Overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="18.0.5.2269" 2. Without overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="" Platform prior to Intel Meteor Lake would be using #1 and platform starting with Meteor Lake expected to use #2 recipe. Change-Id: I1327c813b7aef77c65766eb9c40003bb8a71d4b6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83831 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-09mb/google/fatcat: Add support for soldered-down memorySubrata Banik
This change adds support for soldered-down memory on the Fatcat board. It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes the necessary Makefiles adjustments to handle SPD data in CBFS when this option is enabled. * A new Kconfig option `MEMORY_SOLDERDOWN` is added to control soldered-down memory support. * When `MEMORY_SOLDERDOWN` is enabled, it selects: * `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled * `HAVE_SPD_IN_CBFS` * The Makefile is updated to include the `variants/$(VARIANT_DIR)/ memory` subdirectory and conditionally include the `spd` subdirectory based on `CONFIG_HAVE_SPD_IN_CBFS`. BUG=b:348678071 TEST=Able to build google/fatcat with N-1 silicon. Change-Id: I7edc1134630940812186118a29cbbd550f0e3634 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-08-09mb/google/fatcat: Generate LP5 RAM ID for `H58G56BK7BX068`Subrata Banik
Add the support LP5 RAM parts for fatcat: DRAM Part Name ID to assign H58G56BK7BX068 0 (0000) BUG=b:347669091 TEST=emerge-fatcat coreboot Change-Id: Idcdbbcd42dc6b1c8b13a89b1ace5b2973dde6d2b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83824 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2024-08-09mb/google/brya: Enable storing ISH FW version for truloSubrata Banik
This change enables storing the ISH firmware version on the Trulo baseboard by selecting the `SOC_INTEL_STORE_ISH_FW_VERSION` config option. BUG=b:354607924 TEST=Able to dump ISH version on trulo. > cbmem -c | grep ISH [DEBUG] ISH version: 5.4.2.7780 Change-Id: I69a7fa19c53f435ef1f6306b259f703c7b196137 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83820 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-09soc/intel/cmn/pmc: Add API to dump silicon QDF informationJamie Ryu
This adds pmc_dump_soc_qdf_info function and PMC_IPC_CMD_SOC_REG_ACC PMC IPC Command to read and print Intel SoC QDF information using PMC interface if SOC_QDF_DYNAMIC_READ_PMC is enabled. QDF read command is supported from Panther Lake SoC. QDF is a four digit code that can be used to identify enabled features and capabilities. This information will be useful to debug issues found during the development phase and in the field as well. Change-Id: I927da1a97e6dad4ee54c4d2256fea5813a0ce43d Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83784 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-08soc/amd/*: pass PSP NVRAM base and size to amdfwtoolFelix Held
Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa which doesn't use/support this. This was previously only implemented for Picasso, but not for the SoCs that support this, so add the support to those other SoCs as well. If a mainboard has an section named 'PSP_NVRAM' in its FMAP file, the start and length of it in the flash will be passed to amdfwtool which then adds the base and length to the corresponding type 0x04 PSP directory table entry. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I785ede8eb0df2473a4390b2c305add20f38d7ede Reviewed-on: https://review.coreboot.org/c/coreboot/+/83814 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-08soc/amd/picasso/Makefile: move PSP_NVRAM_[BASE,SIZE]Felix Held
Move PSP_NVRAM_BASE and PSP_NVRAM_SIZE from the BIOS directory table items to the PSP Directory Table items, since the corresponding region will be referenced by the PSP directory table and not the BIOS directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iff7568ea05c701ecd346cc7590cf93b091ff31a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83813 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-08commonlib/device_tree.c: Remove incorrect warningMaximilian Brune
Currently a warning is printed even if the maximum amount of nodes is not exceeded. Remove the warning, since in most cases the maximum amount of nodes for a given prefix is usually well known. For example the /cpu nodes always have a maximum of CONFIG_MAX_CPUS. One may also just want to read the first X amount of nodes matching a given prefix. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic1111e8acb72ea1e9159da0d8386f40cbbdbc63f Reviewed-on: https://review.coreboot.org/c/coreboot/+/83085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-08mb/google/dedede/var/awasuki: Add Fn key scancodeWeimin Wu
The Fn key on awasuki emits a scancode of 94 (0x5e). BUG=b:355538142 TEST=Flash awasuki, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: Ic7aa183bf314fed4901133dc70d848d84fab0784 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-08mb/google/dedede/var/awasuki: Enable ELAN touchscreen with fw_configWeimin Wu
1. Change driver form i2c/hid to i2c/generic. 2. Add fw_config for touchscreen. BUG=b:351968527 TEST=ectool cbi set 6 0x0x10200a0; touchscreen functions normally; Change-Id: Ifd6330be8924d4873f0efab3ce404168a62099eb Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83704 Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-08mb/google/brya/var/trulo: Update ISH GPIO's configurationVarun Upadhyay
This patch configures the GPIO pins to enable ISH on the Trulo device, in accordance with schematic_20240607. BUG=b:354607924 TEST=Builds successfully for google/trulo. Change-Id: I3af478762e0a0aa35a2698e0ed87a4d8c24362f0 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83781 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-08mb/google/brya/var/orisa: Update ISH GPIO's configurationVarun Upadhyay
This patch configures the GPIO pins to enable ISH on the Orisa device, in accordance with schematic_20240607. BUG=b:354607924 TEST=Builds successfully for google/orisa. Change-Id: I24745ba629c59c092ce676b29915e356a4d8d8af Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83656 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-08-07soc/amd/common/psp_smi_flash: add buffer overflow checksFelix Held
Before 'handle_psp_command' calls any of the functions in this file, it make sure that the 'size' field in the command buffer's header doesn't indicate that the command buffer is larger than the SMM memory region reserved for it. The read/write command buffer has a 'num_bytes' field to indicate how many bytes should be read from the SPI flash and put into the data buffer within the command buffer or how many bytes from this buffer should be written to the flash. While we should be able to assume that the PSP won't send us malformed command buffer, we should still better check this just to be sure. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4e8514eedc3ad154a705c8a1e85d367e452dbed Reviewed-on: https://review.coreboot.org/c/coreboot/+/83778 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi_flash: implement SPI read/write/erase commandFelix Held
Use coreboot's SPI flash access infrastructure to do the flash read, write, or erase operations as requested from the PSP. This patch is a modified version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I4957a6d316015cc7037acf52facb6cc69188d446 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-08-07soc/amd/common/psp_smi_flash: implement SPI info commandFelix Held
Detect the block size of the SPI flash and number of flash blocks reserved for the flash region corresponding to the 'target_nv_id' field in the command buffer. This information is then written to the corresponding fields in the command buffer. Since detecting the flash chip still might result in accesses to it, make sure that it's available for use and not currently used by an OS driver. Since this code is inside the SMI handler, we don't have to worry about this code to be interrupted, so we don't need to set some bit to tell other code that we're currently using the SPI controller in the SMI handler. This patch is a modified version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I19041a27a9e8f901d42c3f60af834df625455ea6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83776 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi_flash: add spi_controller_availableFelix Held
The SPI_SEMAPHORE_DRIVER_LOCKED bit in the SPI_MISC_CNTRL register doesn't affect the hardware, but it re-used by AMD as a semaphore to synchronize the access to the SPI controller between SMM and non-SMM software like an OS-level driver. Since it doesn't affect the hardware, it's marked as reserved in the PPRs. Add the 'spi_controller_available' helper function to check this bit to see if some software or driver outside of SMM is currently using the SPI flash controller to avoid interfering with that operation. This patch is a slightly reworked version of parts of CB:65523. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I49218e03a5dd555b2b2d34eaad86673e9fc908c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83775 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi_flash: add find_psp_spi_flash_device_regionFelix Held
Add 'find_psp_spi_flash_device_region' to get a pointer to the spi_flash struct of the SPI flash used in the system and the region_device struct for the target FMAP region specified by the target NV ID from the PSP to x86 mailbox command. In order to have small patches, the newly added static 'find_psp_spi_flash_device_region' function is marked as inline; that inline will be removed in a following patch that calls this new function. This patch is a slightly reworked version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I64b8fba2392de46ecd4c786cef0d5b6acdbd865a Reviewed-on: https://review.coreboot.org/c/coreboot/+/83774 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi_flash: validate target SPI region IDFelix Held
Add and use functions to validate the target non-volatile storage ID in the different command buffer structs. This patch is a slightly reworked version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: Idda0166c862d41d380b2ed21345eead5e0a1c135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83758 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi_flash: add command-specific data structuresFelix Held
This patch is a slightly modified version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I41efeecf9243ddbbd8dc3f842c5ce11058bb7999 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83757 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp: add and call PSP SMI SPI access function stubsFelix Held
Add stub functions for the SPI flash access from the PSP SMI handler and call them for the corresponding P2C mailbox commands. Parts of this patch are taken from CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: Iedbc9d41eb0d4e8d81eeba9c01281161eb839991 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83756 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07soc/amd/common/psp_smi: implement P2C mailbox handlingFelix Held
When the PSP wants to access the SPI flash during runtime, but isn't the owner of the SPI flash controller, it sends an SMI to the x86 side. The corresponding SMI handler then checks the P2C (PSP to core) mailbox for the command and data, processes the command, and if needed puts the requested data into the P2C buffer. The P2C mailbox is a memory region in TSEG aka SMM memory. Both location and size are communicated to the PSP via the PSP SMM info mailbox command which is sent right after mpinit is done. This commit adds the code to access the P2C mailbox to the PSP SMI handler code, but the handling of the actual mailbox commands the PSP sends to the SMI handler is added in later patches to keep the patch size manageable. This patch is a heavily reworked version of parts of CB:65523. Document #55758 Rev. 2.04 was used as a reference. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I50479bed2332addae652026c6818460eeb6403af Reviewed-on: https://review.coreboot.org/c/coreboot/+/83740 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-07soc/amd/common/include/spi: add and use SPI_MISC_CNTRL defineFelix Held
This register is currently used by the SPI DMA code that sets an undocumented bit. A later patch will add and use some other bit in this register. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I48447dcfb3cee07619a9b42434731f0b21458021 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83773 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-07mb/google/brox: Tune Touchpad I2C parametersKarthikeyan Ramasubramanian
Adjust Touchpad I2C fall time configuration such that it meets the I2C fast mode specification(<= 400KHz). BUG=b:328670295 TEST=Build Brox firmware and boot to OS. Confirm the I2C bus frequency(375 KHz), rise(650 ns) and fall(330 ns) times meet the specification. Change-Id: I0006bfb9bb5839ffa1248d9f2ea055160ed0936e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83755 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2024-08-07mb/starlabs/starlite_adl: Remove has_cdm from devicetreeSean Rhodes
The property `has_cdm` only existed in an early patchset, the version that was merged only requires `cdm_index` so remove the former that was added in c6c75dfbaeff208c17bb47fdede855286e12d857. Change-Id: I62a9456e9a4f1571328ba6fd09ae383a8fd11767 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83796 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-07mb/apple/macbookair4_2/dt: Move iGPU settings into igd device scopeFelix Singer
Change-Id: I3161c7d99a2d94d6c85a6c9652b8e78d3f447252 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-07mb/apple/macbookair4_2: Clean up devicetreeFelix Singer
Clean up the devicetree by removing settings set to 0, which are initialized with 0 anyway, remove superfluous disabled devices and also remove comments duplicating the device alias names. Change-Id: I07005ae1db7d92fd50e72351031a5eb491768d3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83782 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06mb/starlabs/starbook/rpl: Nit GPIO changesSean Rhodes
Remove some unused GPIOs and configurations for GPIO's that aren't even connected. Change-Id: I5b4691a0b5e8b1348304d11c1d59aa60517041ec Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83626 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06mb/starlabs/starbook/rpl: Disconnect wireless GPIOsSean Rhodes
The GPIOs for WiFi and Bluetooth are also connected to the EC. They are controlled from there so remove the configuration here. Change-Id: I7aef1b821420daf5ea9f6ae107021e5d406a5ec3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-06mb/starlabs/starbook/rpl: Disconnect SCI/SMI GPIOsSean Rhodes
The platform uses eSPI so these are not needed. Change-Id: I81470658263f4b601c9964ff5bed86b22d24df3b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83624 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06mb/starlabs/starbook/rpl: Add USB ACPI to devicetreeSean Rhodes
Use the USB ACPI to add entries for the USB and TCSS ports. Change-Id: Iab8b6e03c8c05e459fb354bc008109c873a4846f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83623 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06mb/msi/ms7d25,ms7e06: Enable discrete TPM module supportMichał Żygowski
Now that multiple TPM drivers may be compiled in, it is possible to support switching between fTPM and dTPM. The patch adds: - Device tree entry for PC80 discrete TPM - TPM PIRQ# GPIO active low routed to IOAPIC for TPM interrupt - MEMORY_MAPPED_TPM option to board's Kconfig to enable PC80 TPM driver When the ME is disabled, e.g. via HECI command, chipset will route the TPM traffic to SPI automatically. When a SPI TPM is connected to the JTPM1 on the board, it will be probed successfully and initialized in place of inactive PTT/fTPM. Change-Id: Ie6e7026b6f1cec842bce4ef40b6db7feb75200e3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80456 Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-06drivers/{crb,pc80/tpm}: Drop conflicting tpm_config_t typedefMichał Żygowski
When both CRB and pc80 TPM drivers are compiled in, building fails because the tpm_config_t typedef has two incompatible definitions. Given that typedefs are discouraged by the project's coding style, simply get rid of the tpm_config_t typedef. TEST=Compile MSI PRO Z690-A target with CRB and PC80 TPM chips enabled in devicetree. Change-Id: Id41717e265362303a17745303a907c9c8f4f4e12 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82057 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-06intel/alderlake: Add helper functions for Power ManagementSean Rhodes
Clock Power Management, ASPM and L1 Substates have been configured the same way since Skylake. The main control to enable or disable is Kconfig, and then the level can be overridden in devicetree. Despite the UPDs remaining the same since Skylake, this is not the case for Alder Lake, Raptor Lake and Meteor Lake. Taking `starlabs/starbook` as an example, at the time of this commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE enabled. On Comet Lake, this results in the correct configuration, verified with the lspci command: ``` LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- ``` On Raptor Lake: ``` LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+ ``` Clock Power Management, ASPM and L1 Substates are also not configured for CPU root ports. Add helper functions to configure these correctly based on Kconfig, but retain the capability to override the specific levels from devicetree. Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81638 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-06mb/starlabs/starlite_adl: Add Alder Lake N StarLite Mk VSean Rhodes
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 22.04 * Manjaro 22 No known issues. https://starlabs.systems/pages/starlite-specification Change-Id: I8724e578c21353032b844b20b868348580ff561b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-06soc/intel/common/intelblocks/gpio.h: Allow specifying the pad ownershipYuchi Chen
Add pad_own_reg_0 to `struct pad_community`. Pad ownership indicates whether the GPIO is owned by host or Intel Management Engine. If owned by host, then host ownership indicates whether the GPIO is owned by ACPI or driver. Change-Id: I30a934fd00a7a42cb156341da1954e4e4b1231d8 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83315 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platformYuchi Chen
CPU and PCIe IDs are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0. Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83314 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoCChen, Yuchi
Change-Id: I333b137c1dc08a3c06bdd3f7a78ca44a5dd043cc Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83192 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-08-06mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flashKrystian Hebel
Depending on how firmware image was passed to QEMU, it may behave as: - ROM - memory mapped reads, writes are ignored (FW image mounted with '-bios'); - RAM - memory mapped reads and writes (FW image mounted with e.g. '-device loader'); - flash - memory mapped reads, write and erase possible through commands. Contrary to physical flash devices erase is not required before writing, but it also doesn't hurt. Flash may be split into read-only and read-write parts, like OVMF_CODE.fd and OVMF_VARS.fd. Combined size of system firmware must not exceed 8 MiB by default (FW image(s) mounted with '-drive if=pflash'). This function detects which of the above applies and fills region_device_ops accordingly. Tested by starting QEMU with firmware passed as '-drive if=pflash', '-drive if=pflash,readonly=on' and '-bios'. When started with firmware passed through '-device loader', coreboot complains about corrupted FMAP, but this is the same behavior as without this change: [ERROR] Invalid FMAP at 0x40000 [EMERG] Cannot locate primary CBFS Writable pflash support was added about 17 years ago, so it should be supported by all QEMU versions currently in use. Since QEMU 5.0.0 it is possible to change the limit of firmware size with `max-fw-size` machine configuration option, up to 16 MiB, as bigger sizes would overlap with default IO APIC memory range. Change-Id: I3ab9f22c6165064a769881d4be5eab13a0a2f519 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82555 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-08-06Kconfig: Reverse ARCH_SUPPORTS_CLANGArthur Heymans
Since most targets support clang it's easier to reverse the semantics of the Kconfig options. Change-Id: Ib28e7a4cb286b9f8b05be94dae3947179f43c746 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-08-06acpi/acpigen_ps2_keybd: Fix total keymap size calculationTyler Wang
This patch move keymap size calculation inside of has_alpha_num_punct_keys condition. When the condition is not met, it can prevent total keymaps size calculate incorrectly. BUG=none TEST=emerge coreboot pass Change-Id: I3dcf31d89924c1a8f2768e42065761b361e9ca41 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-06mb/google/brox/var/jubilant: Update WWAN and UsbCam SettingsRen Kuo
Update GPIOs for WWAN and USB Camera functions. BUG=b:341188351 TEST=Build and verify on jubilant Change-Id: I145aa994767ddc59be519b96017af71badf82734 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
2024-08-06mb/google/trulo: Register Firmware name for ISHVarun Upadhyay
Define ISH main firmware name so ISH shim loader can load firmware from file system. BUG=b:354607924 TEST=Boot trulo board, check that ISH is enabled and loaded lspci shows: 00:12.0 Serial controller: Intel Corporation Device 54fc Change-Id: Id60cb416a1cce5407bd483f0ce54f477584459b1 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83671 Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-05mb/asus/p8z77-m_pro/overridetree.cb: Correct PCIe devices configKeith Hui
Match PCIe root port allocation and associated comments to boardview, as follows: Z77 PCIe ports 1-4: PCIEX16_3 (x4) Z77 PCIe port 5: PCIEX1_1 Z77 PCIe port 6: RTL8111F LAN Z77 PCIe port 7: ASM1042 USB3 Z77 PCIe port 8: ASM1061 eSATA CPU PCIe lanes 1-8: PCIEX16_1 CPU PCIe lanes 9-16: Multiplexed via 4x ASM1480 to PCIEX16_1 lanes 9-16 and PCIEX16_2 lanes 1-8 (CPU PCIe lanes are not covered by overridetree.cb.) These are not hardware tested. Change-Id: I472e28add254ea945b401d1ddfd03f29f46d8fd2 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-05mb/supermicro/x10slm-f: Add board id for flashing via BMCNico Huber
The ID for X10SLM+F is 0811 as reported by Knogle on IRC. Change-Id: Ie58aad50e66efbc3113541884beea9668d886b5d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-05mb/google/dedede/var/awasuki: Disable SD cardWeimin Wu
Because Awasuki doesn't have SD card, disable related configurations. BUG=b:351968527 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki Change-Id: I1b0d2a9c2f9cdd4bca7c30cdc454ffa84b293146 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83706 Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-05soc/amd: add PSP SMI handler stubFelix Held
The PSP can send SMIs to the x86 side to have the SMI handler service requests from the PSP. This commit adds an empty PSP SMI handler; the actual implementation is added in later patches to keep the patches relatively small. This patch is a slightly modified version of parts of CB:65523. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I65989ff529d728cd9d2cd60b384295417bef77ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/83739 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-05mb/google/brox: Add model brox-ti-pdcBob Moragues
BRANCH=None BUG=b:348171026 TEST=Test on TI PDC device Cq-Depend: chromium:5691079 Cq-Depend: chromium:5691080 Cq-Depend: chrome-internal:7464767 Original-Change-Id: I6ffb8bdb2245a74b0d5270435d0ffc8a44e7c2a6 Original-Signed-off-by: Bob Moragues <moragues@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5691110 Original-Reviewed-by: YH Lin <yueherngl@chromium.org> Change-Id: Iac5b4cd4dcb1d274553f78e9d4295f8f9ad8a863 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-08-05nb/intel/*: Match ACPI with resource allocationArthur Heymans
Currently resource allocation starts top down from the default value 0xfe000000. This does not match what ACPI reports, so adapt CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT to reflect that. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I2ba0e96a7ab18d65b7fbbb38b1a979ea2ec6d1be Reviewed-on: https://review.coreboot.org/c/coreboot/+/80207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-04mb/google/brya/var/nova: Adjust Type-C port to USB 2.0 onlyPranava Y N
This patch introduces the following changes, - Remove TCSS XHCI (USB 3.x) devicetree settings - Update Over Current (OC) & USB 2.0 config - Update TCSS-XHCI capabilities BUG=b:348332200 TEST=Able to build google/nova and ensure lsusb can list genesys hub device. Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83707 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-04mb/google/brya/var/nova: Remove PMC MUX settingPranava Y N
This patch removes the PMC MUX related setting from devicetree as Nova doesn't include a MUX for it's USB-C port. BUG=b:348332200 TEST=Able to build google/nova Change-Id: I23a949ba9b598d7a86c6f8b08a2821651978e489 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-03mb/dell/optiplex_9020: Fix UB in package power calculationMate Kukri
Fix potential undefined behaviour in the `get_pkg_power()` function: - If `rapl_power_unit == 0`, `pkg_power_info / rapl_power_unit` is invalid - If `rapl_power_unit > 7`, the result of the shift doesn't fit into a `uint8_t` Signed-off-by: Mate Kukri <km@mkukri.xyz> Change-Id: I48ef59c4fbeb0a55675ac24da31e6e0b194cb58d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83736 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-08-03mb/google/rex: Skip UART0 config in FSPSubrata Banik
UART0 is already configured in coreboot, so this change sets SerialIo config for UART0 to PchSerialIoSkipInit to skip initialization in FSP. BUG=none TEST=Able to build and boot google/rex0. Able to see all debug prints over CPU uart. Change-Id: I37744f05083eb82ba8ca579b628b69aa976e3d1f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83750 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-03arch/arm64/armv8/mmu: Improve log formatYu-Ping Wu
Currently we use "%p" to print the address, which results in different string lengths, depending on the value of the address. To improve readability of the printed addresses in the log, change the format to "0x%013lx", so that the length of the printed addresses will be consistent. In addition, print the level of the translation table when setting up a new table. Example log: Backing address range [0x0000000000000:0x1000000000000) with new L0 ... Mapping address range [0x0000000000000:0x0000200000000) as ... Backing address range [0x0000000000000:0x0008000000000) with new L1 ... Mapping address range [0x0000000100000:0x0000000130000) as ... Backing address range [0x0000000000000:0x0000040000000) with new L2 Backing address range [0x0000000000000:0x0000000200000) with new L3 Mapping address range [0x0000000107000:0x0000000108000) as ... Mapping address range [0x0000000200000:0x0000000300000) as ... Backing address range [0x0000000000000:0x0000000200000) with new L3 ... BUG=none TEST=emerge-geralt coreboot BRANCH=none Change-Id: Ib29c201e1b096b9c7cd750d2541923616bc858ac Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-02soc/ti/am335x: Remove superfluous formatsArthur Heymans
These formats are already included in memlayout.ld. Change-Id: I89d226440308ce3fbe00382698dcd8c88863e694 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02soc/ti/am335x: Use Linker instead of compiler to linkArthur Heymans
Clang does not work that well as a linker for the header as it will default to other linkers which do not work well here. Instead just use the linker directly. Change-Id: Id6ba42b470349a4b138a65b2a037f16a65982ef7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02soc/intel/common/block/cse: Enforce CSE sync with pertinent GBB flagDinesh Gehlot
The patch enforces CSE sync when the GBB flag GBB_FLAG_FORCE_CSE_SYNC is enabled and the system is currently booting from the RO section. Additionally, it integrates forced CSE sync into eSOL decision-making. BUG=b:353053317 TEST=Verified forced CSE sync on rex0 with GBB 0x200000 Cq-Depend: chromium:5718196 Change-Id: I228bc8ebf58719776f6c39e0bfbb7ad53d9bfb7f Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-02security/vboot: Include new gbb flag to enforce CSE syncDinesh Gehlot
This patch adds a GBB flag to coreboot, which, when enabled, enforces CSE sync even if the current CSE version matches the version in CBFS. The CSME sync GBB and flag are designed to enhance autotest functionalities and are not intended or recommended for use in developing any other features. BUG=b:353053317 TEST=futility gbb --help Cq-Depend: chromium:5718196 Change-Id: I6352959e1e898a90b4c6e12a22f8d6513f90ded9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83685 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-02i2c/drivers/generic: Return ROTM in a packageSean Rhodes
The ROTM method should return a package: ``` Name (RBUF, Package (0x03) { "0 1 0", "1 0 0", "0 0 1" }) Return (RBUF) ``` Adjust the acpigen to do this. Change-Id: Id493f6955c1d0dc3449402262a8575091a828226 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-02soc/ti/am335x: Change and optimize memlayoutArthur Heymans
Clang builds (bootblock: 20800 bytes) are slightly larger than GCC builds (bootblock: 18688 bytes) so increase the size of both bootblock and romstage. The technical reference manual mentions no upper limit to the size of the bootblock in the TI header so increasing the bootblock size is allowed. To be able to link the clang bootblock increase it from 20K to 22K. Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02mb/google/brya/var/trulo: Remove mux references from typec portAmanda Huang
The Type-C kernel driver no longer programs the AP mux. So remove device references to the TCSS Mux control device from the Type-C port driver. BUG=b:351117685 TEST=USB-C drive can be detected after system warm or cold reboot. Change-Id: I2fd6e8fcebd194da03ba3f264ee89037ca11769a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83746 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-02mb/google/brox/var/greenbayupoc: update ALC236 verb tableWu Garen
The previous uploaded verb table is not fully applied due to configuration error. Uploaded the verb table provided by Realtek which can be found in b:336967284. BUG=b:326412504, b:336967284 TEST=deploy and check volume Change-Id: Ib9a8248c4a437fd204f40918d801a4a010a5c4df Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Terry Cheong <htcheong@chromium.org>
2024-08-02mb/google/brox/var/brox: Enable Class-D calibrationTerry Cheong
DC offset of class-D amplifier is 7mV in Brox which is larger than the expected 3mV. Add a section in the verb table to enable class-D calibration based on the updated verb table provided by Realtek in b:342506575 comment#6. This improves the offset to be less than 1mV. BUG=b:342506575 BRANCH=main TEST=Verify DC offset of speaker amplier output is less than 1mV with a multimeter when \ playing -100dB sine waves. Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85 Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-01mb/google/brox: Create jubilant variantRen Kuo
Create the jubilant variant of the brox reference board by copying the template files to a new directory named for the variant. BUG=b:348543712 TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_JUBILANT. Change-Id: Ic54437697058f8bce2167093bd88c0880d1b7cac Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83212 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2024-08-01soc/amd/common/smi_util: add PSP SMI helper functionsFelix Held
The PSP can send SMIs to the x86 side of the system. Add helper functions to configure and to reset the PSP SMI generation. Since Stoneyridge also selects SOC_AMD_COMMON_BLOCK_SMI, add the SMITRIG0_PSP define and rename SMITYPE_FCH_FAKE0 to SMITYPE_PSP in its SoC-specific smi.h to bring it in line with the newer SoCs. This patch is split out from CB:65523. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I525a447c9a75fdb95b9750e85a02896056315edf Reviewed-on: https://review.coreboot.org/c/coreboot/+/83702 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01mb/starlabs/starbook/rpl: Merge and alphabetise FSP UPDsSean Rhodes
Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-01mb/starlabs/*: Add the subsystem ids for HDASean Rhodes
The Windows drivers require the subsystem ID to match on the PCI device, so set these to allow the driver to install. Change-Id: I01b36554d5322018efc72734a8e749cc06263577 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83621 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01mb/emulation/qemu-q35/memmap: Remove redefine macrosElyes Haouas
SMRAMC, C_BASE_SEG, G_SMRAME, D_LCK, D_CLS, D_OPEN, ESMRAMC, T_EN, TSEG_SZ_MASK and H_SMRAME are already defined in included "q35.h" file. Change-Id: Ic3c01cca14749f77adecc327a78ac011ba3f4c0b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83429 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01soc/intel/xeon_sp: Add acpigen_write_pci_root_portLu, Pen-ChunX
acpigen_write_pci_root_port writes SSDT device objects for PCIe root port, _ADR and _BBN are provided. SSDT objects for direct subordinate devices will also be created (if detected), _ADR and _SUN are provided. TEST=Build and boot on intel/archercity CRB Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0 Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-08-01mb/google/nissa: Create teliks variantzengqinghong
Create the teliks variant of the nissa reference board by copying the anraggar files to a new directory named for the variant. BUG=b:352263941 BRANCH=None TEST=1. util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TELIKS 2. Run part_id_gen tool without any errors Change-Id: I744f4d7c2d35544d3a8a8f76e24bad3298442768 Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83408 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-01acpi/acpigen_ps2_keybd: Move KEY_DELETE to rest_of_keymapsTyler Wang
This patch supports keyboards that have delete key but without numpad. To prevent KEY_DELETE be defined twice, move it from numeric_keypad_keymaps to rest_of_keymaps. BUG=b:345231373 TEST=Build and test on Riven/Craaskino, delete key function works Change-Id: Ib922a2b52fa7152ba3d9deb44e2c8200b2a3802c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83684 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-01mb/google/brya/var/orisa: Remove mux references from typec portAmanda Huang
The Type-C kernel driver no longer programs the AP mux. So remove device references to the TCSS Mux control device from the Type-C port driver. BUG=b:351117685 TEST=USB-C drive can be detected after system warm or cold reboot. Change-Id: I4a24fb69ebec87f65b679cde0e4a1a8827cd365d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83722 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-31soc/amd/common/psp: move buffer sizes to common headerFelix Held
Since the P2C_BUFFER_MAXSIZE value will be needed in another compilation unit, move the define to the common psp_def.h. P2C_BUFFER_MAXSIZE is moved there too for consistency reasons. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d4d93760c90ad6e0ecadf70600b1d697a02fa82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83701 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31soc/amd/common/psp_smm: introduce and use send_psp_command_smmFelix Held
When sending mailbox commands to the PSP from SMM, the SMM flag needs to be set right before sending the mailbox command and cleared right after the command is sent. In order to not have this code duplicated, factor it out into a function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3628463dece9d11703d5a068fe7c604108b69c1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/83700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31soc/amd/common/psp_smm: add comments to psp_notify_smmFelix Held
The reasoning behind this and the positive side effects of this aren't too clear from the code, so point those out in a comment. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4f4121031fc1ef600cdf5551f61f1ef4e03b56a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31soc/amd/common/psp_smm: add/improve comments to buffers and flagsFelix Held
Since it's not exactly obvious what 'c2p_buffer', 'p2c_buffer' and 'smm_flag' are used for, add comments to those. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ec092a92fe9f0686ffb7103e441802fc05381f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31device/path: rename domain path struct element to 'domain_id'Felix Held
Rename the 'domain' element of the 'domain_path' struct to 'domain_id' to clarify that this element is the domain ID. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Martin Roth <gaumless@gmail.com> Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83677 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-07-31device: introduce and use dev_get_domain_idFelix Held
To avoid having constructs like 'dev->path.domain.domain' in the SoC code, create the 'dev_get_domain_id' helper function that returns the domain ID of either that device if it's a domain device or the corresponding domain device's domain ID, and use it in the code. If this function is called with a device other than PCI or domain type, it won't have a domain number. In order to not need to call 'die', 'dev_get_domain_id' will print an error and return 0 which is a valid domain number. In that case, the calling code should be fixed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3d79f19846cea49609f848a4c42747ac1052c288 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83644 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31soc/intel/adl: Update DCACHE_BSP_STACK_SIZEKarthikeyan Ramasubramanian
During the stages which use Cache-as-RAM (CAR), coreboot needs more than 1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly. BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-31mb/google/trulo: Keep ISH default enableSubrata Banik
This patch drops fw_config probing for ISH because ISH IP should remains on by default for all Trulo variants. Additionally, removed the redundant ISH entries from variant override devicetree. BUG=b:354607924 TEST=Able to verify ISH PCI Device is available while booting eMMC sku. ``` lspci 00:00.0 Host bridge: Intel Corporation Device 461c ... 00:12.0 Serial controller: Intel Corporation Device 54fc ... 00:1a.0 SD Host controller: Intel Corporation Device 54c4 ``` Also, able to enter S0ix with this patch. ``` > suspend_stress_test -c 1 --ignore_s0ix_substates At AP console: s0ix errors: 0 s0ix substate errors: 0 s0ix pc10 errors: 0 At EC console: power state 5 = S0ix, in 0x38d87 ``` Change-Id: Ic1e415ec848ac91a9bbf21b26597f4e6b5f7a1f5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83695 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31mb/google/brya/var/xol: Using baseboard's PchPmSlpAMinAssert settingsRaymond Chung
Reduce PchPmSlpAMinAssert (pch_slp_a_min_assertion_width) to minimum time (98ms) from 2sec. BUG=b:349595391 BRANCH=firmware-brya-14505.B Test=Verified on xol Change-Id: Ia4b7b7ab5dc9afeb3505dfd2b42d0d397aed7a5c Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83683 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-30mb/google/brya/var/orisa: Remove redundant defaults from overridetreeRishika Raj
Streamline variant-level overrides by removing redundant entries that already exist in either the SoC-level or the platform-level configurations. BUG=None TEST=emerge-nissa coreboot Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-29i2c/drivers/generic: Add support for including a CDMSean Rhodes
Chip Direct Mapping is exclusive to Windows; it allows specifying the position where a chip is mounted. There are 8 positions and a _CDM method should return 0xabcd0X, where X is the position. Tested by booting Windows 11 on the StarLite Mk V, rotating the device and checking the orientation is correct, where previously, it was inverted. Change-Id: If70c25288d835df7064b4051c43abeb2d6531f3b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81409 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-29soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK commentYu-Ping Wu
The comment for the BOOTBLOCK region should be written right above the BOOTBLOCK declaration. BUG=b:317009620 TEST=none BRANCH=none Change-Id: I7afdf74844a9d97169b4e4a23c3c9c6060e886d9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83649 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-27Revert "soc/intel/adl: Guard TWL SoC missing UPDs for build integrity"Subrata Banik
This reverts commit 59ee65d271c7c617bcc240019231da4f0bd04db6. Reason for revert: - Usb4CmMode & CnviWifiCore Upds are available starting with TWL FSP version v5222.01. Therefore, no special handling is required. BUG=b:330654700 TEST=Able to build google/tivviks. Change-Id: I3c74ec5b9924e88a26984fe8d3275ba80edb14ab Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>