diff options
| author | Yuchi Chen <yuchi.chen@intel.com> | 2024-06-25 10:40:10 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-10 01:06:26 +0000 |
| commit | b60cfb89e99bd2c6a7136b99385eb1fbe5b8e85d (patch) | |
| tree | ff13965465e2226908ffb51c56ce5bb0010e7ffa /src | |
| parent | 5eebeaf31cbe30b11275aa5d80a341274f680cfc (diff) | |
soc/intel/common/block/gpio/gpio.c: Improve GPIO debug infos
1. print host software ownership, SMI enable and NMI enable registers
after configuring
2. read and print GPIO configuration dword registers after writing
3. use %zu to print size_t values according to CI reporting.
Change-Id: I8820956f6db91c7bcc26b46a4361da3dfa8f77b5
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83316
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/gpio/gpio.c | 37 |
1 files changed, 28 insertions, 9 deletions
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 63d7a5e8d2..d49742d1b5 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -167,6 +167,12 @@ static void gpio_configure_owner(const struct pad_config *cfg, hostsw_own &= ~gpio_bitmask_within_group(comm, pin); pcr_write32(comm->port, hostsw_own_offset, hostsw_own); + + if (CONFIG(DEBUG_GPIO)) { + printk(BIOS_DEBUG, "HOST_OWN[0x%02x, %02zu]: Reg: 0x%x, Value = 0x%08x\n", + comm->port, relative_pad_in_comm(comm, cfg->pad), hostsw_own_offset, + pcr_read32(comm->port, hostsw_own_offset)); + } } static void gpi_enable_gpe(const struct pad_config *cfg, @@ -187,7 +193,7 @@ static void gpi_enable_gpe(const struct pad_config *cfg, pcr_or32(comm->port, en_reg, en_value); if (CONFIG(DEBUG_GPIO)) { - printk(BIOS_DEBUG, "GPE_EN[0x%02x, %02zd]: Reg: 0x%x, Value = 0x%x\n", + printk(BIOS_DEBUG, "GPE_EN[0x%02x, %02zu]: Reg: 0x%x, Value = 0x%08x\n", comm->port, relative_pad_in_comm(comm, cfg->pad), en_reg, pcr_read32(comm->port, en_reg)); } @@ -212,6 +218,12 @@ static void gpi_enable_smi(const struct pad_config *cfg, /* Set enable bits */ pcr_or32(comm->port, en_reg, en_value); + + if (CONFIG(DEBUG_GPIO)) { + printk(BIOS_DEBUG, "SMI_EN[0x%02x, %02zu]: Reg: 0x%x, Value = 0x%08x\n", + comm->port, relative_pad_in_comm(comm, cfg->pad), en_reg, + pcr_read32(comm->port, en_reg)); + } } static void gpi_enable_nmi(const struct pad_config *cfg, @@ -237,6 +249,12 @@ static void gpi_enable_nmi(const struct pad_config *cfg, /* Set enable bits */ pcr_or32(comm->port, en_reg, en_value); + + if (CONFIG(DEBUG_GPIO)) { + printk(BIOS_DEBUG, "NMI_EN[0x%02x, %02zu]: Reg: 0x%x, Value = 0x%08x\n", + comm->port, relative_pad_in_comm(comm, cfg->pad), en_reg, + pcr_read32(comm->port, en_reg)); + } } /* 120 GSIs is the default for IOxAPIC */ @@ -368,16 +386,17 @@ static void gpio_configure_pad(const struct pad_config *cfg) /* Patch GPIO settings for SoC specifically */ soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf); - if (CONFIG(DEBUG_GPIO)) - printk(BIOS_DEBUG, - "gpio_padcfg [0x%02x, %02d] DW%d [0x%08x : 0x%08x" - " : 0x%08x]\n", - comm->port, pin, i, - pad_conf,/* old value */ - cfg->pad_config[i],/* value passed from gpio table */ - soc_pad_conf);/*new value*/ pcr_write32(comm->port, PAD_CFG_OFFSET(config_offset, i), soc_pad_conf); + + if (CONFIG(DEBUG_GPIO)) + printk(BIOS_DEBUG, + "gpio_padcfg [0x%02x, %02d] DW%d [0x%08x : 0x%08x : 0x%08x : 0x%08x]\n", + comm->port, pin, i, + pad_conf, /* old value */ + cfg->pad_config[i], /* value passed from gpio table */ + soc_pad_conf, /* new value */ + pcr_read32(comm->port, PAD_CFG_OFFSET(config_offset, i))); /* updated value */ } gpio_configure_itss(cfg, comm->port, config_offset); |