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2021-08-24soc/intel/tigerlake: Add PCH-H chipset devicetreeJeremy Soller
Based on the base TGL devicetree, add one specific to TGL-H that adds the additional supported devices. Introduces a new Kconfig for selecting the PCH support. Reference: - Intel doc 615985 Change-Id: Icc130461edcecc4a3e1f6544ccb905608881d2f7 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add TGL-H power limitsJeremy Soller
Convert the power limit defines to an enum and add TGL-H entries. Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel: Add TGL-H CPUIDJeremy Soller
Change-Id: I5a76bcbd6661648a9284d683eb360ec956a9f9a6 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56942 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24Revert "soc/intel/broadwell/pch: Replace ACPI device NVS"Furquan Shaikh
This reverts commit 68d8357dab55660058ad1ab8dca34fd03e0adbb5. Reason for revert: Device NVS is expected by mainboard samus in payload depthcharge: https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icb5fa6da3412a51aae56c3658163e5b98d57bab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-24Revert "soc/intel/broadwell/pch: Drop device NVS remainders"Furquan Shaikh
This reverts commit 34bd6ba97917b0bc54bb1f1e106a56b5c03e19ac. Reason for revert: Device NVS is expected by mainboard samus in payload depthcharge: https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60 Not reverted: * ACPI_HAS_DEVICE_NVS does not exist anymore in ToT and hence it's selection in broadwell is not required. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic31d7ae62c5df72708b724160e96e10b46002eb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-23mb/google/hatch: Create moonbuggy variantRehan Ghori
Create the moonbuggy variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=191356135 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_MOONBUGGY Signed-off-by: Rehan Ghori <rehang@google.com> Change-Id: Iaf545dcd5ff537afdf029f510553d16a1239763e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-23mb/google/dedede: add gooey variantstanley.wu
gooey is the same design as boten, and differs only in replacing Cr50 with discrete TPM. BUG=b:193366710, 197247706 TEST=FW_NAME=gooey emerge-keeby coreboot Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I2a54f872a7d5c0bee76a9e6e309613d9357b380b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-23include/bcd: move bcd code to commonlib/bsd/includeRicardo Quesada
Move bcd2bin() / bin2bcd() functions to commonlib/bsd/include/ Also, the license is changed from GPL to BSD. This is because it is needed from "utils" (see CL in the chain). For reference bin2bcd() & bcd2bin() are very simple functions. There are already BSD implementations, like these ones (just to name a few): https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/include/lib/math.h#67 http://web.mit.edu/freebsd/head/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c BUG=b:172210863 TEST=make (everything compiled Ok). Change-Id: If2eba82da35838799bcbcf38303de6bd53f7eb72 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56904 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-23mb/google/guybrush: Enable PCIe L1 SubstatesMatt Papageorge
This change enables L1.1 and L1.2 on all real Guybrush PCIe devices. BUG=b:188123142 TEST=Boot to ChromeOS and verify L1SS are functional by dumping the settings with "lspci -vv". Leave system on for 20 minutes and no hang. Also perform 20 reboots and suspend operations Cq-Depend: chrome-internal:4012927 Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-23mb/google/dedede/var/bugzzy: Configure GPIO settingsSeunghwan Kim
Override GPIO pad configurations based on the latest bugzzy schematics. BUG=b:192521391 BRANCH=None TEST=Built test coreboot image and boot on bugzzy board Change-Id: I7c3580e7eb34efed0441ead243343d2d7875d50f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-23soc/mediatek/mt8195: Update clock square settingChun-Jie Chen
To reduce suspend power consumption, 1. Disable unused CLKSQ2. 2. Set CLKSQ_EN to sleep control for SPM 26M sleep control. No bus clock when enter 26m sleep control, and only control clock square by side band. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: Ia9a1735d6f508ce35b9af2d67831a3474255198b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57043 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-23soc/mediatek/mt8195: add HDMI low power settingRex-BC Chen
Add HDMI low power setting to reduce power consumption. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ica91645789e5de3401131e7050d2b1ee06c535dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/57042 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-22mb/google/brya/var/brya0: Align comments in overridetreePaul Menzel
Change-Id: Id3eb18cae2dd9a7b148bc9f3dcaf387f35dbd2fb Fixes: 312fb716 ("mb/google/brya: Add ALC1019_NAU88L25B support") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-22AGESA f15tn: Fix building IDS tracing supportAngel Pons
Also add a config file to ensure the code gets build-tested. Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53986 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-22AGESA f15tn: Hook up IDS options to KconfigAngel Pons
IDS (Integrated Debug Services) options are meant to be enabled when one wants to debug AGESA. Since they are compile-time options, using Kconfig is the logical choice. Currently, none of the options builds. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and Asus A88XM-E does not change. Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-08-22AGESA f15tn: Factor out common OptionsIds.hAngel Pons
Subsequent commits will add Kconfig options to configure IDS. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: I861762280b274566ce14969a30e2e0c98e120a69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-08-22AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED`Angel Pons
The `ASSERT` macro is already defined in `src/include/assert.h`, and AGESA's definition is never used. On Asus A88XM-E, toggling the value of the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary when using reproducible builds. Attempting to use AGESA's definition of the `ASSERT` macro results in build errors: In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info': src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value] #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE)); Given that coreboot's definition of `ASSERT` is more useful, drop AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro. Also remove the `IdsAssert` function, as it is no longer used anywhere. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-08-22AGESA f15tn boards: Sync IDS option valuesAngel Pons
In preparation to replace OptionsIds.h with Kconfig options, use the same settings on all AGESA f15tn boards. The only difference this makes is that the `IDS_LATE_RUN_AP_TASK` macro no longer expands to nothing. It is expected that the impact this difference makes is minimal. Note that the `IDSOPT_TRACING_ENABLED` option currently fails to build. Tested on asus/f2a85-m, still boots. Change-Id: Iedd4d1f255650012f3efd9a27718e18c1c904dc1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53982 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-20qualcomm/sc7180: Switch to common MIPI panel libraryJulius Werner
This patch changes the sc7180 boards to use the new common MIPI panel framework, which allows more flexible initialization command packing and sharing panel definitions between boards. (I'm taking the lane count control back out again for now, since it seems we only ever want 4 for now anyway, and if we ever have a need for a different lane count it's not clear whether that should be a property of the board or the panel or both. Better to leave that decision until we have a real use case.) Also, the code was not written to deal with DCS commands that were not a length divisible by 4 (it would read over the end of the command buffer). The corresponding kernel driver seems to pad the command with 0xff instead, let's do the same here. (Also increase the maximum allowed command length to 256 bytes, as per Qualcomm's recommendation.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-20mb/google/brya: Add ALC1019_NAU88L25B supportEric Lai
Add ALC1019_NAU88L25B DB support. BUG=b:195891240 TEST=audio is functional when playing youtube. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9209c4cab00fc03b2a6107b5c32804786cd2e242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-20soc/intel/adl: Update power limits for ADL-M SKUSumeet Pawnikar
Update SKU specific power limits for ADL-M as per document 643775. BUG=None BRANCH=None Change-Id: I40b9b3a508c549d940e1c2c9e8b4079695b694e6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-20soc/intel/adl: Update PCI ID for ADL-M SKUSumeet Pawnikar
Update PCI ID for ADL-M as per document 643775. BUG=None BRANCH=None Change-Id: Ia2c5ce270bc421d8a41cc4bc6ce0b51987d2aaec Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-20mb/google/zork: only enable RTD2141 when presentPeter Marheine
An MST hub is only present on some devices that are configured with a particular daughterboard indicated by EC fw_config, so add a fw_config probe that matches the USB daughterboard ID from CBI to only enable it on devices where present, using variant-specific daughterboard IDs. BUG=b:185862297 TEST=RTD2141 remains in ACPI tables on a berknip with Dali DB, and is not present on the same system if probe is changed to enable it for picasso DB. BRANCH=zork Change-Id: I4ada9b492ab221fa98350bf2faf27a23342f3a55 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2021-08-20soc/amd/common: Skip psp_verstage on S0i3 resumeMartin Roth
PSP_Verstage will take almost the entire time to run that is allotted to S0i3 resume. Since coreboot isn't running, the PSP needs to handle any security requirements. The long- term plan is that the PSP won't even load psp_verstage on S0i3 resume, but when it is loaded, this makes sure we exit immediately BUG=b:177064859 TEST=Verify that PSP_verstage doesn't run on S0i3 resume Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-08-20soc/intel/cannonlake: Unbreak some short linesNico Huber
Change-Id: I8c8b49d519b7c6a3d1e4946818b2fc5a1dd1d3e1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56663 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19Revert "src/soc/intel/cannonlake: Update C-state latency control limits"Nico Huber
This reverts commit 66dbb0c5d67279722fcbcb547d9c6b61e606d50e. The numbers were meant for Cannon Lake, but the code was also meant to be used for all other platforms using the Cannon Point PCH. Now Cannon Lake support is even dropped, so we can cleanly revert to the recommended values for the other platforms. Change-Id: Iea56c6a29ca4b34c9852393fed2e3be4de128ec6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56662 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19acpi: Fill fadt->century based on KconfigNico Huber
Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-19soc/intel/denverton_ns: Sanity check MMCONF_BASE_ADDRESSKyösti Mälkki
According to received feedback, FSP-T enables MMCONF at address 0xe0000000 with 256 busses. Sanity-check that Kconfig matches that. Add MMCONF_BUS_NUMBER such that MCFG in ACPI will be correct. Change-Id: I01309638a9f4ada71e5e3789db34892ed4abfa3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-19mb/intel/adlrvp: Drop INTEL_CAR_NEM Kconfig select on ADL-P RVPSubrata Banik
This patch enables eNEM flow for Alder Lake SoC hence drop INTEL_CAR_NEM Kconfig from ADL-P RVP. ALDERLAKE_CAR_ENHANCED_NEM Kconfig will select all relevant Kconfig required to enable eNEM for Alder Lake. Additionally, select INTEL_CAR_NEM Kconfig for ADL-M RVPs from Kconfig.name. BUG=b:168820083 TEST=Able to build and boot ADL-P RVP using eNEM mode. Change-Id: I08561c8f50bbc4afe2bcdff4cc50e74d8fa2f68e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48345 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19soc/intel/alderlake: Move INTEL_CAR_NEM selection from SoC to mainboardSubrata Banik
This patch decouples the selection of eNEM feature enablement from SoC to ensure the ADLRVP does the validation first prior enabling this feature on OEM/ODM reference designs. BUG=b:168820083 TEST=No changing is being observed in .config with and without this CL. Change-Id: I709185159d9869501b1d8e8d00f6d25ec77838bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19mb/google/dedede/var/driblee: Generate RAM ID and SPD fileFrank Wu
Add the support RAM parts for Driblee. Here is the ram part number list: 1. Hynix H9HCNNNBKMMLXR-NEE 2. Micron MT53E512M32D2NP-046 WT:F 3. Samsung K4U6E3S4AA-MGCR 4. Micron MT53E512M32D1NP-046 WT:B BUG=b:195619346 BRANCH=keeby TEST=emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I683acb91ec13cbd772e732d7f81152ceb3cefc1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56924 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19mb/google/brya: set tcc_offset value to 10Sumeet Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUGb=b:195706434 BRANCH=None TEST=Built for brya platform and verified the MSR value Change-Id: I22573e8ca935d99a16b0876768df169db4e61c4d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57000 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19soc/intel/alderlake: set default PL4 values for different SKUsSumeet Pawnikar
Set default PL4 values for various Alder Lake CPU SKUs as per bug#191906315 comment#10. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board. Change-Id: I53791badbec3c165d56f20ce0656dc15d63bab37 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56917 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19soc/intel/common: Add TGL-H PCI IDsJeremy Soller
Add TGL-H PCI IDs from the Processor and PCH EDS docs. Reference: - Intel doc 615985 - Intel doc 575683 Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19device_util.c: Replace `memcpy()` with `strcpy()`Angel Pons
Use `strcpy()` instead of `memcpy()` to copy string literals. Change-Id: I8ebf591e3348d992739ed7cc2e4015aa650f115a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-19mb/google/brya/variants/primus: Fix GL9755S power sequenceMalik_Hsu
- Enable EN_PP3300_SD - Configure SD_PE_RST_L correctly BUG=b:195625340 TEST=Able to boot with SD card Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I33c17e88cabdc9b13634fc8f341aa6a09b7bfde5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19mb/google/brya: Enable ADL_ENABLE_USB4_PCIE_RESOURCES for primusMalik_Hsu
primus supports USB4 and so needs to reserve bus numbers and prefmem and mem resources for potential hotplugs of devices. BUG=b:193377625 BRANCH=None TEST=build pass Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I1d1f8cc3460c1b89dade4f01690c77efcd799098 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19google/trogdor: Read SKU ID as binary-first base3 strappingJulius Werner
We're running out of SKU IDs in the base2 system, so convert it to binary-first base3. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia7f749fa042d3eac76bfe1e74531905c6e279ad2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57004 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-18soc/amd/cezanne: Disable Co-op multitaskingRaul E Rangel
There are gremlins in the system. thread_coop_enable has an assert. This is currently problematic for two reasons. assert(current->can_yield <= 0); When doing smm_do_relocate we are entering a deadlock. The root cause hasn't been quite found yet, but it's related to co-op multi-threading. For some reason the assert in thread_coop_enable is firing when releasing the console_lock spin lock. I'm assuming cpu_info hasn't been initialized yet. The assert tries to perform a printk, but since the console_lock is still held we end up in a dead lock. This dead lock will generally not happen after a warm reset. Again I'm assuming because the cpu_info struct has some valid values at this point. For now disable multi-tasking until we fix the cpu_info initialization. BUG=b:194391185 TEST=Boot guybrush to OS Co-developed-by: nikolai.vyssotski@amd.corp-partner.google.com Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia3143f538a31b5aaaea104aa1d8bcf44e6dcb528 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57005 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-18soc/amd/common/upep.asl: Correct device list formatPratik Vishwakarma
Use correct format for constraint list as expected by kernel driver. With this change, kernel is able to correctly list dummy device in constraint list. BUG=b:194687976 TEST=Build and boot to OS in Guybrush. Change-Id: I7af1941ffd21cd5864c7285f44cb2d063d2f225f Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57012 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-18mb/google/dedede/var/sasukette: Add fw_config probe for ALC5682I-VD & VSZhi Li
Update the `_HID` value of device in SSDT depending on the fw_config. According to value of AUDIO_CODEC_SOURCE field in fw_config(SSFC) which stored in CBI: AUDIO_CODEC_ALC5682: _HID = "10EC5682" /* ALC5682I-VD */ AUDIO_CODEC_ALC5682I_VS: _HID = "RTL5682" /* ALC5682I-VS */ BUG=b:193623380 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Ic8840454e4934162ea59c742634a56f70b153238 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2021-08-18mb/google/guybrush: Enable STT in device treeJason Glenesk
Enable Skin Temperature Tracking with initial configuration settings. BUG=b:190732595 TEST=Confirm that AGT tool can successfully complete data collection Change-Id: I37b5da1b56586ef75ad17f6766cd00ddac87aa5a Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55434 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-18device: Move MIPI panel library from mainboard/google/kukui into commonJulius Werner
All boards that are trying to use MIPI panels eventually run into the problem that they need to store physical parameters and a list of DCS initialization commands for each panel, and these commands can be very different (e.g. a large amount of very short commands, a few very large commands, etc.). Finding a data format to fit all these different cases efficiently into the same structures keeps being a challenge, and the Kukui mainboard already once put a lot of effort into designing a clean, flexible and efficient solution for this. This patch moves that framework into a common src/device/mipi/ library where it can be used by other boards as well. (Also, this will hopefully allow us to save some duplicated work when using the same panel on different boards at some point.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I877f2b0c7ab984412b288e2ed27f37cd93c70863 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-08-17mb/google/octopus/var/phaser: Change IRQ trigger method to levelJoey Peng
The change from Synaptics S7817 to Elan 3915N and pin distribution of touch IC is the same. The original Elan section was copied from reference design and was never used before. According to vendor spec definition IRQ trigger method needs to change to level. BUG=b:190574692 TEST=Build coreboot and check that device works Change-Id: I44ee779242779c78ceafdddd34dca2571e714dd3 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56380 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-17mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:BWisley Chen
Add SPD support to lantis for MT53E512M32D1NP-046 WT:B BUG=None BRANCH=firmware-dedede-13606.B TEST=FW_NAME=lantis emerge-dedede coreboot chromeos-bootimage Change-Id: I22c50a55dd3b8bbda64ba1b607c8b22cc6592f98 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-17mb/google/dedede/var/cappy2: Fix the DUT with cirrus codec PLT failSunwei Li
irq(ACPI_IRQ_LEVEL_LOW) -> ACPI_DESCRIPTOR_INTERRUPT -> IO-APIC, will assert interrupt frequently; irq_gpio(ACPI_GPIO_IRQ_EDGE_BOTH) -> ACPI_DESCRIPTOR_GPIO -> INT34C8; will not assert interrupt frequently; Because IRQ configuration can't be setted to both EDGE trigger. BUG=b:195635555 BRANCH=dedede TEST=Cirrus audio codec PLT pass Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I65bca519f75af84848284f039b6ad67cb1887823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56973 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16trogdor: Fix "TPM interrupt" lb_gpio to be ACTIVE_HIGHJulius Werner
"Latched" GPIOs like this one are a virtual representation of the pending interrupt flag for the edge-triggered pin and not a direct representation of line state, so they should always be marked ACTIVE_HIGH or depthcharge will incorrectly negate them. This has always been wrong and meant that depthcharge doesn't correctly wait for Cr50 flow control responses on these platforms. Thankfully it doesn't seem like we've seen any practical issues from this, but it's still very wrong. BRANCH=trogdor BUG=none TEST=Booted CoachZ (no visible difference) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie1586b0e10b64df0712e28552411c4d540a7e457 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2021-08-16mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD devicePatrick Huang
Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources. In guybrush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device. BUG=b:186384256 BRANCH=none TEST=Verify the config setting can update to the GPPCLKCONTROL registers. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cbMAULIK V VAGHELA
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56954 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/intel/adlrvp_m: Enable CR50 TPM support over SPIThejaswani Puta thejaswani.putta@intel.com
Add Kconfig options and enable TPM device in devicetree BUG=None TEST=Booted the image and checked the successful TPM communication in verstage,romstage & ramstage from coreboot logs. Signed-off-by: Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com> Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-16mb/google/dedede: Create driblee variantFrank Wu
Create the driblee variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:191732473 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DRIBLEE Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1ad9a4e0cf7999337b55d62d5cc94e4f6c2e98f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-16mb/google/dedede: Create corori variantIan Feng
Create the corori variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:194356176 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CORORI Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I8380d5aab61c99d545625789ff1251ec1caa84a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56796 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/google/poppy/variants/atlas: stop setting touchscreen probed=1Matthew Blecker
All Atlas devices have the touchscreen controller, so probing for its presence is unnecessary. Removing the probe requirement allows the touchscreen ACPI device in Linux to re-enumerate when rebinding its I2C adapter device. Without this change, after rebinding the touchscreen's I2C adapter device using sysfs the touchscreen ACPI and HID devices are absent, and the touchscreen is unresponsive. With this change, the touchscreen ACPI and HID devices are re-created after rebinding its I2C adapter device, and the touchscreen becomes responsive again. BUG=b:177350937 TEST=Tested on 2 Atlas DUTs running Chrome OS R94 top-of-tree builds with Linux 4.4 and 5.4. Built new AP FW from Atlas Chrome OS firmware branch with this change applied. Tested shipping RO + new RW, and new RO + new RW. Test sequence: 1) Boot DUT, verify basic touchscreen functionality. 2) $ cd /sys/bus/platform/drivers/i2c_designware 3) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}} lrwxrwxrwx. 1 root root 0 Aug 12 01:07 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6 drwxr-xr-x. 4 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00 drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002 drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw/hidraw1 4) $ echo i2c_designware.0 > unbind 5) Verify touchscreen is unresponsive (as expected after unbind). 6) $ ls -ld i2c_designware.0 ls: cannot access 'i2c_designware.0': No such file or directory 7) $ echo i2c_designware.0 > bind *** Without this change: *** 8) Touchscreen remains unresponsive. 9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00}} ls: cannot access 'i2c_designware.0/i2c-6/i2c-ACPI0C50:00': No such file or directory lrwxrwxrwx. 1 root root 0 Aug 12 01:18 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 4 root root 0 Aug 12 01:18 i2c_designware.0/i2c-6 *** With this change: *** 8) Touchscreen is functional again. 9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}} lrwxrwxrwx. 1 root root 0 Aug 12 01:09 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6 drwxr-xr-x. 4 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00 drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003 drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw/hidraw1 Signed-off-by: Matthew Blecker <matthewb@chromium.org> Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db Reviewed-on: https://review.coreboot.org/c/coreboot/+/56928 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/google/brya/var/redrix: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I61377e6cdd3af9d6d80b9e1e68191b39f43358ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/56969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: Add I2C parameterEric Lai
Add I2C parameters to make sure each bus speed is around 390kHz. BUG=b:188793264 TEST=Measure by scope. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib47228b8684c44f6acfec9e9e4b6e7b18ba6f6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya/variants/kano: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for kano BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4d6099fa8d17bebf798ddf236a68886087e2a95e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: Configure EN_FCAM_PWR to highVarshit B Pandya
Recent change "7a8c68a: mb/google/brya: Configure H21 as GPO and A17 as low" turned EN_FCAM_PWR low since EN_FCAM_PWR is turned ON and OFF by IPU driver while MIPI UFC probing. However USB UFC also requires 3.3V which is enabled by A17. This caused USB UFC enumeration to fail BUG=b:196014678 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I88c204ec07b1f7511f0d88074e336cfc9116a7d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56882 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/google/brya/primus: Fix G2 touchscreen reset GPIO polarityCasper Chang
modify reset_gpio as active low to meet touchscreen spec BUG=b:195490284 BRANCH=none TEST=build coreboot and touchscreen works Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I7ce1b3025db8abebf5693b34da846a7e969246fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: allow MKBP devices and disable TBMC deviceBoris Mittelberg
Enable MKBP (Matrix Keyboard Protocol) interface for all Brya family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:170966461 TEST=manual test on Brya P1: Volume Up/Down buttons Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ic9c707f57871f388c363e01c9ab78a3b358ce728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/guybrush: Update GPIOs for fingerprint MCUMartin Roth
Add mainboard finalize and shutdown call to match zork. Deassert EN_PWR_FP in bootblock, power up correctly in finalize. | Phase | SOC_FP_RST_L | EN_PWR_FP | S3 resume | |-----------|--------------|-----------|----------------------| | Bootblock | **Low** | **Low** | Maintain High / High | | Romstage | Low | Low | Maintain High / High | | Ramstage | Low | **High** | Maintain High / High | | Finalize | **High** | High | | | Shutdown | **Low** | **Low** | | BUG=b:191694480 TEST=Build, verify GPIO configuration. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-16soc/intel/alderlake: Create eNEM Kconfig for Alder LakeSubrata Banik
Alder Lake SoC specific Kconfig that internally selects all eNEM related Kconfig. CONFIG_ALDERLAKE_CAR_ENHANCED_NEM will get autoselected if platform doesn't have INTEL_CAR_NEM Kconfig selected explicitly. BUG=b:168820083 TEST=Verified CONFIG_INTEL_CAR_NEM is still enable. Change-Id: Ife1c7d2036cece4598275dfc26ed138fb46bd881 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS KconfigSubrata Banik
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS Update eNEM init flow: - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1 Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000 BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode. Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enableSubrata Banik
As per TGL EDS doc:575681, two ways will be controlled with one bit of SF QoS register(SF Mask#1/#2) hence, selects SF_MASK_2WAYS_PER_BIT for TGL SoC. Change-Id: Ibeef653e0c510b62880b10b3f9767664d89c9623 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15soc/intel/common: Calculate and configure SF Mask 1Subrata Banik
MSR IA_SF_QOS_INFO (0xc87) has been introduced since TGL and is used to find out the NUM_SNOOP_FILTER_WAYS. Bit[5:0] of MSR 0xc87 indicates the maximum number of bits that may be set in any of the SF MASK register. Hence, this patch calculates SF way count using below logic: Calculate SF masks 1: 1. Calculate SFWayCnt = (MSR 0xC87) & 0x3f 2. if CONFIG_SF_MASK_2WAYS_PER_BIT: a. SFWayCnt = SFWayCnt / 2 3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - SF_MASK_2 Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15soc/intel/common: Calculate and configure SF Mask 2Subrata Banik
As per TGL EDS, two ways will be controlled with one bit of SF QoS register hence, this patch introduces SF_MASK_2WAYS_PER_BIT Kconfig to allow SoC users to select SF_MASK_2WAYS_PER_BIT to follow the EDS recommendation. Calculate SF masks 2: 1. if CONFIG_SF_MASK_2WAYS_PER_BIT: a. data_ways = data_ways / 2 Also, program SF Mask#2 using below logic: 2. Set SF_MASK_2 = (1 << data_ways) - 1 Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15mb/google/brya: set PL4 value dynamically for thermalSumeet Pawnikar
Set PL4 value dynamically for brya board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000) Change-Id: I20b98ccd8493ed238de647cda8ceb25f62029133 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15mb/google/brya/{redrix,taeko}: Deduplicate lockdown configFelix Singer
Lockdown configuration is done in their baseboards. Thus, remove the setting from the variants overridetree. Change-Id: Iadb1201718466503987e4f6bd72bf711a2d3128e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-13mb/google/guybrush: Create nipperkin variantKarthikeyan Ramasubramanian
Create the nipperkin variant of the guybrush reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/guybrush -x -a make sure the build includes GOOGLE_NIPPERKIN Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie525ea501e6c3d5d94e67c1db1d4e307fb7ccba7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56921 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13soc/intel/tgl: Hook up ucode for TGL-U and TGL-RTim Crawford
Hook up microcode from 3rdparty repo for: - TGL-U: 06-8c-01 (CPUID signature: 0x806c1) - TGL-R: 06-8c-02 (CPUID signature: 0x806c2) Verified microcode blob was found in CBFS on system76/darp7 (TGL-U). CBFS: Found 'cpu_microcode_blob.bin' @0x103c0 size 0x31c00 in mcache @0x76c2d0ac microcode: sig=0x806c1 pf=0x80 revision=0x88 coreboot reports the correct revision for the microcode. Change-Id: I210c0133dad7ade63b9f7177aaa9a69b019469af Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56862 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13mb/google/brya/variants/brya0: add PL4 values for different SKUsSumeet Pawnikar
Add PL4 values for brya0 board for different CPU SKUs. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000) Change-Id: I095e9eda6665fd1927f35ee57d52922eddd8227a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-13mb/google/guybrush: update USB 2.0 Lane Parameter settings for USB port5Ivy Jian
Tune the USB phy settings to update TXVREFTUNE0/COMPDISTUNE0 to higher value for USB port 5 (Type-A). BUG=b:194053549 TEST= Pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Id1ede34bdbee0c1f9f7d10fc7ffbc9648af31e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56925 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKUMeera Ravindranath
DDR5 Maple Ridge SKU (Board ID 0x16) uses a Memory down DIMM configuration. TEST=Boot DDR5 MR SKU to OS. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56881 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13mb/intel/adlrvp: Rename spd_info struct based on memory topologyMeera Ravindranath
Naming spd_info struct based on memory topology helps in reuse of code. lp4_lp5_spd_info -> memory_down_spd_info ddr4_ddr5_spd_info -> dimm_module_spd_info Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b7a66b5524d8b80776ab7578ce7b13181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-08-13mb/{kontron/bsl6,siemens/chili}: Add `inhibit_flashlock` nvram optionNico Huber
Change-Id: I8c5d6686bf7c694f9d594e3801c79cfd7fb3da80 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56342 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13mb/google/dedede: allow MKBP devices and disable TBMC deviceBoris Mittelberg
Enable MKBP (Matrix Keyboard Protocol) interface for all dedede family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:170966461 TEST=manual test on Madoo: Volume Up/Down and Power buttons, Tablet Mode switch Cq-Depend: chromium:3069163 Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I9d1f43e4dd56318af4c1d5f5c1c3a2c237a05c5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56840 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13mb/intel/adlrvp: Use HDA TMODE 8T to match spec for ADL P RVPSathya Prakash M R
With current setting Display audio codec probe fails. Hence HDMI/DP audio fails. Earlier, with FSP 2037 was used the mode was incorrectly programmed to 4T This setting was carried ahead with below change: Commit : 50f8b4ebdd7db8077b87ab7686637599c9d93af3 The issue was fixed in later FSPs and with current FSP v2237, we need to set the TMODE to 8T as per spec. TEST=Verify HDMI/DP Playback on ADL P RVP Fixes: 50f8b4ebdd7db8077b87ab7686637599c9d93af3 (soc/intel/alderlake: Add enum for HDA audio configuration) Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Change-Id: Ia39a33f5da2fea0dc2eaf4eae45999a711c61c33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56208 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/alderlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/jasperlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/tigerlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/skylake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-clause and adjust comments. This changes behavior since now related options are always set, depending on if coreboot or the FSP should be responsible for the chipset lockdown. This ensures a defined state independent from the default configuration of the FSP. Change-Id: I0c43a11a40a474de4af22aa5506b1d387809bda2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/cannonlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause and adjust comments. Change-Id: I202c212ec8e9ac63f5512c2e74040c23e1562b9a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/alderlake: Configure the SKU specific parameters for VR domainsV Sowmya
This patch configures the SKU specific power delivery parameters for the VR domains. +--------------+-------+-------+-------+-------+-----------+--------+ | SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 682(45W)| IA | 2.3 | 2.3 | 160 | 57 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 482(28W)| IA | 2.3 | 2.3 | 109 | 40 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 282(15W)| IA | 2.8 | 2.8 | 80 | 20 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ These config values are generated iPDG application with ADL-P platform package tool and supports 15W/28W/45W SKU's. RDC Kit ID for the iPDG tools, * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:195033556 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56325 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADLV Sowmya
This patch updates the VccIn Aux Imon IccMax for ADL-P to SOC SKU specific values from the FSP default value 160. * ADL-P 682(45W) = 137. * ADL-P 482(28W) = 128. * ADL-P 282(15W) = 128. These config values are generated iPDG application with ADL-P platform package tool and supports 15W/28W/45W SKU's. RDC Kit ID for the iPDG tools, * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:195033556 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56176 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/apollolake: add 4Gb and 6Gb dram densityJamie Chen
This patch adds 4gb and 6gb dram density support to APL and GLK. BUG=b:178665760 BRANCH=NONE TEST=build fw and flash to the dut, the dut can boot up successfully. Change-Id: Ic0d5d14f26a30da7a9caf4ef43d7fac88a4d2bf1 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55153 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/apollolake: change LPDDR4 density enum definitionJamie Chen
Originally we use rank_density=0 to mean disable the channel, but actually rank_density=0 means 4Gb density in the FSP. This patch changes the LPDDR4 enum values to the real density number and adds a switch statement to mapping the density define in the FSP. BUG=b:178665760 BRANCH=NONE TEST=build fw and flash to the dut, the dut can boot up successfully. Change-Id: I36dba2cef130211e7aea9e2a4f82c5db78f82a83 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56805 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12mb/system76/*: Add CMOS option tableTim Crawford
System76 uses several custom CMOS values downstream. Reduce our diff by providing a generic layout with the defaults: boot_option=Fallback debug_level=Debug power_on_after_fail=Enable Tested on galp3-c, gaze15, oryp5, oryp6. All boards boot multiple times with USE_OPTION_TABLE selected. Change-Id: Ie57b0e5713bba8ad46e1a4123a3ddd43e0eea964 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-08-12soc/mediatek/mt8192: move DFD driver to common folderRex-BC Chen
Move DFD driver to common folder so MT8195 can also use it. BUG=b:192429713 TEST=emerge-asurada coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7937cddf5f3a66f9269a94301d3134e6f4f9f22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-12vc/mediatek/mt8195: Optimize DRAM init time by disabling Vcore settingRyan Chuang
Remove the unnecessary Vcore setting for the DVFS feature. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: If3c28e57a559a7ec04319c1a489138817e44ec4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-12soc/mediatek: revise the dependency of DVFS config optionsRex-BC Chen
The MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT only makes sense if DVFS is enabled (e.g., MEDIATEK_DRAM_DVFS) so we should change it to depend on that instead of selecting DVFS. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib81e4e48e863616ed1e36cd5c0000f4e2cfb5456 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-12drivers/generic/alc1015: Add HID to support alc1019Eric Lai
ALC1019 will use the ACPI compatible and share the same driver with ALC1015. Add HID to support more compatible ICs. BUG=b:195891240 TEST=ALC1019P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3e98297f3a39048b24d61e61ca95c60cd2037eb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-12mb/google/dedede/var/galtic: Add charger throttling functionFrankChu
Add charger current throttling support for galtic control charger index * 64 = Value mA 32*64=2048 28*64=1792 24*64=1536 20*64=1280 BUG=b:187231627 TEST=Built and tested on boten system Cq-Depend: chrome-internal:3846209 Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I5e1849551ff051bca591f19f9e40da4c89ab74e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-08-12mb/google/dedede/variants/haboki: add discrete TPM in overridetreeWisley Chen
Haboki is project which use discrete TPM, so add discrete TPM and disable cr50 in overrideree. BUG=b:187094464 TEST=FW_NAME=haboki emerge-keeby coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I08f2a562c3f62c60402350151ea260b70890a744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-12soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-STim Crawford
Prevent the FSP from writing its default SVID SDID values of 8086:7270 for internal devices as this locks most of the registers. Allows the subsystemid values set in devicetree to be used. A description of this SSID table override behavior, along with example code, is provided in the TigerLake FSP Integration Guide, section 15.178 ("SI_CONFIG Struct Reference"). The xHCI and HDA devices have RW/L registers rather than RW/O registers. They can be written to multiple times but cannot be modified after being locked, which happens during FspSiliconInit. Because coreboot populates subsystem IDs after SiliconInit, these devices specifically must be written beforehand or will otherwise be locked with their default values of 0:0. TGL also introduces parameters for customizing the default SVID:SSID. These must be set or it will still use the FSP defaults. Tested by checking lspci output on System76 darp7 (TGL-U). References: - b1fa231d76a ("soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S") - TigerLake FSP Integration Guide - Intel Document #631120-001 Change-Id: I391b9fd0dc9dda925c1c8fe52bff153fe044d73e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-12mb/google/brya/variants/redrix: enable LTE PCIe portWisley Chen
Enable LTE PCIe port according to fw config. BUG=b:192052098 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Ic9472d2249c622858a75c63bc82e8e4e8166a3d7 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56894 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12mb/google/brya/variants/redrix: add mipi camera supportWisley Chen
Add mipi camera support by selecting the Kconfig symbols and adding it to the devicetree with ACPI UID 0x50000 and name IPU0. BUG=b:192052098 TEST=checked mipi camera works Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I69281f36ddbc1abf9905c8db9287500f9aa995c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56893 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12mb/google/brya/variants/gimble: Update GPIO for PP1800 DMIC enableMark Hsieh
add GPP_D16 in gimle gpio.c and set value to 1 for PP1800 DMIC init sequence BUG=b:195968649 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ia0639162e2c3f02f622470fa16c21fe8a067cf7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56889 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12mb/google/trogdor: Add new variant WormdinglerZanxi Chen
New board introduced to trogdor family. BUG=b:193870279 BRANCH=none TEST=make Change-Id: If3d9662e8725e30e1308d77b05545efbee29f846 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-08-11mb/google/brya/variant/taeko: Update devicetree settingsJoey Peng
Based on schematic and gpio table of taeko, generate overridetree.cb settings for taeko. BUG=b:195494281 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-11soc/intel/alderlake: Implement report_cache_info() functionSubrata Banik
Make use of deterministic cache helper functions from Alder Lake SoC code to print useful information during boot as below: Cache: Level 3: Associativity = 12 Partitions = 1 Line Size=64 Sets=16384 Cache size = 12 MiB Change-Id: I30a56266015d69abccb885b3f230689488ee0360 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 21:55:22 +0000