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authorMartin Roth <martinroth@chromium.org>2021-08-11 13:34:03 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-08-20 15:14:32 +0000
commitb90e6fdd25f7fcc9db6be50a0b117a7509c6fdb1 (patch)
treeb11bebe2c1d2a9809793ecd7a34c7ca4006159cf /src
parentad5b8b8ef94be2ed28a620806ca0620411578ed9 (diff)
soc/amd/common: Skip psp_verstage on S0i3 resume
PSP_Verstage will take almost the entire time to run that is allotted to S0i3 resume. Since coreboot isn't running, the PSP needs to handle any security requirements. The long- term plan is that the PSP won't even load psp_verstage on S0i3 resume, but when it is loaded, this makes sure we exit immediately BUG=b:177064859 TEST=Verify that PSP_verstage doesn't run on S0i3 resume Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/common/psp_verstage/psp_verstage.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c
index 5c59c4f4e4..d223c945db 100644
--- a/src/soc/amd/common/psp_verstage/psp_verstage.c
+++ b/src/soc/amd/common/psp_verstage/psp_verstage.c
@@ -200,6 +200,16 @@ void Main(void)
{
uint32_t retval;
struct vb2_context *ctx = NULL;
+ uint32_t bootmode = 0;
+
+ /*
+ * Currently, we want to skip running verstage on all S0i3 resumes. This relies
+ * on an assumption that the PSP will be checksumming all of its components.
+ * TODO(b/196400450): Remove when PSP no longer loads verstage on S0i3 resume.
+ */
+ svc_get_boot_mode(&bootmode);
+ if (bootmode == PSP_BOOT_MODE_S0i3_RESUME)
+ svc_exit(0);
/*
* Do not use printk() before console_init()