diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-08-10 12:28:09 +0800 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-12 17:59:00 +0000 |
| commit | 716320b726a4fa6e7f42f2aec90de6f98ef52dd3 (patch) | |
| tree | f4e543f8c03de46e69ccee6690f34909e663c16d /src | |
| parent | 45727275476a495044e205ae8fb273feda3f8d5d (diff) | |
soc/mediatek/mt8192: move DFD driver to common folder
Move DFD driver to common folder so MT8195 can also use it.
BUG=b:192429713
TEST=emerge-asurada coreboot
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7937cddf5f3a66f9269a94301d3134e6f4f9f22e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/mediatek/common/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/mediatek/common/dfd.c (renamed from src/soc/mediatek/mt8192/dfd.c) | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/common/include/soc/dfd_common.h | 13 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/dfd.h | 7 |
6 files changed, 22 insertions, 14 deletions
diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index ab24617d86..754c0da580 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -40,4 +40,10 @@ config DPM_FOUR_CHANNEL help This option enables four channel configuration for DPM. +config MTK_DFD + bool + default n + help + This option enables DFD (Design for Debug) settings. + endif diff --git a/src/soc/mediatek/mt8192/dfd.c b/src/soc/mediatek/common/dfd.c index 4d1b08aab4..103151f377 100644 --- a/src/soc/mediatek/mt8192/dfd.c +++ b/src/soc/mediatek/common/dfd.c @@ -6,7 +6,7 @@ void dfd_init(void) { - printk(BIOS_INFO, "[%s]\n", __func__); + printk(BIOS_INFO, "%s: enable DFD (Design For Debug)\n", __func__); setbits32(dfd_cfg, RESET_ON_KEEP_EN); dsb(); } diff --git a/src/soc/mediatek/common/include/soc/dfd_common.h b/src/soc/mediatek/common/include/soc/dfd_common.h new file mode 100644 index 0000000000..d716ed0823 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dfd_common.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_DFD_COMMON_H +#define SOC_MEDIATEK_DFD_COMMON_H + +#define CPC_FLOW_CTRL_CFG 0x0C53A814 +#define RESET_ON_KEEP_EN BIT(17) + +static u32 *const dfd_cfg = (void *)CPC_FLOW_CTRL_CFG; + +void dfd_init(void); + +#endif diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 94e4bd3d14..e099ffdf0f 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -64,10 +64,4 @@ config SRCLKEN_RC_SUPPORT This option enables clock buffer remote controller module to control PMIC 26MHz clock output. -config MTK_DFD - bool - default n - help - This option enables DFD (Design for Debug) settings. - endif diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 5bd88c32a4..934b6888b2 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -46,7 +46,7 @@ ramstage-y += apusys.c ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c -ramstage-y += dfd.c +ramstage-y += ../common/dfd.c ramstage-y += ../common/dpm.c ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/flash_controller.c diff --git a/src/soc/mediatek/mt8192/include/soc/dfd.h b/src/soc/mediatek/mt8192/include/soc/dfd.h index 650e5fd091..e225b08060 100644 --- a/src/soc/mediatek/mt8192/include/soc/dfd.h +++ b/src/soc/mediatek/mt8192/include/soc/dfd.h @@ -3,15 +3,10 @@ #ifndef SOC_MEDIATEK_MT8192_DFD_H #define SOC_MEDIATEK_MT8192_DFD_H -#define CPC_FLOW_CTRL_CFG 0x0C53A814 -#define RESET_ON_KEEP_EN BIT(17) +#include <soc/dfd_common.h> /* DFD dump address and size need to be the same as defined in Kernel DTS. */ #define DFD_DUMP_ADDRESS 0x6A000000 #define DFD_DUMP_SIZE (1 * MiB) -static u32 *const dfd_cfg = (void *)CPC_FLOW_CTRL_CFG; - -void dfd_init(void); - #endif |