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2023-08-09soc/amd/stoneyridge: use SoC common uart opsMatt DeVillier
Define the UARTs as MMIO devices in the chipset devicetrees. Drop ACPI _STA in asl since now handled by common SSDT generator. Implement wait_for_aoac_enabled() since required by SoC common code, and ensure compiled during all stages necessary. TEST=build/boot google/liara, verify console UART still functional. Change-Id: Ibecafdfa189d9c63a29b63759c5b965d03719009 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77093 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09Revert "soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions"Jeremy Soller
This reverts commit 5dfec718290609dc0fd0331070ad703107e0b7e7. Reason for revert: This change made it impossible to disable ASPM by FSP parameter. ASPM_DISABLE would result in the FSP parameter not being programmed, causing it to be the FSP default value instead. This additionally fixes MTL to match ADL. Change-Id: I60c0ea08513fcb0035449ea3fef1681de528c545 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75280 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09mb/ibm/sbp1: call soc soc_config_iio to configure IIO UPDJohnny Lin
Change-Id: I56ee0d4a26931fe05d2d35046325901930086e35 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76344 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09mb/intel/archercity_crb: call soc soc_config_iio to configure IIO UPDJohnny Lin
TESTED=On Intel AC, after seleting DISPLAY_UPD_IIO_DATA to compare IIO UPD data are expected. lspci -vvv result is also normal. Change-Id: Icfc2a22cb2e1f95be6bfc1d712e620e19a23ce27 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-09soc/intel/xeon_sp/spr: Add soc_config_iio to set IIO UPD from mainboardJohnny Lin
To deduplicate mainboard mainboard_config_iio since there are a few SPR-SP mainboards now. The flow would be soc function initialize_iio_upd initializes the table with the default values which are mostly zero, then mainboard can overwrite it by soc_config_iio. Change-Id: I72d74241fcad4c85a95f6d14587418f544caadd9 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76185 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-09mb/google/dedede/var/boxy: Generate new SPD ID for CXDB4ABAM-MLStanley Wu
Generate RAM ID for CXMT CXDB4ABAM-ML DRAM Part Name ID to assign CXDB4ABAM-ML 1 (0001) BUG=b:290154780 BRANCH=dedede TEST=FW_NAME=boxy emerge-dedede coreboot chromeos-bootimage Change-Id: Ide44acf6bb8e5d5023c76d9e5e48ef113f7c6ec6 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76825 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-09mb/system76/tgl: Enable Bluetooth audio offloadTim Crawford
This has two noticeable effects: 1. Devices populate the list much quicker while scanning. 2. Devices do not disappear and reappear from the list while scanning. Tested on system76/lemp10. Change-Id: I598c53805785914b4e9ae7f620e724eadbe643d4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Daniel Sutton <daniel@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77047 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09mb/google/brya/var/yavilla: Modify NVM size and width sizeSerin Yeh
NVM has 8KB to store camera module related settings and parameters. According to NVM hardware spec, the NVM size should be 0x400 and the width size should be 0x08. Re-set the right NVM format and ensure camera related configs can get the correct module information. BUG=b:294155898 TEST=none Change-Id: I58932bc0f3dd935aa0ea8e68b2a4b0ae4907b316 Signed-off-by: Serin Yeh <serin.yeh@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76893 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09mb/google/brya: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. TEST=build/boot Windows/linux on redrix?, verify touchscreen functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I0273014b2d164f67f503da7b968a09256bffb43c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74929 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09mb/google/brya: Implement touchscreen power sequencingMatt DeVillier
For brya variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I8e56ac4834ce69de18bef2d34f5c361a7fda1aab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09soc/intel/xeon_sp/ebg: Add periodic SMI bits definitionMichał Żygowski
Change-Id: Ia906a115538964628958bb4b6e3de3aa71577cce Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76252 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08cpu/amd/pi/00730F01: Use common code for mp_initArthur Heymans
TEST=APU2 still boots and doesn't show any new errors in dmesg. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia9f0eb3df8fd2dfe395f616da981cc3a0cd3b29d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-08soc/amd/common/data_fabric/domain: read IO decode windows from registersFelix Held
Before add_io_regions only reported one fixed IO range to the resource allocator that covered the whole IO range from 0x0000 to 0xffff. Instead read the data fabric IO space decode base and limit address register pairs to get the actual IO port decoding from the data fabric registers. This will also help with adding support for multiple PCI root domains to the common data fabric domain code so that Genoa can use it. In that case each PCI root domain will only decode a part of the whole IO port range. Beware that the data fabric IO base and limit fields can contain values that correspond to IO port addresses far outside of the addressable IO port range. In case of Picasso, the IO limit read from the only enabled DF IO range register would be 0x1ffffff after converting the raw data to an IO port address. To not give the resource allocator wrong constraints make sure that the IO limit we report will be at maximum 0xffff. TEST=On Mandolin (Picasso) and Birman (Phoenix) the full range of IO port addresses still gets reported as a domain IO resource producer like before the patch: DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I087d96f7bdaae0d7b53089f6abaf0500a4b064e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/glinda/include/data_fabric: add data fabric IO decode registersFelix Held
PPRs #57254 Rev 1.52 and #57255 Rev 0.33 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia58e26caa1ba910b41911991b176a1ac8c4e0065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/phoenix/include/data_fabric: add data fabric IO decode registersFelix Held
PPRs #57019 Rev 3.05 and #57396 Rev 3.06 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I769dc317115981391cf0f4e0b743c600407a6eb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76958 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08soc/amd/mendocino/include/data_fabric: add DF IO decode registersFelix Held
PPRs #57243 Rev 3.02 and #56558 Rev 3.04 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic68e73e28362abc5d812839b40282114c7ba25ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/76957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/cezanne/include/data_fabric: add data fabric IO decode registersFelix Held
PPR #56569 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifcae9c9ad664d50100cd40692fd9631845f76671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/picasso/include/data_fabric: add data fabric IO decode registersFelix Held
PPR #55570 Rev 3.18 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I61d4fca48d71010bbc4bd94a2fb8889bad08f1cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-08soc/amd/common/data_fabric/domain: rename add_io_regionsFelix Held
Rename add_io_regions to add_data_fabric_io_regions to be consistent with add_data_fabric_mmio_regions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia990cc14dd6dc162ad614a6e9e0b36426cb04670 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-08soc/amd/common/data_fabric/domain: factor out report_data_fabric_ioFelix Held
As a preparation to read the IO decode ranges from the data fabric registers instead of having it hard-coded, factor out the report_data_fabric_io function to report one IO producer region from add_io_regions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I51c3f8cd6749623f1a4bad14873d53b8a52be737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76933 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08soc/amd/*/include/data_fabric: add dst_ prefix to fabric_id fieldFelix Held
Rename the fabric_id struct field in the df_mmio_control union to dst_fabric_id to both better match the register definitions and also be a bit clearer about what this is doing. Also use tabs for indentation in the struct inside the df_mmio_control union. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0a17d82a5d7b66a8f84854f21fbbb319da81ac43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-08soc/amd/*/include/data_fabric: reorder register definitionsFelix Held
Order the data fabric register definitions by function number and register offset. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia3066ad0f564520cb322a3e41a413eb3bf51260d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_*Felix Held
Now that the data fabric PCI device functions are included in the register definitions, the remaining data fabric device function numbers can be dropped from the define names. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1a26402b8078d288a7e32c1668591d001fa3ede9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76889 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08soc/amd/*/include/data_fabric: rename D18F0_MMIO_* to DF_MMIO_*Felix Held
Now that the data fabric PCI device functions are included in the register definitions, the remaining data fabric device function numbers can be dropped from the define names. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia0355838ac1d513ba562fd6fb4672342dd383498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76888 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08soc/amd/common/data_fabric_helper: use DF broadcast read/write functionsFelix Held
Instead of open coding the broadcast data fabric PCI register access in the functions for indirect non-broadcast data fabric register access, just use the existing data_fabric_broadcast_[read,write]32 functions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I174c1e6ee4856d97c5ec6d07bb8c217d6df9425f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macrosFelix Held
To have both the PCI function number and the register offset into the config space of that function of the data fabric device in the data fabric register definitions, introduce and use the DF_REG_ID, DF_REG_FN and DF_REG_REG macros. The DF_REG_ID macro is used for register definitions where both the function number and the register offset are specified, and the DF_REG_FN and DF_REG_REG macros are used to extract the function number and the register offset from the register defines. This will allow having one define for accessing an indexed group of registers that are on different functions of the data fabric device. TEST=MMIO resources read from the data fabric's MMIO decode registers don't change on Mandolin and the ACPI CRAT table is also identical. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63a284b26081c170a217b082b100c482f6158e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76886 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08sb/intel/i82371eb: Streamline IDE debug messagesKeith Hui
Debug messages shown during IDE initialization are streamlined as follows: "Primary IDE interface" (and similar) are shortened to "Primary interface". We don't need to see "IDE" twice as messages are already prefixed. Refactor "IDE: (Primary) IDE interface: (on)" into "IDE: (Primary interface): (on)" to allow compiler to deduplicate component strings, also used later in messages re UDMA/33. This reduces uncompressed string size by 32 bytes and allows ramstage to compress a wee bit better. Change-Id: I16f5c2b3775c5a73b83d83817d7075e944089a12 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73331 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08superio/serverengines/pilot: drop unused super I/O chipFelix Held
Since it was the only super I/O in the serverengines folder, also drop the parent folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I610c94bc100c9d5558da442b2847d8f26de07820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77064 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08mb/google/rex/variants/ovis: Use correct device_index for RT8168Stefan Reinauer
Fix ethernet MAC address configuration. Currently, coreboot would use ethernet_mac0 for both ports when setting the system's MAC address. Instead, set the right device_index for the second controller to pick up ethernet_mac1. BUG=b:294856127 TEST=boot device and observe two different MAC addresses on the ethernet ports. Change-Id: I5ff6d62d2f837a120f7095f9b9aed487e6c5aee4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77044 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08mb/google/brask/var/kuldax: Set power limit values for RPL SKUsDavid Wu
Add the RPL CPU power limits and system power limits based on the suggestion of the thermal team for RPL SKUs. The PL4 value suggested by the thermal team which is different from the reference document 686872. BUG=b:292471206 BRANCH=firmware-brya-14505.B TEST=built and booted into OS. Change-Id: Ia030d13ca276c5e8340ae3b20d6e169bb162751d Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76769 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2023-08-08mb/asrock/b75pro3-m: Drop destructive GPIO settingsFabian Groffen
Without setting these GPIO bits, you /can/ power on your board after powering it down again. This includes after cutting the power. The only way to recover from this is to pull the CMOS battery and cut the power for 15mins. Then make sure you don't do this GPIO trickery or you end up with the same state of basically an unresponsive "dead" mainboard. So flash the chip before you pull the battery. One small workaround I found when you like to flash from the system, is to press the power button with 1 second after you enable power to the board. In this small timeframe, apparently the superio chip didn't intialise/restore/gets set with the settings that make it never want to power on again. The other workaround is to connect the appriopriate pins on the ATX power connector to force power to the mainboard. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I4c9df200ba3ec5f315ad3d184588551d29fa68ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/75212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08vendorcode/cavium: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I19c029968584fedbb6749e66c7ea2f74a7d580f4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08mb/google/poppy/rammus: Fix jack detect GPIO configurationMatt DeVillier
Copy jack detect GPIO config of NAMI variant, which uses the same codec for the external jack/mic. The internal pull-up isn't needed, and fixes issue of high CPU usage under Windows. TEST=build/boot google/rammus, verify jack detect functional under both Win11 and Linux 6.x, no high CPU usage from excessive interrupts. Change-Id: Ifbe23a6b33343e54b43879a8971c7cb6475cf1f0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76947 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08mb/google/nissa/var/yavilla: Update eMMC DLL settingsTony Huang
Update eMMC DLL settings to prevent eMMC initialization error BUG=b:290567342 TEST=warm/cold reboot stress test 2500 times pass Change-Id: I418836ec3e2d2221c219eae35e2b22aeaacce4a5 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-08mb/google/rex/var/screebo: Change sdcard clk from 7 to 6Kun Liu
Update firmware to reflect schematics change for SD Card CLKSRC from 7 to 6 for EVT board revision BUG=b:291051683 TEST=emerge-rex coreboot Change-Id: I3347f739650458c833d5a825742cf1d663853cc5 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77023 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08ACPI: Add helper fill_fadt_extended_pm_io()Kyösti Mälkki
Once platform code has filled in the (legacy) ACPI PM register map, added function will fill in the extended entries in FADT. TEST=samsung/lumpy and amd/mandolin FADT stays unchanged. Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-07mainboard/protectli/vault_cml: Switch to IT8784EMichał Żygowski
The first platform samples came with IT8786E. The production units switched to IT8784E in the final design. Change the code to use IT8784E and reflect the proprietary firmware configuration of the SIO chip. TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the configuration with superiotool and compare the configuration with proprietary firmware. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5dc6669b592484e445c8c4bbe95d73f0a9f0392e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74175 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-07superio/ite: Add IT8784E supportMichał Żygowski
IT8784E is basically a IT8786E stripped from serial ports 3-6. The patch creates a chip directory for IT8784E used by protectli/vault_cml platforms. TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the configuration with superiotool and compare the configuration with proprietary firmware. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ibe01358611f3ce3f155ddb01a7d177a3ff75765e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-07mb/google/dedede/var/boxy: Update power limitsStanley Wu
Add ramstage.c in Makefile.inc and update boxy power limits in Boxy ramstage.c. BUG=b:290293153 TEST=emerge-dedede coreboot and check psys and PLx value on boxy Change-Id: I4257dab358f066ebd13b6f251e8a5258a72fbd39 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76877 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06soc/mediatek/mt8188: Support ARM arch timerYidi Lin
Use ARM architectual timer by initializing frequency to 13 MHz. Since system timer is the source of the architectual timer, we also call `timer_prepare` in `init_timer`. BUG=b:229800119 TEST=run `suite:faft_bios` to verify the firmware stability. check timestamps by cbmem. Cq-Depend: chromium:4747539 Change-Id: I8b1348044e4c92984510604b7f61611e13284d86 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76919 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06mb/google/brya: Add DRIVERS_GFX_GENERIC to BRYA by defaultWon Chung
All boards based on brya will have GFX devices to represent DRM connectors in the kernel's /sys/class/drm/. There should be no functional impact with or without this patch. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I11afa9e8a1c8bf9f57bf6d195f07531182bd36f1 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-06device, soc: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the device and soc directories that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I89c05c7c1c39424de2e3547c10661c7e3f58b8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-08-06mainboard: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-06drivers: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the drivers directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8442bc18ce228eca88a084660be84bcd1c5de928 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68980 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-06cpu: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the cpu directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3033f2a9eebc75220f7666325857b3ddd60c8f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68979 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-06mb/google/brya: select ENABLE_TCSS_USB_DETECTIONMatt DeVillier
Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable booting from TCSS USB-C ports. TEST=build/boot google/banshee, verify able to boot from all USB ports using edk2 payload. Change-Id: I998cc4a40950f43b4c511ead93ccc02c56c8367c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76945 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06mb/google/volteer: select ENABLE_TCSS_USB_DETECTIONMatt DeVillier
Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable booting from TCSS USB-C ports. TEST=build/boot google/drobit, verify able to boot from USB ports using edk2 payload. Change-Id: Ic6ab84dd5d1b980296eac043917d2cc7f14a5536 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-08-06soc/intel/common/tcss: Configure USB-C ports with attached devicesCoolStar
Inspect all type-C USB ports, check if there is a USB device attached, and if so, send the connection request to the PMC. This allows for any attached USB2/USB3 devices to be used for booting by the payload. Since this functionality is only needed by ChromeOS devices with TCSS running upstream coreboot, introduce a new Kconfig to guard its use. Boards needing it will select it in subsequent commits. TEST=tested with rest of patch train Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72909 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06soc/intel/common/block/tcss: Fix printk formattingMatt DeVillier
Variable 'i' is unsigned, so use %zu vs %zd. Change-Id: I5f5b28796b30285e81a94c37e686a9e763cab204 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76943 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05commonlib/fsp_relocate: Fix pe_relocate() return value on successJeremy Compostella
Similarly to te_relocate(), on success pe_relocate() should return 0. It has never been an issue so far as pe_relocate() return value is not tested. Change-Id: I8e531662952d12e1f0ffa34042dab778ea602bfc Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76891 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-05mb/system76: Enable C10 reporting on systems using eSPITim Crawford
Report CPU C10 state over eSPI so that the EC can use Virtual Wires to detect if PECI can be used. Change-Id: I301361f35caee8ba1c3fd9227219603897add92b Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76910 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/system76/cml-u: Fix inclusion of romstage.cTim Crawford
When lemp9 was converted to a variant in CB:64528, the Makefile was not updated to handle the variant-specific `romstage.c`. This, as would be expected, caused memory init errors and broke boot on CML-U boards. Tested lemp9 boots to payload again. Fixes: 5b7b04c938f2 ("mb/system76/cml-u: Convert lemp9 to a variant") Change-Id: Ibc11d69a1662df653e6553421d67a9cd1b1d03e2 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-08-05mb/google/dedede: Enable wake from S0ix on EC_HOST_EVENT_HANG_DETECTReka Norman
BUG=b:279097356 TEST=On dibbi: - flash OS 15449.0.0 (where suspend is broken due to b:274531972) - run `suspend_stress_test --count=1 --suspend_max=30 --suspend_min=28` - check the AP wakes up immediately when the EC detects a sleep hang Change-Id: I24a2aa5de1f76e6dd1c1ce726b648583756e5e55 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76938 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05mb/google/dedede/var/boxy: Add power limits for N4500/N5100Stanley Wu
Add PLx from JSL PDG(ID: 613095) in boxy devicetree. BUG=b:290293153 TEST=emerge-dedede coreboot and read correct value on boxy CPU log: CPU TDP = 6 Watts, CPU PL4 = 60 Watts Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76876 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05src/*/post_code.h: Change post code prefix to POSTCODEYuchen He
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. header="src/soc/amd/common/block/include/amdblocks/post_codes.h \ src/include/cpu/intel/post_codes.h \ src/soc/intel/common/block/include/intelblocks/post_codes.h" array=`grep -r "#define POST_" $header | \ tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2` for str in $array; do splitstr=`echo $str | cut -d '_' -f2-` grep -r $str src | cut -d ':' -f 1 | \ xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g" done Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05mb/google/nissa/var/craaskov: Add wifi sar tableJamie Chen
Add wifi sar table for craaskov BUG=b:290739538 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ib21f674b6749e125bf76a196902c994bfac15e65 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76576 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/rex: enable d3hot for storage devicesSukumar Ghorai
_DSD "StorageD3Enable" property is needs to be set under the root port in the DSDT or SSDT. The ACPI _DSD method is the preferred way to opt D3hot support for storage devices. This also bypasses the low LTR from SSD that blocking S0i2.2 LTR/latency SoC requirement. Name (_DSD, Package () { ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"), Package () { Package (2) {"StorageD3Enable", 1}, // 1 - Enable; 0 - Disable } } ) BUG=b:289028958 TEST=Check code compiles & boot rex, and verify the "StorageD3Enable" SSDT entry. Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76835 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/nissa/var/craaskov: Configure the external V1p05/Vnn/VnnSxRex Chou
This patch configures external V1p05/Vnn/VnnSx rails for Craaskov to follow best practices for power savings – untested though. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:290165011 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ibaf6a285788e26688d3d42691ab40052ef6d6cdb Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76926 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/nissa/var/craaskov: Add DPTF parametersVan Chen
The DPTF parameters were verified by the thermal team. Based on thermal table in 290705146#comment11. Set "tcc_offset" = "8" BUG=b:290705146 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76712 Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05mb/google/glados: use acpi_is_wakeup_s3() vs FSP UPDMatt DeVillier
To be consistent with other boards setting the keyboard backlight at boot. Change-Id: I40d8ebe468a967f0dfe1e82bff9c63f1986699c7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76942 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/eve: Use keyboard backlight for proof-of-life at bootMatt DeVillier
This feature was originally present and then dropped, but turns out that users prefer it. Set the backlight to 50% in romstage, back to zero in ramstage; skip enabling on the S3 resume path. TEST=build/boot google/eve, verify keyboard backlight turns on/off as expected. Change-Id: I33af888d614010538f69512bbd052ed2b83fcaa5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-05mb/google/rambi: Fix built-in audio under WindowsMatt DeVillier
Move the jack detect GpioInt resources under the codec (where they belong), but also leave a copy under LPEA for since the Linux drivers (incorrectly) require them there. Add pin list for Windows' SST driver. Adapted from the Intel ValleyView edk2 ACPI reference code. TEST=build/boot Win11, Linux on google/swanky; verify audio functional OOTB under Linux, under Windows with coolstar's drivers. Change-Id: I51c07013fc20f07d2fd3639f7fbc2af0e0e490a0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76795 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2023-08-05mb/google/cyan: Adjust ACPI for Maxim audioMatt DeVillier
- add HRV and GpioIO for coolstar's windows drivers - fix interrupt type for TI jack detect switch TEST=build/boot Win11, Linux on google/cyan; verify audio working OOTB under Linux, under Windows with coolstar's audio drivers. Change-Id: I6bf6bb9e9989ca8f42436800666d95dd05799838 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76800 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-08-05sb/intel/lynxpoint/Kconfig: Remove SOUTH_BRIDGE_OPTIONSElyes Haouas
Remove dummy SOUTH_BRIDGE_OPTIONS. Change-Id: Ic2f10ef03844ff55addfa27035b54971ac41dbc9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-05sb/intel/ibexpeak/Kconfig: Remove SOUTH_BRIDGE_OPTIONSElyes Haouas
Remove dummy SOUTH_BRIDGE_OPTIONS. Change-Id: Ifce7965040d96486ee8de2fba2ead9c54ee9a9f9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76948 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04mb/hp: Add EliteBook 820 G2Iru Cai
Most of the components of this laptop are tested to work, which is listed in the documentation. Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04bootsplash: Add ImageMagick voodooNico Huber
The JPEG decoder, that was added many years ago to display a boot- splash in coreboot, has a few quirks. People used to do some voodoo with GIMP to convert images to the right format, but we can also achieve the same with ImageMagick's `convert`. The currently known constraints are: * The framebuffer's color format is ignored, * only YCC 4:2:0 color sampling is supported, and * width and height have to be a multiple of 16 pixels. Beside that, we can only display the bootsplash if it completely fits into the framebuffer. As the latter's size is often decided at runtime, we can't do much more than offering an option to set a specific size. Change-Id: I564e0d89fb46503ff4c11e095726616700009968 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04mb/amd/birman/port_descriptors_phoenix.c: Disable ASPMFred Reitberger
Disable ASPM on ethernet, sd card, wwan, wlan, and ssd0 PCI devices. This reduces kernel error logs such as: [ 15.172613] r8169 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I7b1605f18a91ed20bfc6ab70547c415e0278d290 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04soc/amd/phoenix: Makefile change to include split hash tableKarthikeyan Ramasubramanian
Include multiple hash tables into relevant CBFS. BUG=b:277292697 TEST=Ensure that all multiple hash tables are part of Myst BIOS image with PSP verstage enabled. Change-Id: I1601f4a01db5b2bbf8b5636ef9e69e41c1d9a980 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76589 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/phoenix: Add SVC call to inject v2 hash tablesKarthikeyan Ramasubramanian
On mainboards using Phoenix SoC with PSP verstage enabled, to accommodate growing number of PSP binaries, multiple smaller hash tables are introduced. Also some hash tables are in V2 format identifying the concerned PSP binaries using UUID. Add SVC calls to support multiple hash tables with different versions. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Ensure that all the hash tables are injected successfully. Ensure that PSP validated all the signed PSP binaries using the injected hash tables successfully. Change-Id: I64e1b1af55cb95067403e89da4fb31bec704cd4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76588 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/common/psp_verstage: Support multiple hash tablesKarthikeyan Ramasubramanian
Currently PSP verstage updates PSP bootloader with one unified hash table containing hashes for all the signed PSP binaries to be validated. With growing number of PSP binaries to validate and memory constraints in PSP, there is a requirement to split and update the hash table into multiple smaller chunks. Hence change the update_psp_fw_hash_table() signature such that the hash tables are updated in a chipset specific way. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Build the Skyrim BIOS image and confirm that the hash table is identical before and after this change. Change-Id: I75aac5bc5e7f61069be25d801d0838fdf565d3d1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76587 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04mb/google/skyrim: Select ACPI_S1_NOT_SUPPORTEDTim Van Patten
As of OS/FW: 15276.0.0 - Skyrim is not able to wake from S1/standby. The wake issue either needs to be fixed, or S1 should not be advertised as a capability in the ACPI table. Select ACPI_S1_NOT_SUPPORTED to indicate that ACPI state S1 is not supported on Skyrim devices. This results in 'standby' being removed from /sys/power/state. BUG=b:263981434 TEST=suspend_stress_test TEST=frostflow-rev2 ~ # cat /sys/power/state freeze mem Change-Id: I85fcdca34187a8c275cf5a93beb931dfb27a7c87 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04mb/google/{rex,ovis}: Disable C1-state auto demotion for rex & ovisSukumar Ghorai
C1-state auto demotion feature allows hardware to determine C1-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter PC2 and lower state in camera preview case and save platform power. Note: C1 demotion heuristics used EPB parameter to balance between power and performance, i.e. low threshold when EPB is low in-order to get C1 demotion faster and vice-versa. ChromeOS operates at default EPB=0x7 (low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits than expected (similar to AC mode) and losing power respectively. BUG=b:286328295 TEST=Code compiles and correct value of c1-state auto demotion is passed to FSP. Also verified PC residency improvement ~10% in camera preview case. Change-Id: I548e0e5340dec537d05718dd2f4652e10fb36ac0 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04soc/amd/common/data_fabric_helper: add comment about cfg_inst_acc_enFelix Held
Since all indirect data fabric register accesses will be non-broadcast accesses that target a specific data fabric instance, the cfg_inst_acc_en bit in the DF_FICAA_BIOS register will always be set since that makes the indirect access target only a specific data fabric instance. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9aff01750c2c1e3506141b3ed293a980a64f8fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/76885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-04soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotionSukumar Ghorai
FSP has a parameter to enable/disable c1-state autodemotion feature. Boards/Baseboard can choose to use this feature as per requirement. This patch hooks up this parameter to devicetree. BUG=b:286328295 TEST=Check code compiles & boot google/rex, and correct value has been passed to FSP. Change-Id: I2cc60bd297271fcb3000c0298af71208e3be60fc Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76826 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-08-04soc/intel/mtl: Change default for debug consent from 3 to 6Kane Chen
USB DBC is very helpful for SoC debug. TraceHub needs to be enabled in coreboot if debug consent == 2 or 4. Debug consent == 6 enables USB DBC without TraceHub enabled. This patch updates the Kconfig help text to meet PlatformDebugOption in MTL and changes debug consent to 6 in default to provide basic SoC debug capability. TEST=Boot to OS on screebo and DBC connection is OK. Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76880 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/sifive/fu540/Kconfig: Fix opensbi platformMaximilian Brune
commit 9a7a677 from opensbi project moved the fu540 platform to generic code and commit 26998f3 from opensbi removed the old non generic platform. Therefore opensbi platform needs to change to generic. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I76aa3d386936b331785a23edb8deb0d73609be47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04ec/google/chromeec: move TBMC ACPI device under CRECMatt DeVillier
Tablet motion control is a function of the EC, and under Windows, the TBMC device needs to be initialized after CREC, or driver init will fail. The only way to ensure this happens is for TBMC to be a child device under CREC. TEST=build/boot Win11, Linux on google/eve, verify tablet mode drivers loaded and orientation switching functional under both OSes. Change-Id: I5e9eab9ae277b5a04dc2666960a727e5680bf6f4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76792 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04soc/intel/common: Return CB_ERR when cse_data_clear_request() failsKrishna Prasad Bhat
cse_prep_for_rw_update() should return CB_ERR when cse_data_clear_request fails. It was modified to CB_SUCCESS in this commit ad6d3128f87c ("soc/intel/common: Use enum cb_err values") BRANCH=None BUG=None TEST=Verify the system goes to recovery during downgrade when cse_data_clear_request() fails. Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-04soc/intel/meteorlake: Generate new TME key on each warm bootPratikkumar Prajapati
Enable config TME_KEY_REGENERATION_ON_WARM_BOOT for Intel Meteor Lake SOCs. This config allows Intel FSP to programs TME engine to generate a new key for each warm boot and exclude CBMEM region from being encrypted by TME. Bug=b:276120526 TEST= Boot up the system, generate kernel crash using following commands: $ echo 1 > /proc/sys/kernel/sysrq $ echo "c" > /proc/sysrq-trigger System performs warm boot automatically. Once it is booted, execute following commands in linux console of the DUT and confirm ramoops can be read. $ cat /sys/fs/pstore/console-ramoops-0 S0ix also tested and found working. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-04mb/google/rex/var/screebo: Add fw_config probe for GL9750 and RTS5227SKun Liu
Add support for SD card reader GL9750 and RTS5227S BUG=b:284273384 TEST=emerge-rex coreboot Change-Id: I98aa0d3e52c355f6c1528c912a6fa0f32652dda8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-04mb/google/dedede/var/pirika: Support for Samsung K4U6E3S4AB-MGCLDaniel_Peng
Add the new memory support: Samsung K4U6E3S4AB-MGCL BUG=b:294151054 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/lp4x/gen_part_id.go JSL lp4x \ src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" Change-Id: Ief9bbf11fc05c8155f1da7188926a29dbbfbe488 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76542 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04cpu: Get rid of CPU_SPECIFIC_OPTIONSElyes Haouas
Remove dummy CPU_SPECIFIC_OPTIONS. Change-Id: I267b2a7c6dfc887b572e1b63b0f59fbfa4d20f0e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76681 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03drivers/intel/gma/Kconfig: Remove unused INTEL_GMA_OPREGION_2_0Elyes Haouas
Change-Id: I9241d713fb8cc26c768746c8e442b46292036d20 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76694 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/common/block/cse/Kconfig: Remove unused symbolsElyes Haouas
Change-Id: I35742721e049102a3e153b857824073a5d257cc3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76693 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/xeon_sp/spr/Kconfig: Remove unused MAX_MC_CHNElyes Haouas
Change-Id: Ia4011a0f29d360fbe46a5e052e2acb3d23d8ceaf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76695 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03mb/ibm/sbp1/Kconfig: Remove unused MAX_SOCKET_UPDElyes Haouas
Change-Id: I5d9133f2255a96c8367f69dcbb198a1a142cdb82 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/jasperlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I5ad1a1bf51bb7a451239252f01a90c1d4d94ba49 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76685 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/skylake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Iea0e55c6c55635976dad0422470f3927bdc26e35 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/tigerlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Id268943b9347fdb54e07b55c0a2a18ac77bb3a58 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/xeon_sp/Kconfig: Remove useless USE_FSP2_0_DRIVERElyes Haouas
Change-Id: Ic384ee804e217ba79f7e191f122ec61565abfc40 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/xeon_sp/spr/Kconfig: Remove unused SIPI_FINAL_TIMEOUTElyes Haouas
Change-Id: I915e0e942adf33175fdc9fe055fce013824d6c0f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76698 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/broadwell/Kconfig: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I4ccb8d38f18cb440f54723cc1f29e25b82dac8ee Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76700 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03mb/google/nissa/var/pirrha: Generate SPD ID for supported memory partSeunghwan Kim
Add pirrha supported memory parts in mem_parts_used.txt, generate SPD IDs for them. 1. K3KL8L80CM-MGCT (Samsung) 2. K3KL6L60GM-MGCT (Samsung) BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76881 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/meteorlake: Set UPDs for TME exclusion range and new key genPratikkumar Prajapati
Set UPD params GenerateNewTmeKey, TmeExcludeBase, and TmeExcludeSize when TME_KEY_REGENERATION_ON_WARM_BOOT config is enabled. These UPDs are programmed only when INTEL_TME is enabled. Bug=b:276120526 TEST=Able to build REX platform. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75626 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/common: Merge TME new key gen and exclusion range configsPratikkumar Prajapati
Merge TME_KEY_REGENERATION_ON_WARM_BOOT and TME_EXCLUDE_CBMEM_ENCRYPTION config options under new config option named TME_KEY_REGENERATION_ON_WARM_BOOT. Program Intel TME to generate a new key for each warm boot. TME always generates a new key on each cold boot. With this option enabled TME generates a new key even in warm boot. Without this option TME reuses the key for warm boot. If a new key is generated on warm boot, DRAM contents from previous warm boot will not get decrypted. This creates issue in accessing CBMEM region from previous warm boot. To mitigate the issue coreboot also programs exclusion range. Intel TME does not encrypt physical memory range set in exclusion range. Current coreboot implementation programs TME to exclude CBMEM region. When this config option is enabled, coreboot instructs Intel FSP to program TME to generate a new key on every warm boot and also exclude CBMEM region from being encrypted by TME. BUG=b:276120526 TEST=Able to build rex. Change-Id: I19d9504229adb1abff2ef394c4ca113c335099c2 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76879 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03mb/google: Add more comment on GFX devices for the future referenceWon Chung
Add more details to instruct future boards/models implementers regarding how GFX devices should be added. If HDMI and DP connectors are enumerated by the kernel in /sys/class/drm/ then corresponding GFX device should be added to ACPI. It is possible that some connectors do not have dedicated ports, but still enumerated. The order of GFX devices is DDIA -> DDIB -> TCPX. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76776 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-03mb/google/nissa/var/craaskov: Add overridetreeRex Chou
Add override devicetree based on schematics(ver. 20230714). BUG=b:290248526 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id002282d91dc94b00f5d133203b62ca39d6cae6d Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76662 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properlyMichał Żygowski
Build issue introduced by patch CB:76418 (commit hash 01025d3ae78e02192d389f22abd36747e3d8c63b) for Google boards. Patch has not been rebased to latest master and tested before submission causing the Jenkins jobs to fail. Change-Id: I95bd2485b98be4ab3a39eaaebb9efb34db93bbe8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03src/soc/intel/alderlake: add SOC_INTEL_RAPTORLAKE_PCH_S symbolMichał Żygowski
Introduce new symbol SOC_INTEL_RAPTORLAKE_PCH_S that can be selected by board with RPL-S PCH. For now only the IoT variant of RPL-S FSP is available for use with 700 series chipsets. Boards with 600 series chipsets can still use RPL CPUs with the ADL-S C.0.75.10, which contains minimal RPL-S CPU support. Change-Id: I303fac78dac1ed7ccc9d531a6c3c10262f7273ee Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 15:50:26 +0000