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2023-08-30soc/intel/meteorlake: Allow to override Fast VmodeJay Patel
This patch adds option to override Fast Vmode on Meteor Lake SoC. This requires CepEnable, EnableFastVmode, IccLimit FSPM UPDs in FSP header. If the hardware supports Fast Vmode, the FSPM will set the ICC limit value to the value passed from coreboot. With CepEnable and EnableFastVmode enabled, if IccLimit is not specified by coreboot, FSPM sets IccLimit as default value. If no values assigned to all the three CepEnable, EnableFastVmode and IccLimit, coreboot sets their values to 0 and Fast Vmode is disabled. BUG=b:286809233 TEST=In debug MTL FSP logs, the value of FSP parameters is as passed from coreboot including enable_fast_vmode, cep_enable, and fast_vmode_i_trip. Also, fast_vmode_i_trip value is passed to pcode using mailbox command without any error. This test done on google/rex board. Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: Id05dccac56c504523f9327babe0c6fbeff488ec2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75566 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-30mb/google/rex/var/karis: Remove USB cameraTyler Wang
Karis use MIPI camera only, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I96316d63c068c48b5bec75d3b4c5444d15fd985f Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77510 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-30mb/google/rex/var/karis: Remove SAR sensorTyler Wang
According to the schematic, karis does not have a SAR sensor. Update GPIO settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ib3b66b9594f2d0fddbbfc56e99f06b6587487f2a Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-30mb/google/rex/var/karis: Set GPP_D04 to NCTyler Wang
Follow schematic, set GPP_D04 to NC. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ie222a2773ff7d2b87641f55b4d37ff3bdf761cd2 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-30mb/google/rex/var/screebo: Enable GL9750 invert WP functionKun Liu
enable GL9750 invert WP function BRANCH=none BUG=b:297244291 TEST=emerge-rex coreboot Change-Id: I7fdc94b5ca6b316ee0291c38e39c5f8b08cbc127 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77414 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-30drivers/genesyslogic/gl9750: Add invert write protect polarityBen Chuang
Add an option to invert write protect polarity for GL9750. Change-Id: I5761f3066291a2400caecbecc79ae893f0a0c146 Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77403 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-29soc/amd/common/data_fabric/Makefile: remove invalid commentFelix Held
The !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE comment was likely a copy-paste leftover, so remove it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45b12d1dc5af84be99d54fea0c9ccf610cf5dae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-29Revert "soc/intel/meteorlake: Generate new TME key on each warm boot"Subrata Banik
This reverts commit 5013c60a871af8fbce8c38a1c342c454e5b8452f. Reason for revert: consecutive reboots are causing kernel panic. BUG=b:297153853 TEST=Able to perform 50 cycles of consecutive reboot after reverting this CL and it boots to the OS every single time(w/o any kernel panic). Change-Id: If6c96dcc62c706a522b98a1cf1dd1920ad6473a1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77467 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-29drv/intel/fsp2_0: Add FW Splash Screen event log entriesSubrata Banik
This patch adds logic for logging the FW splash screen event to the event log. There could be three possible scenarios as below: 1. Platform w/o FW splash screen (i.e., either HAVE_FSP_LOGO_SUPPORT or BMP_LOGO configs not enabled) Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) not present in the event log. 39 | 2023-08-27 12:42:54-0700 | System boot | 12 40 | 2023-08-27 12:42:54-0700 | ACPI Wake | S5 41 | 2023-08-27 12:42:54-0700 | Wake Source | Power Button | 0 2. Platform w/ FW splash screen (i.e., both HAVE_FSP_LOGO_SUPPORT and BMP_LOGO configs are enabled) Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) is enabled in the event log. 34 | 2023-08-27 12:07:29-0700 | System boot | 11 35 | 2023-08-27 12:07:29-0700 | Firmware Splash Screen | Enabled 36 | 2023-08-27 12:07:31-0700 | ACPI Wake | S5 37 | 2023-08-27 12:07:31-0700 | Wake Source | Power Button | 0 3. Failed to render FW splash screen (due to any reason if FSP failed to render the splash screen) Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) is disabled in the event log. 43 | 2023-08-27 13:06:10-0700 | System boot | 13 44 | 2023-08-27 13:06:10-0700 | Firmware Splash Screen | Disabled 45 | 2023-08-27 13:06:11-0700 | ACPI Wake | S5 46 | 2023-08-27 13:06:11-0700 | Wake Source | Power Button | 0 BUG=b:284799726 TEST=Verify that the event shows up in the event log when the user selects the HAVE_FSP_LOGO_SUPPORT and BMP_LOGO configs to display the firmware splash screen. Change-Id: Ie9e09acff5443c31b881c300134bc0bb06c490c6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-29commonlib: Add ELOG_TYPE_FW_SPLASH_SCREEN eventLogSubrata Banik
This patch adds a new eventLog type ELOG_TYPE_FW_SPLASH_SCREEN to support logging when we show firmware splash screen to the user. BUG=b:284799726 TEST=Event shows in eventlog when user selects BMP_LOGO and HAVE_FSP_LOGO_SUPPORT configs. Change-Id: Id1572ecb83ca025ff65608e7ae4f3a065024f6d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77507 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28src/device/dram/Makefile.inc: specify one file per lineSergii Dmytruk
A trivial follow-up on CB:67060. This makes contents of the file look a bit less regular, but more like the rest Makefile.inc in the code base. Change-Id: I772d37825e4b59cf927637dc39bfb3ee06115860 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77533 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28Revert "mb/google/brya: fix MRC cache failure for hynix parts"Nick Vaccaro
This change causes a freeze during boot on an RPL-UR that does not have the memory part string in the CBI. BUG=b:296353047 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage', flash and boot problematic DUT to kernel. This reverts commit c51a7cdde4e1cb9014be401136c3f07f220ef365. Change-Id: I99fe5111b5294673d9e0a5d13f9c240e0f4a92c3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77516 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: <srinivas.kulkarni@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28mb/google/rex/var/rex0: Enable BT offload audio for Intel MtP2 moduleAnil Kumar
Enable the required GPIO and FW_CONFIG support to configure BT offload audio in discrete mode for Intel Mysty Peak module on google/rex Proto2 HW. BUG=b:297125514 Test=Verified BT audio playback on google/rex Proto2. Change-Id: I560f1700f78f8b653dfcc2f26764f0ebf2652689 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77357 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-28drivers/spi/spi-generic: Fix typoElyes Haouas
'useable' -> 'usable'. Change-Id: Iad2e1ef97a5c98ffa6f33806bce5b77722e687e8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28arch/x86/cpu: Remove unnecessary parenthesesElyes Haouas
Change-Id: I157a3a700ed998b1012c85857c5fad78f60d62dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77525 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28drivers/spi/tpm: Remove space between function name and '('Elyes Haouas
Change-Id: I9804fcd9076b5a4813f099db0852a5af5ac36609 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77523 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28drivers/lenovo/wacom: Remove space between function name and '('Elyes Haouas
Change-Id: Idc38c759489976cbdf51d9c4bb950ef6d470b93a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-28drivers/intel/gma: Remove space between function name and '('Elyes Haouas
Change-Id: Id7634099e40c0bf97944be124b494c41d6335ad7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28mb/google/rex/var/karis: Remove UWBTyler Wang
According to the schematic, karis does not have a UWB, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I8a442518c2007cde883183871cef96db416850c0 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77437 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-27acpi/acpi.h: Use __packed over __attribute__((packed))Elyes Haouas
Change-Id: Iabbb637c797a361a2cbc55505002774ff4f774e1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77526 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/system76: Enable DRIVERS_GENERIC_BAYHUB_LV2 to fix LTR issueJeremy Soller
Clevo started using OZ711LV2 for the SD card reader around the time of making its TGL boards. Without the driver, CPUs don't go to power states lower than C2 due to LTR not being programmed. After enabling the driver the CPU will go to C8 while the system is idle, giving significant power savings if the system is left on battery power. There is another issue with RPL where it only goes to C6 instead of C8. This may be due to the intel_idle driver in Linux (as of 6.5-rc6 mainline and 6.4.6 stable) not supporting RPL C-states. - tgl: Started being used with the Gazelle 3060 variant - adl: Used on all models - rpl: bonw15 does not have an SD card reader Change-Id: I85c60feb6dcae7d877e70a6c6f2d3a7b3296fa0e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26soc/amd: Move psp_transfer.h out of each SOC into commonMartin Roth
The psp_transfer.h file was the same under all SoCs, and is really tied to the file common/vboot/transfer.c, not the SOC. This patch makes an include directory under vboot to put the header into and sets it to be included for all SoCs using SOC_AMD_COMMON. This makes the header file available to all platforms, so that new chips that don't use the psp_verstage don't have to make a psp_transfer.h file just to satisfy the compiler. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b9f2adee3a1d4d8d32813ec0a850344b7d717b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77303 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26vc/amd/pi: Add SPDX headers to all files that don't have themMartin Roth
License classifiers are much better about classifying files with SPDX headers than they are at classifying the general text licenses due to minor variations in the text. To help with classification, add the SPDX headers to the files. To see the current state of coreboot's licensing, see: https://coreboot.org/fossology/ Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If490f6705e7862d9ad02c925104113b355434101 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-26soc/intel/common/block/oc_wdt: Add OC watchdog common blockMichał Żygowski
Add new block for handling overclocking watchdog. The watchdog is present since Skylake or maybe even earlier so it is safe to use with most of the microarchitectures utilizing intelblocks. The patch adds the common block for initializing and feeding the watchdog. Timeout is defined statically in Kconfig and should be set high enough by the board or SoC Kconfig to let the board boot with full memory training and avoid reset loops. Full training of 128GB DDR5 DIMM memory on AlderLake takes about 5 minutes. Newer SoCs with newer memory technologies and higher RAM capacity may take more. The default has been set to 10 minutes. The patch also adds support for feeding watchdog in driverless mode, i.e. it utilizies periodic SMI to reload the timeout value and restart the watchdog timer. This is optional and selectable by Kconfig option as well. If the option is not enabled, payload and/or software must ensure to keep feeding the watchdog, otherwise the platform will reset. TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets after some time. Enable the watchdog in driverless mode and see the platform no longer resets and periodic SMI keeps feeding the watchdog. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68944 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/google/rex/var/karis: memory: Add Micron MT62F512M32D2DR-031Tyler Wang
Add new memory part in the mem_parts_used.txt and generate the SPD ID. 1. MICRON MT62F512M32D2DR-031 WT:B BUG=b:291018417 TEST=emerge-rex coreboot Change-Id: I6e05c0d41a4899ed64dbab7efd8904cd361cb50e Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77426 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/google/dedede/var/taranza: Add Wifi SAR for taranzaSheng-Liang Pan
BUG=b:297276380 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Cq-Depend: chrome-internal:6373154 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If21c7a7d329b0b1cc2c73dadb0c5b8a5b8ab27e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77399 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2023-08-26mb/google/rex/var/karis: Remove WWAN moduleTyler Wang
According to the schematic, karis does not have a WWAN module, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I653e3b4fae8a53018a6004528d1cfb3a6c883687 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77427 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26vendorcode/intel/edk2: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: If093dc08c70c521cbef96ac5b5a7a46b37169bcd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-26mb/google/rex/var/rex0: Use FW_CONFIG to select the correct SAR tableSubrata Banik
This patch changes the SAR table selection logic to use FW_CONFIG which will eventually help to support different WiFi SAR tables. TEST=Able to build and boot google/rex. Change-Id: I8f1244e3c3715bc3fbe6be1ade87817ff19836de Signed-off-by: YH Lin <yueherngl@google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77428 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26vc/intel: Remove unnecessary Kconfig optionsMartin Roth
These Kconfig options were being used basically as #define statements, which is unnecessary. This isn't a good use of Kconfig options and would be better just as #defines if actually needed. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If987b50d8ec3bb2ab99096e5e3c325e4d90a67a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-26vc/siemens: Only add the include path for hwlib when neededMartin Roth
This patch moves the line adding hwlib to the include path to the inner makefile so that it doesn't get added to every build, but only when CONFIG_USE_SIEMENS_HWILIB=y Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id668b76366a554efff560cec746e637487ebdbf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77417 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26vc/amd: Only pull in Makefiles & dirs that are neededMartin Roth
This keeps the vc/amd/pi & pi/00670F00 Makefiles from getting pulled into the build when they aren't needed. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If600c78c2ba74dd03cf493586dae037b96b7d623 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-26vc/eltan: Only pull in vc/eltan/security Makefile when enabledMartin Roth
This change tells the build to only pull vc/eltan/security/Makefile.inc into the overall build when USE_VENDORCODE_ELTAN is enabled in Kconfig. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1e462d8cc21c44716463c41cab598588cf4a22c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77418 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-26mb/google/nissa/var/yaviks: Disable SUSCLK based on fw_configWisley Chen
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage. BUG=b:296511904, b:294456574 BRANCH=firmware-nissa-15217.B TEST=build and verified by EE Change-Id: I9a6bf0ab7cc77f95e0d64f1380eac9e022fc08e4 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77383 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26soc/intel/meteorlake: Add PMC GPIO GPE group mappingCliff Huang
Add two missing mapping for GPIO GPE routes Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I3f0d13cf7c07201856e934f22efc4cc8c4ea5bf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77423 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26memrange: Honor `limit` in the last step of top-down stealingNico Huber
We only checked that the resource fits below the given `limit` in memranges_find_entry(), but then accidentally placed it at the top of the found memrange. As most resources have only a coarse limit, e.g. the 4G barrier of 32-bit space, this became only visible when artificially setting an unusual, lower limit on a resource. So, for the final placement, use `MIN(limit, range end)` instead of the range's end alone. Change-Id: I3cc62ac3d427683c00ba0ac9f991fca62e99ce44 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-25mb/google/brask/var/kuldax: Set customized_leds value for RTL8111KDavid Wu
Set customized_leds value for RTL8111K to fix led can't work. BUG=b:297093096 BRANCH=firmware-brya-14505.B TEST=Verified RTL8125 and RTL8111K led can work normally. Change-Id: Icb8624005e7e24398abdd242570970c6bfa8a09f Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77390 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/google/brya: Create nokris variantChen-Tsung Hsieh
Create the nokris variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:285838647 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_NOKRIS Change-Id: If7cb00ce978236746dfe4d097d1f20aeebb96a35 Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-25commonlib: Add PSR backup eventlog typesKrishna Prasad Bhat
Add new eventlog types to support logging of Platform Service Record (PSR) backup related messages. Eventlog entries are added on PSR data backup success/failure and also when PSR data is lost. BRANCH=None BUG=b:273207144 TEST=Verify elog event added after PSR data backup command is sent cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent ... ELOG: Event(B9) added with size 10 at 2023-07-27 06:44:49 UTC Change-Id: I01ce3f7ea24ff0fdbb7a202ec3c75973b59d4c14 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77004 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/google/rex/var/ovis: Update PWM_BUZZER GPIO configJakub Czapiga
BUG=b:271491845 TEST=Build and boot google/ovis on Rex P1 with buzzer added on GPP_B08 Change-Id: I44718ea15c93a075b6468f335a869a2cfa585273 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76049 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-25soc/intel/apollolake: Correct the logic for the legacy 8254 timerSean Rhodes
The `use_8254` should be flipped, the same as the other Intel SOCs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2d6c859c0910b796d2ae5874a560ff9974578106 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-25mb/google/nissa/var/joxer: set the DB_USB field in FW_CONFIGMark Hsieh
Joxer will have SKUs with no type-c on daughter board, add fw_config for EC control it. BUG=b:297131468 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie8098f72e29a10ebbaf3ba3b09d6a002d09fd35a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77394 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/amd/birman: Enable two USB4 xHCI controller devicesAnand Vaikar
TEST: Boot to ubuntu OS and verify that USB4 devices are listed in lspci command 00:08.3/06:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c0 00:08.3/06:00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c1 Change-Id: I6253a7694702179454bc1ca14825fd4f3b949c13 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-25soc/amd/common/include/root_complex: add IOHC MISC SMN base addressesFelix Held
The Genoa server SoC has 4 IOHC PCI roots instead of the 1 the mobile SoCs have, so add the additional 3 SMN base address definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I72dba39bff7c7a739e1dfddd80e7f22e65b5f139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77395 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25drivers/intel/fsp2/Makefile.inc: Deduplicate compression type checksFelix Singer
When LZMA compression is selected, then it's not needed to check if LZ4 compression is selected in addition. So instead of handling both cases separately, check for LZ4 only if LZMA is not selected. This applies to the cases of both, FSP-M and FSP-S. Change-Id: I4ea61a38baf4c29bf522a50a26c6b47292e67960 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77323 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-25mb/google/rex/var/karis: Add SOC_TCHSCR_INT settings to gpio tableTyler Wang
Karis use I2C touchscreen only, add SOC_TCHSCR_INT(GPP_C07) to ramstage gpio table. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ie715cfbe1984dbe38cd933312304b42ce9088806 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-25mb/google/rex/var/karis: Fix incorrect GPIO pad numbersKapil Porwal
Fix incorrect GPIO pad numbers. GPP_F19 was mistakenly used instead of GPP_F14, GPP_F15 and GPP_F16 GPIOs. BUG=none TEST=none Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I219b78a5e92d9c56799964ea88615c27aed2e92e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77401 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24Kconfig: Add option to make clang the default compilerArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ie910f654abdb8d79c686363d2bd8af4ceeea4087 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76436 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/hp/compaq_elite_8300_usdt: enable mSATARiku Viitanen
Tested with a Kingston UV500. It works the same (3Gb/s) as with vendor FW. According to smartctl -a /dev/sda: SATA Version is: SATA 3.1, 6.0 Gb/s (current: 3.0 Gb/s) Change-Id: I5c714351586e6084029ce4c54fb47cbae4d3405b Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77376 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-24mb/siemens/fa_ehl: Remove RTC RV3028C7Johannes Hahn
Delete this RTC from the configuration as fa_ehl mainboard uses a different real time clock. Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Change-Id: Ifd6b68d05a094cb4c890f1ffce62d89b771e23c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2023-08-24mb/siemens/fa_ehl: Remove TPMJohannes Hahn
The mainboard currently does not make use of a dedicated TPM. Although it has one assembled. This TPM is not connected via LPC hence it is turned off in the devicetree. Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Change-Id: I96cc38c3812d76d654339ad5b2b7f88fd1327779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77351 Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-08-24mb/siemens/fa_ehl: Remove NC_FPGAJohannes Hahn
fa_ehl mainboard does not make use of the SIEMENS NC_FPGA as it is not placed on this board. Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Change-Id: I5f1f796e4339ba37d461d6818c2bb6ba028b89c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-08-24mb/google/dedede/var/boxy: Enable 100M mode blink in RTL8111H LAN LED configStanley Wu
Enable bit 9 for 100M mode green LED blink. Reference: - RTL8111H-CG Datasheet 1.92 section 7.2 for customizable led configuration BUG=b:293983804 TEST=emerge-dedede coreboot and verify LAN LED behavior Change-Id: Ice5686affcc014a2dfd35b7f579c8eaa38c2d3fe Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-24mb/google/nissa/var/yaviks: rename DB_NONE to DB_1AWisley Chen
Yaviks doesn't have none DB sku, and rename to DB_1A for yahiko. BUG=b:294928078, b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Icb952c0716d446d5feb5580f357120a27193284e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77384 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24soc/intel/metorlake: Fix PMC GPIO group assignmentCliff Huang
Those values need to match with the ones defined in PMC PWRM GPIO CFG register. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I8e84df83caab794e2fe7186e89e78343c2b55fd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mainboard/siemens/fa_ehl: Add new mainboard based on mc_ehl2Johannes Hahn
Add a new mainboard called fa_ehl which is based on Siemens's 'mc_ehl2'. This commit simply copies the mainboard directory and adjusts the naming to match the new board's name. Moreover a variants scheme is provided for possible alternative implementations. Follow-up commits will introduce the needed changes for the new mainboard. Change-Id: Ia389c8812d14db8b663547e6336e900becbc8be6 Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76444 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2023-08-24acpi: Add function to add ARM PL011 to ACPI DBG2Arthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3c3f7f579ec0ec4fdb72e1f6b785026daab17bac Reviewed-on: https://review.coreboot.org/c/coreboot/+/76297 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24soc/intel/apollolake: Move the PMC definitions to pmc.h fileMichał Żygowski
Add a pmc.h file, which is needed for OC watchdog compilation. The PMC definitions from pm.h are moved to pmc.h. TEST=Build UP Squared and Intel GLKRVP sucessfully. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I2726aaae1ce60d15a3944dadcf793def2dcb3a1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-08-24soc/mediatek/mt8188: Remove GPT timer initYidi Lin
GPT timer init is no longer needed after DRAM blob is switching to ARM arch timer. BUG=b:229800119 TEST=boot to kernel Change-Id: Iec1f93c96e791220feed4225959ef15c074ba577 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77388 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/vell: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I62103563ec49769cd842fedf8c2c55118c55aa14 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/taniks: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I12fa83987869b9a52940a49e9f7897d62abf59ff Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/taeko: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I07e85f28c4f260d04317ec594e162db20f3d4ddd Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/volmar: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ie7982d1001c4a65322b4e6fdbd70b20c8eee6f0e Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/primus: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I78eee4c5f11b06fbc104182a4313c20be91b821b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76905 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/osiris: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I6157894b96da2e9faed229a1f18c0c0b7c60897b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/omnigul: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ie0304ea4343361ff0395c7204ebb76bffb5a6d97 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/mithrax: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Icdb8e9a20ab536f80fa7358472cca01996faf447 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/rex/var/karis: Disable GSPI0Tyler Wang
According to the schematic, karis does not have a SPI touchscreen, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I55eb9e3cebe426fcd023789831ce64a18d075d69 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-24mb/google/brya/var/marasov: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ie2c089c0418f76ac7c8ce2e531dbbc91c66f34a0 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76901 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/kano: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I15888b4e5bd46c98e0864eaa6850e1a24b22fe65 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76900 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/gimble: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ief27cd6e32780683c53a88d73194c6d82c6c212b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/felwinter: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I7be4a47ea2a8cb2b6f4a2d633252eec523807da6 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/crota: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ic5343de88f5f089c9ec4a992f5a6383c08641568 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76897 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/banshee: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Iced1061bab224d918fd5f0525423ac6858e1799b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24soc/nvidia: Fix incorrect SPDX licenseMartin Roth
The SPDX license header for this file did not match the license text in the file. Update the SPDX header and remove the license text. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ifc0db79e43df6d14b80b0ad3061fe42de17ed90f Reviewed-on: https://review.coreboot.org/c/coreboot/+/77379 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-24soc/intel/jasperlake: Use boolean type where applicableMichael Strosche
Change-Id: If3c2e5bd9ee7e0f77d0c39ffe2ca9ad17b77d9bd Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-23mb/amd/mayan: Enable the DT and M.2 SSD1 PCIE slotsAnand Vaikar
Program the EC GPIOs to enable the DT or M.2 SSD1 PCIe slots based on the config option selected. Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-23soc/intel/xeon/spr: Improve RMT configurationNaresh Solanki
Set EnforceDdrMemoryFreqPor to 0 for RMT builds. This is needed for proper functioning when EnforcePopulationPor is set to 1. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: Icf4fe01ac9b546830334717dbfa53782d2a85ba1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-23soc/mediatek/mt8188: Simplify pmif init flowSen Chu
Based on "MediaTek_EFUSE_MT8188_Confidential A_Technical Doc.docx", MT8188G used in ChromeOS project does not support clock hardware monitor. Thus, we can simplify the initialization flow by removing the hardware default value check. BUG=b:292866009 TEST=emerge-geralt coreboot BRANCH=none Change-Id: I07cd753f153da5b0aea1518a04a818214f986aeb Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77334 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-23mb/google/brya: Create quandiso variantRobert Chen
Create the quandiso variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_QUANDISO Change-Id: I846c39260e2db504d7bec6e81a8317b6824c17f4 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-23mb/google/rex/var/karis: Remove WWAN temperature sensorTyler Wang
According to the schematic, karis does not have a WWAN temperature sensor, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ic82c6cfec067faa37d452bed5c4977402a2139a5 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77284 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-23mb/google/dedede/var/pirika: Add USB2 PHY parameters for Type-A/Type-CDaniel_Peng
This change are added fine-tuned USB2 PHY parameters to improve the USB2 eye diagram result. BUG=b:296493887 BRANCH=firmware-dedede-13606.B TEST=Local build bios successfully. And verified the USB2 eye diagram test result. Change-Id: I915fe689883267901e8faba28632345d8c227c28 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77359 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-23mb/google/brask/var/constitution: Separate wifi sar tableMorris Hsu
Separate constitution and intrepid wifi sar table in variant.c BUG=b:291859402 BRANCH=firmware-brya-14505.B TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I0f89b3d5f5252a2b55bad4d91ad4ab9ec7519c50 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77242 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-22mb/google/brya/var/bb/brask: enable HDMI gpios earlyNick Vaccaro
Add some HDMI-related gpios that are needed for early sign-of-life to the early_graphics_gpio_table array so that SOL will show up on HDMI ports. BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage` and verify it builds without error. Change-Id: Ic36a636e68c2d457f40329a2e9c69dab5bbba41f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77353 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-22soc/qualcomm: Add missing newlines for logsYu-Ping Wu
Change-Id: Ifd2e0043122946211aceb5ff88db0314de720fb9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77336 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21soc: Remove SOC_SPECIFIC_OPTIONSElyes Haouas
Move specific options under the boolean and remove dummy SOC_SPECIFIC_OPTIONS. Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-21mb/google/rex/var/karis: Remove world facing cameraTyler Wang
According to the schematic, karis does not have a WFC. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I9b4ecf2e96c77c131a60e48614d792370dd33423 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-21ec/google/wilco/superio: Adjust PS2K HID/CID for Windows driversMatt DeVillier
Allows coolstar's Windows overlay drivers to attach, while not affecting operation under Linux or ChromeOS TEST=build/boot Win11, Linux 6.x on google/drallion Change-Id: I30ab2e9da00743c4d7086aac94652be46040f36d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77305 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21ec/google/wilco/acpi: Read message when notifying UCSICoolStar
Allows the EC to be properly notified of type-c events like charger wattage too low (eg), TEST=build/boot Win11, Linux 6.x on google/drallion Change-Id: I7a4130cf6f8c24e3f91e327adf1f3e563322c0af Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77282 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21ec/google/wilco: Correct scope of UCSI ACPI deviceCoolStar
Set the USCI device scope to _SB and set HID to USBC000 so Windows driver attaches. This matches the ACPI used by the non-Chromebook version of the Dell Latittude 7410 (which uses the same EC). TEST=build/boot Win11 on google/drallion Change-Id: If482fa4a4856c7bc085795bc72b35ebefe2f15c4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77281 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21ec/google/wilco/acpi: Unhide GOOG000C ACPI deviceMatt DeVillier
Allows coolstar's Windows drivers to attach. TEST=build/boot Win11 on google/drallion Change-Id: Idd339811563cd2cdfc4cc31bc5660a62f4e36a66 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-21ec/google/wilco/acpi/dptf: Fix mutex synclevelMatt DeVillier
Both Windows and MacOS get cranky if the Mutex synclevel is non-zero, aborting any Acquire() call with Mutex param that has a non-zero synclevel. TEST=build/boot Win11 on google/drallion, verify DPTF driver loaded and functional. Change-Id: Ie77e9ed04658b508b2063ae219afcdc0ac465c58 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77279 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21soc/intel/alderlake: add GPIO definitions for RPL PCHTim Crawford
The RPL PCH uses a different ACPI Device ID than ADL PCH. Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835) Change-Id: I03f47a43ff985213ad617e834db7f974f687d877 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21mb/msi/ms7e06: Add support for MSI PRO Z790-P DDR4/DDR5 (WIFI)Michał Żygowski
TEST=Boot Ubuntu 22.04 on MSI PRO Z790-P (DDR5 variant) with Intel Core i5-13600K using UEFI Payload. Change-Id: Id2c77621d24bb097b930342eb1961270854d5f68 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76325 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21vc/intel/fsp2_0: Add a copy of ADL-S IOT FSP MemInfoHob.h for RPL-S IOTMichał Żygowski
Similar situation happened last year when IoT FSP for ADL-S came out before the Client FSP variant: https://github.com/intel/FSP/issues/83 It seems IoT FSP publishes the MemInfoHob.h file much later due to legal reasons. Hack the missing file to get the builds using RPL-S IoT FSP from repo working properly. This change could be merged, subject for later revert (when the header file is published). Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21soc/intel/alderlake: Guard PchPcie{Clock,Power}Gating on RPL FSPMichał Żygowski
PchPcieClockGating and PchPciePowerGating UPDs are not yet available in RPL-S IOT FSP. It also looks like those UPDs are not generally available in all public RaptorLake FSP headers yet, so guard it against SOC_INTEL_RAPTORLAKE to avoid build errors. Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-08-21soc/intel/broadwell/pch/Kconfig: Remove dummy PCH_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I21db0474157ba20cdf3eaef086aaf29fde29d6c5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76701 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21mb/google/skyrim/var/crystaldrift: drop commented out line in DTMatt DeVillier
Line is a duplicate, commented out. Drop it as it serves no purpose. Change-Id: Id35bdea0915ca47cac4f38ede6ccbf2f2fb59f47 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77304 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21device/dram: add DDR4 RCD I2C access functionsKrystian Hebel
Registering Clock Driver (RCD) is responsible for driving address and control nets on RDIMM and LRDIMM applications. Its operation is configurable by a set of Register Control Words (RCWs). There are two ways of accessing RCWs: in-band on the memory channel as MRS commands ("MR7") or through I2C. Access through I2C is generic, while MRS commands are passed to memory controller registers in an implementation-specific way. See JESD82-31 JEDEC standard for full details. Change-Id: Ie4e6cfaeae16aba1853b33d527eddebadfbd3887 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-21soc/intel/apollolake/chip.h: Use boolean type where applicableMichael Strosche
Change-Id: I6f2dc0fcc4392f77b8011221c0cf22af5da45172 Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 02:58:38 +0000