diff options
| author | Naresh Solanki <Naresh.Solanki@9elements.com> | 2023-08-21 13:14:27 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-23 12:14:09 +0000 |
| commit | 40c740584bd86a535924c0b0337f9ef094f3d394 (patch) | |
| tree | 1c573c9a033555a885dd14126fa6dceebe6f2aa0 /src | |
| parent | 8cc8b3c14b07d03e4c702510b21d7e311049798e (diff) | |
soc/intel/xeon/spr: Improve RMT configuration
Set EnforceDdrMemoryFreqPor to 0 for RMT builds. This is needed
for proper functioning when EnforcePopulationPor is set to 1.
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: Icf4fe01ac9b546830334717dbfa53782d2a85ba1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 57f12c5d4d..8abac91de5 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -278,6 +278,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmConfig.serialDebugMsgLvl = 0x3; mupd->FspmConfig.AllowedSocketsInParallel = 0x1; mupd->FspmConfig.EnforcePopulationPor = 0x1; + mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; } } |