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authorSergii Dmytruk <sergii.dmytruk@3mdeb.com>2023-08-27 17:53:48 +0300
committerFelix Held <felix-coreboot@felixheld.de>2023-08-28 17:47:55 +0000
commit55d3a54d104a7c87e230a5df494d21568e0f5805 (patch)
tree3ac3989084aa854226660c7d2c4138e76d96d8f0 /src
parent37ccd23155038463cbfc803c3587a54e2540a91f (diff)
src/device/dram/Makefile.inc: specify one file per line
A trivial follow-up on CB:67060. This makes contents of the file look a bit less regular, but more like the rest Makefile.inc in the code base. Change-Id: I772d37825e4b59cf927637dc39bfb3ee06115860 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77533 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/device/dram/Makefile.inc6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc
index 64f1dba801..7772db2de5 100644
--- a/src/device/dram/Makefile.inc
+++ b/src/device/dram/Makefile.inc
@@ -1,7 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only
romstage-y += ddr_common.c
-ramstage-y += ddr_common.c spd.c
+ramstage-y += ddr_common.c
+ramstage-y += spd.c
romstage-$(CONFIG_USE_DDR5) += ddr5.c
ramstage-$(CONFIG_USE_DDR5) += ddr5.c
@@ -9,7 +10,8 @@ ramstage-$(CONFIG_USE_DDR5) += ddr5.c
romstage-$(CONFIG_USE_LPDDR4) += lpddr4.c
ramstage-$(CONFIG_USE_LPDDR4) += lpddr4.c
-romstage-$(CONFIG_USE_DDR4) += ddr4.c rcd.c
+romstage-$(CONFIG_USE_DDR4) += ddr4.c
+romstage-$(CONFIG_USE_DDR4) += rcd.c
ramstage-$(CONFIG_USE_DDR4) += ddr4.c
romstage-$(CONFIG_USE_DDR3) += ddr3.c