| Age | Commit message (Collapse) | Author |
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1. Add DB_1C_LTE 4 on DB_USB fw_config.
2. Implement WWAN power sequencing.
3. Disable LTE-related GPIOs based on fw_config.
4. Add I2C SX9324 (P-sensor) support.
Refer Schematic file: CA31AC_R10_MB_SUB_240903A_P.pdf
BUG=b:374666995
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Confirm the device node i2c-STH9324:00 created correctly,
and command for # i2cdump -f -y 11 0x28 is workable.
Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84925
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Irq2axi translates wire-based interrupt into message signal interrupt.
Since MT8196 uses legacy wire-based interrupt, this feature needs to be
disabled. If the interrupt is not handled, it will cause the system fail
to boot.
TEST=Build pass, check irq2axi_disable log and the interrupt can be
correctly handled by checking /proc/interrupts.
BUG=b:317009620
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84896
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The boot time is improved by 58ms in bootblock. (78ms -> 20m)
BUG=b:361729697
TEST=check cbmem
Change-Id: I27ce378ba8e3744cfb3921835e34b32bbba991cb
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84897
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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De-assert PERST# at romstage to reduce the waiting time in ramstage.
BUG=b:361728592
TEST=The boot time improves 62ms
Change-Id: I2cd5cd59e7513b6e4036c3e8013a3c7322d2f787
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Looking at Intel document 759603 revision 001, Alder Lake N only has 5
PCIe clock outputs and clock request pins. I only have the version 2 of
this board which has a significantly different USB port configuration to
version 1, but there the Ethernet controller on RP 11 and the E key m.2
slot on RP 12 share the last PCIe clock output. The on-board TUBF0304
clock buffer chip takes the clock output form the last PCH PCIe clock
generator output and drives the clock inputs of both the last Ethernet
chip and the E key m.2 slot. Since the last clock output is always
active, since RP 11 has the PCIE_RP_CLK_REQ_UNUSED flag set, using the
non-existent clock output and request for RP 12 didn't break things.
ASPM L0s might still work though, since that one doesn't involve
switching off the PCIe reference clock, but haven't tested that yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I103f7c3fe0b806f5c0a5202b8221f522a4b1c378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83911
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It may come with 8th or 9th Gen CPUs. i5-8500T has been tested here.
Works:
- Serial adapter from daughter board (COM1 connector)
- USB ports front and back
- USB-C port (charging, data)
- HDMI
- Ethernet
- SATA
- NVMe
- internal speaker
- TPM2.0
- PCIe x8 port (x8 riser tested, x4 not)
Does not work:
- front audio jacks
Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80609
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the functions that call 'spi_controller_available' end up checking
if the SPI controller is busy, refactor the function into
'spi_controller_busy' to simplify the logic on the caller's side. Also
move printing of the notice that the SPI controller is busy to
'spi_controller_busy' to not have that duplicated in caller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibc21ab6eacf07c4adffdb4658142c2f9dfcbf2a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84920
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the RPMC-related functions will only need the spi_flash struct,
but not the region_device struct of the store region corresponding to
the 'target_nv_id', factor out 'get_flash_device' from
'find_psp_spi_flash_device_region'.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia99d3454df2c1c4182c193da7de1bbb4eef18313
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84905
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral
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Disable UFS controllers during romstage initialization only when
resuming from S5 (full power off).
On warm reboot, the UFS controllers are already disabled by the
previous boot cycle, so disabling them again is unnecessary.
TEST=Able to ensure UFS controller is already disabled in warm reboot
path and not causing any problem during S0ix cycle test.
Change-Id: Ia27d2156a002cef032d5f57d212cf4eb520b3bdf
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
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Disable the `FSP_UGOP_EARLY_SIGN_OF_LIFE` option (eSOL) for the
Ovis baseboard.
eSOL currently only supports display output over eDP and HDMI.
Ovis/Deku exclusively use Type-C for display, and eSOL cannot render
output over Type-C during early boot because it depends on Type-C
firmware loaded in a later stage.
TEST=Able to build and boot google/deku.
Change-Id: I5ddbd340f667b1631a42d130a793f0b1831aa0ba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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1. Extend 1 bit [34] for the TOUCHSCREEN_SOURCE.
SSFC range for TOUCHSCREEN_SOURCE is bit[32:34].
2. Touchscreen panel: MUTTO A153728S1Y,
and set TOUCHSCREEN_ILIT2901 to value "4"
3. Datasheet: #153728S1V1.0 SPEC_20240923.pdf
BUG=b:375986645
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Confirm command evtest and touchscreen function is workable.
Change-Id: I6e13c948edca5a894e1a00a1954f0f88c4a079cf
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84894
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add API to get Power Delivery (PD) Chip info which includes vendor ID,
product ID and firmware version(if any).
BUG=None
TEST=Build Brox BIOS image and boot to OS.
Change-Id: I4cc4493ac64d44076877fee633488c95cd09807e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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commit 6c83a71b0a80 ("skl mainboards/dt: Move usb{2,3}_ports settings
into XHCI device scope") not only moved the USB port definitions under
the XHCI device reference, but also combined multiple register
definitions. In doing so, it broke the inheritance from the baseboard,
since the variant overridetree registers now replaced the entire
usb2_ports/usb3_ports structs, rather than replacing individual array
elements therein. This resulted in any USB ports inherited from the
baseboard and not overridden by the variant being non-functional as they
were not included in the resulting combined devicetree.
To fix this, return to overriding individual array elements in the
usb2/3_ports structs.
TEST=build/boot google/fizz/var/karma. Verify all USB ports present and
functional. Verify mainboard/static.c in built shows all ports.
Change-Id: I0e80bf4949a857c21d44537eb720a7a8a7db2f80
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84955
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures the ESPI_SOC_ALERT_L GPIO pad on fatcat as
NC to enable S0ix low power entry.
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84957
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
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Package C-state auto demotion feature allows hardware to determine lower
C-state as per platform policy. Since platform sets performance policy
to balanced from hardware, auto demotion can be disabled without
performance impact.
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: I01f2cb8ac1093ae98cc076e35ad1924baa53aa59
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch adds is_battery_present() to check if the
battery is physically present
BUG=b:335046538,b:329722827
TEST=Build Brox and check is_battery_present
returns the correct battery status.
Change-Id: Ie49ed8f6d8b0fa59ec0e7b06efea9cac4d253957
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83735
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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1. Modify the I2C frequency of the touchpad between 380 Khz and
400 Khz to meet the spec.
2. Increase clk the time of high (TH) to greater than 600ns.
Before:
I2C0 - 420KHz
TH - 557ns
After:
I2C0 - 398Khz
TH - 630ns
BUG=b:351968527
TEST=Check that the wave form meets the spec.
Change-Id: I5ccaa3a669e18319311de14833966410c7adf40d
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84898
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Add Micron part MT62F2G32D4DS-020 WT:F only for Francka.
DRAM Part Name ID to assign
MT62F2G32D4DS-020 WT:F 0 (0000)
BUG=b:373394046
TEST=emerge-fatcat coreboot
Change-Id: I2de56c8c7a028edefbd3dc53f8b1e26dee3286f7
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84781
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The size of the inner array of the 2-dimensional array pad_funcs should
be 4 instead of SPI_BUS_NUMBER (6). This bug leads to two extra
gpio_set_mode() calls with unexpected GPIOs.
Inspecting spi.o, the data immediately after the .rodata.pad_funcs
section is .rodata.spi_ctrlr_bus_map, with the following data:
00000428 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00
00000438 00 00 00 00 00 00 00 00 ...
This is equivalent to the following calls:
gpio_set_mode(GPIO(GPIO05), 0);
gpio_set_mode(GPIO(GPIO00), 0);
The second call is already included in the pad_funcs array, so the first
call is the only practical impact of this bug.
Change-Id: I9c44f09b3cdadbbf039b95efca7144f213672092
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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If the mainboard expects upcoming reset, then skip the reset after
disabling UFS. This will reduce the number of resets during firmware
update.
BUG=b:375444631
TEST=Build Brox BIOS image and boot to OS. Perform a firmware update and
confirm that the number of reset is reduced by 2 resets.
Change-Id: I4399555302ec23a76f89f406f437f311eea0ef99
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84935
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Update device tree to support speaker o/p on MAX98357A AIC.
BUG=b:357011633
TEST=build coreboot image and test audio playback on Google/Fatcat board.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I20de87f673e947f0e2332b818ebca01c0fa5e200
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84888
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP
headers for FSP as banshee is using a converged firmware image.
This effort also helps to save banshee boot time by 80-100ms as
RPL FSP is better optimized.
Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which
saves 10ms of the boot time.
BUG=b:358254132
TEST=Able to build and boot google/banshee.
cold boot time w/o this CL
```
Total Time: 1,399,888
```
cold boot time w/ this CL
```
Total Time: 1,295,334
```
Change-Id: If22e07a4c1b35fe1d060ca523743c6c503937287
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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From power team's recommendation, increase the VccIn Aux Imon IccMax
to 30A to meet HW settings.
BUG=b:376306118
TEST=Build firmware and check the value is changing as expected.
Paste the firmware log.
[SPEW ] VccInAuxImonIccImax= 0x78
[SPEW ] (MAILBOX) VccInAuxImonIccImax = 120 (1/4 Amp)
[INFO ] Override VccInAuxImonIccImax = 120
Change-Id: I71020c2f631cb517a52d4bb65e35277eb731ced7
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. Right now we simply
wait for 100ms in ramstage for that.
To speed up the boot time, pre-initialize PCIe by asserting PERST#
earlier in the bootblock stage. The pre-initialization time is stored
in the early init data region, so that the PCIe initialization in
ramstage could make sure the required 100ms delay is still reached.
This pre-initialization will speed up the boot time by 100ms on rauru.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I2b84c25ae3ea9069fd38fa6b20b8235a7fc3a484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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We want to configure different VBT timings for panels of different sizes
and distinguish them through SSFC. We select the reserved bit 6 of SSFC
as the flag bit. When using a 12-inch panel, set this bit to 0; when
using an 11-inch panel, set this bit to 1.
Without splitting, the platform_BootPerf test will fail.
BUG=b:374428465
TEST=
1. can match VBT with SSFC
-When SSFC is set to 0x40:
$ cat /sys/firmware/log | grep vbt
Bit 6 of SSFC is 1, use vbt-teliks_panel_11_inch.bin
CBFS: Found 'vbt-teliks_panel_11_inch.bin' @0x1c6140 size 0x50f in mcache @0x76adda14
-When SSFC is set to 0x0:
$ cat /sys/firmware/log | grep vbt
Bit 6 of SSFC is 0, use vbt-teliks.bin
CBFS: Found 'vbt-teliks.bin' @0x1c5bc0 size 0x50e in mcache @0x76add9b0
2. can pass platform_BootPerf test
The platform_BootPerf time measured for all SKUs is less than 1.55s.
Change-Id: Ia8fb45aede5ead4826d983760506c366a70643ee
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84871
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This commit adjusts the EC host command range for the Fatcat board to
0x800-0x807 & 0x200-0x20f.
This change is necessary because the microchip EC used on the Fatcat
board has a smaller host command range than the ITE/Nuvoton ECs used
on other Fatcat variants.
The `gen1_dec` register in the devicetree is updated to reflect this
change.
As per boot log, the `gen1_dec` aka offset 0x84, base address is 800
and size is 8 bytes.
AP FW Boot log:
[SPEW] PCI: 00:00:1f.0 resource base 800 size 8 align 0 gran 0 limit 0 flags c0000100 index 84
BUG=b:376207365
TEST=Able to build and boot google/fatcat w/o any error.
without this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
[ERROR] LPC: Cannot open IO window: 800 size 8
[ERROR] No more IO windows
with this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
Change-Id: Ifcee533341fa583d841a4b564f25831c6d04e951
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84919
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
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This patch implements the `save_dimm_info()` API to populate and pass
DRAM-related information to the next stage. This information
is used to generate the SMBIOS memory table, providing details about
installed DIMMs.
This addresses the issue where SMBIOS lacked detailed DIMM information.
Verified that `dmidecode` correctly dumps the DIMM information from the
SMBIOS table after this change.
BUG=b:376103463
TEST=Built and booted successfully. Verified DIMM info in SMBIOS using
`dmidecode`.
> dmidecode -t 17
```
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x000B, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2 GB
Form Factor: Row Of Chips
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: LPDDR5
Type Detail: Unknown Synchronous
Speed: 6400 MT/s
Manufacturer: Hynix
Serial Number: 00000000
Asset Tag: Channel-0-DIMM-0-AssetTag
Part Number: H58G56BK7BX068
Rank: 1
Configured Memory Speed: 6400 MT/s
Minimum Voltage: 0.5 V
Maximum Voltage: 0.5 V
Configured Voltage: 0.5 V
...
...
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2 GB
Form Factor: Row Of Chips
Set: None
Locator: Channel-3-DIMM-0
Bank Locator: BANK 0
Type: LPDDR5
Type Detail: Unknown Synchronous
Speed: 6400 MT/s
Manufacturer: Hynix
Serial Number: 00000000
Asset Tag: Channel-3-DIMM-0-AssetTag
Part Number: H58G56BK7BX068
Rank: 1
Configured Memory Speed: 6400 MT/s
Minimum Voltage: 0.5 V
Maximum Voltage: 0.5 V
Configured Voltage: 0.5 V
```
Change-Id: I3b942610272de401589ee0463de9cd0985974774
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This patch adds ACPI names for the following devices:
- THC0 (PCI: 00:10.0)
- THC1 (PCI: 00:10.1)
- SRAM (PCI: 00:14.2)
- FSPI (PCI: 00:1f.5)
TEST=Able to build and boot google/fatcat without any error.
w/o this patch:
[ERROR] Missing ACPI Name for PCI: 00:10.0
[ERROR] Missing ACPI Name for PCI: 00:10.1
[ERROR] Missing ACPI Name for PCI: 00:14.2
[ERROR] Missing ACPI Name for PCI: 00:1f.5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I474089607522a4bd13375cc34b8f8645ca3663d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84910
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
This change sets the SMBUS device to min sleep state D0 in the ACPI
sleep state table.
TEST=Able to build and boot google/fatcat.
w/o this patch:
[WARN ] Unknown min d_state for PCI: 00:1f.4
w/ this patch:
No Error or Warning.
Change-Id: If84d2ee8abfef34f6411e01e6c37d4e2008a3666
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84909
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This commit defines the EC_SYNC_IRQ and GPIO_PCH_WP macros for
different Fatcat variants.
The EC_SYNC_IRQ macro is used for tight timestamps and wake support,
while the GPIO_PCH_WP macro is used for the WP signal to the PCH.
These macros were previously undefined or incorrectly defined for some
variants. This commit fixes these issues and ensures that the macros
are defined correctly for all variants.
Specifically, this commit:
- Defines EC_SYNC_IRQ and GPIO_PCH_WP for Fatcat Nuvo and Fatcat ITE.
- Defines EC_SYNC_IRQ as 0 (not connected) for Fatcat.
- Defines GPIO_PCH_WP as GPP_D02 for Fatcat.
- Leaves EC_SYNC_IRQ and GPIO_PCH_WP as 0 (TODO) for Francka.
TEST=Able to build and boot google/fatcat.
w/o this patch:
```
cros_ec_lpcs GOOG0004:00: couldn't retrieve IRQ number (-22)
cros_ec_lpcs GOOG0004:00: probe with driver cros_ec_lpcs failed with error -22
```
w/ this patch:
```
cros_ec_lpcs GOOG0004:00: Chrome EC device registered
```
Change-Id: I9bd248496f08869c08cf6daafeed6584d0b166b7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
|
|
This patch updates the flash map layout to guarantee that the
RW_SECTION_B section starts at the 16MB boundary.
Additionally, fix typo in flash descriptor comment, where comment
incorrectly referred to "MTL" instead of "PTL".
TEST=Successfully builds google/fatcat.
Change-Id: Ia6dba611fba50f9694a75670d954a4630cde4d70
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84899
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This to fix the error when using C23:
cannot cast an object of type 'nullptr_t' to 'uintptr_t' (aka 'unsigned long')
return (uintptr_t)NULL;
^
Change-Id: Ibdc8794513a508fc61a5046692f854183c36b781
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
|
|
Use the resource size to determine Vtd BAR size and drop the code to
calculate the Vtd BAR size.
While on it do not truncate the resource address to 32-bit, since the
DMAR entry is 64-bit wide anyway.
TEST: Booted on intel/archercity_crb
Change-Id: Ibaadc25c44345ba2eb9e6f75989d32b43d00d7a5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
Align DSDT names with SSDT naming scheme, as provided by
iio_domain_set_acpi_name() and hide unused devices by implementing
the _STA method as done on newer platforms.
Change-Id: I8488907f28a78a6f71046dba54ba9cbd4b0652eb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
Get rid of some helper functions by properly using a pci_driver.
Configure SAD if necessary and lock SAD if necessary in the newly added
SAD PCI driver. This allows to drop lock_pam0123(), unlock_pam_regions()
and socket0_get_ubox_busno().
- Fixes SAD instance on secondary sockets not decoding the C-F segments
as DRAM, which would prevent those sockets to access the ACPI/SMBIOS
table anchor
- Adds PCI multi segment support
(SKX and CPX only, other were working properly already)
- Moves locking of PAM0123_CSR and PAM456_CSR from SoC to driver code
Change-Id: I167b6ce48631fe3f97359ee33704f52ca854dbd1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84794
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set characteristics 1 based on slot type and scan PCI capabilities
to update the characteristics 2 field in SMBIOS type 9 accordingly.
Change-Id: If96e0381b10c25cf73b3797a0f02a40dc933993e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
|
|
Add a helper method to read the PME capability.
Will be used in the following commit.
Change-Id: Id1fdc98c9ce86d3ddf8056bb609afc58008cf2e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84793
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add the code to request the provisioning of the RPMC root key from the
PSP. When RPMC hasn't already been provisioned enabled and the PSP has
detected a SPI flash chip that both supports RPMC and has monotonic
counters that can still be provisioned, we send the PSP mailbox command
to request the RPMC provisioning and then reset the system, so the PSP
can do the actual provisioning.
TEST=On an out of tree AMD reference board using the Cezanne SoC code,
provisioning RPMC works as expected when selecting the corresponding
PERFORM_RPMC_PROVISIONING Kconfig option:
1st boot to initiate the RPMC provisioning:
[DEBUG] PSP: Querying PSP capabilities...OK
[DEBUG] PSP: Querying HSTI state...OK
[SPEW ] RPMC isn't provisioned
[SPEW ] SPI flash supports RPMC
[SPEW ] RPMC revision 0
[SPEW ] PSP NVRAM isn't healthy
[SPEW ] PSP NVRAM is using RPMC protection
[SPEW ] SPI flash RPMC counter 0 can still be provisioned
[SPEW ] SPI flash RPMC counter 1 can still be provisioned
[SPEW ] SPI flash RPMC counter 2 can still be provisioned
[SPEW ] SPI flash RPMC counter 3 can still be provisioned
[SPEW ] SPI flash RPMC counter 0 is in use
[SPEW ] SPI flash RPMC counter 1 is not in use
[SPEW ] SPI flash RPMC counter 2 is not in use
[SPEW ] SPI flash RPMC counter 3 is not in use
[SPEW ] SoC RPMC slot 0 can still be provisioned
[SPEW ] SoC RPMC slot 1 can still be provisioned
[SPEW ] SoC RPMC slot 2 can still be provisioned
[SPEW ] SoC RPMC slot 3 can still be provisioned
[DEBUG] RPMC: perform fusing using RPMC counter address 0
[DEBUG] OK
[NOTE ] RPMC: Rebooting
[INFO ] warm_reset() called!
2nd boot after the provisioning is done:
[DEBUG] PSP: Querying PSP capabilities...OK
[DEBUG] PSP: Querying HSTI state...OK
[SPEW ] RPMC is provisioned
[SPEW ] SPI flash supports RPMC
[SPEW ] RPMC revision 0
[SPEW ] PSP NVRAM isn't healthy
[SPEW ] PSP NVRAM is using RPMC protection
[SPEW ] SPI flash RPMC counter 0 has already been provisioned
[SPEW ] SPI flash RPMC counter 1 can still be provisioned
[SPEW ] SPI flash RPMC counter 2 can still be provisioned
[SPEW ] SPI flash RPMC counter 3 can still be provisioned
[SPEW ] SPI flash RPMC counter 0 is in use
[SPEW ] SPI flash RPMC counter 1 is not in use
[SPEW ] SPI flash RPMC counter 2 is not in use
[SPEW ] SPI flash RPMC counter 3 is not in use
[SPEW ] SoC RPMC slot 0 has already been provisioned
[SPEW ] SoC RPMC slot 1 can still be provisioned
[SPEW ] SoC RPMC slot 2 can still be provisioned
[SPEW ] SoC RPMC slot 3 can still be provisioned
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7760c0bf7618ca60ef160329d0110ac8109032a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84707
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the code to query the status of the replay-protected monotonic
counter (RPMC) infrastructure from the PSP and display it in a decoded
form.
Certain SPI flash chips have 4 32-bit monotonic counters in addition to
the actual flash storage. During the RPMC root key provisioning process,
which is done at the end of manufacturing, a 256 bit RPMC root key is
generated by the PSP and programmed into both SoC fuses and the RPMC SPI
flash chip. After that, commands to read or increment the monotonic
counters can be sent to the SPI flash which are protected by a
HMAC-SHA-256 signature using a key derived from the provisioned RPMC
root key.
The code to do the RPMC provisioning is added in a follow-up patch.
TEST=On an out of tree AMD reference board using the Cezanne SoC code
and with the SOC_AMD_COMMON_BLOCK_PSP_RPMC Kconfig option selected, the
newly added code prints this on the console after the provisioning was
done:
[DEBUG] PSP: Querying PSP capabilities...OK
[DEBUG] PSP: Querying HSTI state...OK
[SPEW ] RPMC is provisioned
[SPEW ] SPI flash supports RPMC
[SPEW ] RPMC revision 0
[SPEW ] PSP NVRAM isn't healthy
[SPEW ] PSP NVRAM is using RPMC protection
[SPEW ] SPI flash RPMC counter 0 has already been provisioned
[SPEW ] SPI flash RPMC counter 1 can still be provisioned
[SPEW ] SPI flash RPMC counter 2 can still be provisioned
[SPEW ] SPI flash RPMC counter 3 can still be provisioned
[SPEW ] SPI flash RPMC counter 0 is in use
[SPEW ] SPI flash RPMC counter 1 is not in use
[SPEW ] SPI flash RPMC counter 2 is not in use
[SPEW ] SPI flash RPMC counter 3 is not in use
[SPEW ] SoC RPMC slot 0 has already been provisioned
[SPEW ] SoC RPMC slot 1 can still be provisioned
[SPEW ] SoC RPMC slot 2 can still be provisioned
[SPEW ] SoC RPMC slot 3 can still be provisioned
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I498eec58189da710b725ac6575c68ba7ab0bcc43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84706
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The functions psp_get_ftpm_capabilties, psp_get_hsti_state, and
psp_get_psp_capabilities which were added in commit 5e7ab1a23346
("soc/amd/common/psp: add helper functions to retrieve capability bits")
have a bug in the 'cmd_status' error handling logic. In case of an
error, 'cmd_status' is non-zero, while the check somehow expected the
opposite. Fix the bug by returning an error if 'cmd_status' is non-zero.
Change-Id: Iafcd185ec4a8a4c0e463b0ac5bac3ef78a0af305
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84836
Reviewed-by: Ana Carolina Cabral
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
When creating variant, it was copied from teliks, and according to the requirements of telith project, update the override devicetree to use ELAN touchscreen.
BUG=b:373510302
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. power on proto board successfully
3. touchscreen is functional
Change-Id: If0da85a38f3a68b6f50cfd096a628174b313fcc9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84865
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Create the rull variant of the nissa reference board by copying
the template files to a new directory named for the variant.
And based on schematics NB7559_MB_SCH_V1_2024_1010.pdf
update devicetree settings.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:374673463
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_RULL
Change-Id: If48273f3e9db69507b41ea0313916d94ecabe309
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This change enables the integrated GPU (iGPU) display on the Fatcat
board based on the FW_CONFIG setting (specifically the DISPLAY bit).
By conditionally probing the display based on FW_CONFIG, the iGPU
is dynamically enabled or disabled according to the SKU configuration.
TEST=Verified display functionality on Fatcat with the iGPU:
> cbi set 6 0x58A814 4 (DISPLAY_ABSENT):
- lspci does not list the iGPU.
- No display output, but the device boots to the OS (verified via
console).
> cbi set 6 0x5CA814 4 (DISPLAY_PRESENT):
- lspci lists the iGPU.
- Display output is functional, showing firmware and OS UI.
Change-Id: I5762adf5ec8a86a00c16544670cb2f998055bd35
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84877
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
The iGPU device is enabled by default in the Pantherlake chipset
configuration. Remove the redundant device entry in the Fatcat
devicetree.
This change ensures that the iGPU remains enabled without explicit
configuration in the board-specific devicetree.
TEST=Able to build google/fatcat and able to see firmware and OS
display/UI.
Change-Id: I9a2ec9b47acb389f5bb6b30e61352aaefa327328
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84876
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Add PCIe domain support.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I3e06dfaf79924cd5352348afaa526fc7dedbb540
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84700
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable PCIe support for mt8196.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I9c0aaa1c6da8c247b319e7ed2317dd871e276461
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84698
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a trivial mainboard_needs_pcie_init implementation that always
return true. For now, the storage types of rauru SKUs are still unknown.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6b4f08e15f62da18aa37226075894f2827a9e7ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84697
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add PCIe driver for MT8196 platform.
According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. To ensure the 100ms
delay requirement is met and to save delay time in the ramstage, add
an early init data region to store the elapsed time since assertion.
This will speed up the boot time by 100ms.
PCIe port 1 and port 2 share the same PCIe resources, but PCIe port 2 is
not used. Therefore, in mtk_pcie_pre_init(), make sure PCIe port 2 is
reset to prevent interference with PCIe port 1.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I826a96822e88972bcd4966b6681797a646adf3d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
To reduce duplicate pcie.h in other SOC folder, mocw pcie.h to
mediatek/common folder
TEST=Build pass
BUG=b:317009620
Change-Id: I8e29ed4027433700652b07b3461eeb8546d45c9b
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
This code is never reached since the hardware uses different SoCs.
Besides, mainboard specific code should not be added to SoC code.
Change-Id: Id82d5d0b829442c35c093974c06a029259838a9a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
This commit improves the debug messages when initializing SPI flash
windows by adding the window type (Fixed Decode or Extended Decode)
to the log output.
This makes it easier to understand which window is being initialized
and can help with debugging issues related to SPI flash access.
w/o this patch:
[INFO ] MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
[INFO ] MMAP window: SPI flash base=0x900000, Host base=0xf9900000, Size=0x700000
w/ this patch:
[INFO ] Fixed Decode Window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
[INFO ] Extended Decode Window: SPI flash base=0x900000, Host base=0xf9900000, Size=0x700000
Change-Id: I904f70f42fa70ea06e6f49bd44631a8491463207
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
|
|
Ideally lock configuration is not applicable for early GPIO
configuration (like bootblock/romstage) and is only required for GPIO
PAD configuration by later statge (like ramstage).
The GPP_D15 pin was previously configured with LOCK_CONFIG in the
early bootblock GPIO configuration. This is not necessary and prevents
later boot stages from configuring this GPIO.
Change-Id: Ie0e648b750d7579def39ed95eab862dc3245499c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
|
|
Enable BT audio offload of WIFI_CNVI_WIFI6E or unprovisioned
based on fw_config.
BUG=b:373510270
TEST=Build and boot to Lotso. Verify the config from serial logs.
w/o this CL -
```
[SPEW ] -- CNVi Config --
[SPEW ] CNVi Mode= 1
[SPEW ] Wi-Fi Core= 1
[SPEW ] BT Core= 1
[SPEW ] BT Audio Offload= 0
```
w/ this CL -
```
[SPEW ] -- CNVi Config --
[SPEW ] CNVi Mode= 1
[SPEW ] Wi-Fi Core= 1
[SPEW ] BT Core= 1
[SPEW ] BT Audio Offload= 1
```
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Change-Id: I36f8c3fb24166c86d5fc4099fa9cde8cdecb9d49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84768
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This patch adds SPI and some accelerator device IDs for SNR platform.
IDs are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product
Families EDS, doc No. 575160 rev 2.0.
Change-Id: I7bd135d788816e4c3c42ac937450cf8cdcea00bc
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84782
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:348678529
TEST=on Google Fatcat board. Set the proper CBI fw_config bit(s) and
check that the corresponding GPIO PADs are configured as expected
value accordingly.
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d54
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch updates the flash map layout to guarantee that the
RW_SECTION_B section starts at a 16MB boundary.
TEST=Successfully builds google/fatcat.
Change-Id: I74ea21a8a4107d438bc03a0da182ea7e991e74bc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
|
|
Nova doesn't support thunderbolt, so disable the TBT setting.
Enabling TBT also causes the system to fail to enter S3/S5 state.
S5 fail log:
24-10-21 20:23:34.610 Port 80 writes:
24-10-21 20:23:34.610 9a02 9a32 9a14 9c15 9c18 9c19 9c20 9c22 9c25 9c28 9c3f 9c43 9c44 9c4f 9c23 9a50 9a5f 9a33 9b40 9b41
24-10-21 20:23:34.620 9b42 9b47 9c80 9c81 9c82 9c83 9a61 9a63 9a03 9a04 9a05 9a06 9a07 9a0f 9a65 9a64 9c6a 9c71 9c7f 99
24-10-21 20:23:34.626 a0 a1 72 24 25 24 25 55 24 25 55 55 73 74 75 75 75 75 75 75
24-10-21 20:23:34.633 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
24-10-21 20:23:34.639 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
24-10-21 20:23:34.643 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 76 77 79 9c
24-10-21 20:23:34.649 93 7a fe 7b f8 aa ab 96 <--new
powerinfo
24-10-21 20:23:59.424 powerinfo
24-10-21 20:23:59.424 power state 4 = S0, in 0x00ff
The correct power state for S5 is G3, not S0.
BUG=b:374213121
TEST=emerge-constitution coreboot chromeos-bootimage. Booting to OS and verify S3/S5 by EC log.
Change-Id: I2bae8ae396f001dbef3322e361f9563792e1a1ef
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84838
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
1. 2nd touch panel: INX N140HCN-EA1 C5
2. Set TOUCHSCREEN_ELAN9004 to value "3"
BUG=b:374899470
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Confirm command evtest and touchscreen function is workable.
Change-Id: Ic25bd46c7cb7948e920de4fd44edb87f20cf01c4
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84834
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
|
|
Add the new memory support:
Samsung K3LKBKB0BM-MGCP
BUG=b:374880584
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/glassway/memory/ \
src/mainboard/google/brya/variants/glassway/memory/\
mem_parts_used.txt"
Change-Id: I47d9fd64fa841a2cf60930c5e319a9130019b0a5
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84831
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
|
|
Change-Id: I8c9d66777b69b35f4df147c141fe94694f57be31
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83902
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I475f0c7582148e9b9f86b542f753a6654e9f9135
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
|
|
Use boolean for pch_is_wpt() and pch_is_wpt_ulx().
Change-Id: Ifd1a46ebdbe08df6cc21ada100b94930b02cd7de
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
|
|
Erying is a Chinese manufacturer selling desktop motherboards with
laptop SoCs and custom shim to mount desktop coolers.
Working:
- Serial port (IT8613E 0x3f8)
- All rear USB ports (3.0, 2.0)
- Both HDMI ports
- Realtek GbE NIC
- Internal audio (ALC897/ TGL-H HDMI)
- Environment Controller (SuperIO fan control)
- All SATA ports
- All PCI-E/M.2 ports
- M.2 NGFF WiFi
- PCI-E Resizable BAR (ReBAR)
- VT-x
WIP/Broken:
- PCI-E ASPM (also broken on vendor's FW, clocks are messed up)
- S3/s0ix (also broken on stock, setting 3VSB register didn't help -
system goes to sleep, but RAM loses power)
- DisplayPort on I/O panel (seemingly a simple fix)
- One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet)
- Automatic fan control (IT8613E can't read CPU_TIN at the moment)
Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as
vendor hasn't enabled any protections on SPI chip.
TEST=Flash coreboot build onto the motherboard, install following PCI-E
cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi.
Power the system up and boot into Windows 10 to check ACPI sanity, then
reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk
benchmark, compilation at the same time to check system's stability.
Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add and use a new helper function to determine if a device is
1) a PCIe device
2) it's mark hot-plug capable
Change-Id: I61cc013844024b43808cd2f054310cb6676ba69e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
In case of a PCH-less platform, no DRHD_INCLUDE_PCI_ALL flags are
used, all PCIe integrated end points should be explicitly listed
under the DRHD they are affiliated to. Otherwise, the device MSI
setting could fail.
TESTED = Build and boot on intel/beechnutcity CRB
In CentOS Stream (5.14.0-479.el9.x86_64) 9 5.14.0-479.el9.x86_64,
without the changes, below failure logs will occur,
[ 6.908347] ------------[ cut here ]------------
[ 6.908353] WARNING: CPU: 0 PID: 8 at drivers/pci/msi/msi.h:121 pci_msi_setup_msi_irqs+0x27/0x40
[ 6.908374] Modules linked in:
[ 6.908379] CPU: 0 PID: 8 Comm: kworker/0:0 Not tainted 5.14.0-479.el9.x86_64 #1
[ 6.908385] Hardware name: Intel Beechnut City CRB/Beechnut City CRB, BIOS c1e9362c93be-dirty 09/25/2024
[ 6.908389] Workqueue: events work_for_cpu_fn
[ 6.908401] RIP: 0010:pci_msi_setup_msi_irqs+0x27/0x40
[ 6.908411] Code: 90 90 90 0f 1f 44 00 00 48 8b 87 00 03 00 00 89 f2 48 85 c0 74 14 f6 40 28 01 74 0e 48 81 c7 c8 00 00 00 31 f6 e9 19 de ac ff <0f> 0b b8 ed ff ff ff c3 cc cc cc cc 66 66 2e 0f 1f 84 00 00 00 00
[ 6.908417] RSP: 0000:ffffac47c0137c80 EFLAGS: 00010246
[ 6.908423] RAX: 0000000000000000 RBX: ffff9a0a874e2000 RCX: 000000000000009c
[ 6.908428] RDX: 0000000000000001 RSI: 0000000000000001 RDI: ffff9a0a874e2000
[ 6.908433] RBP: 0000000000000000 R08: 0000000000000004 R09: 0000000000000001
[ 6.908437] R10: ffff9a0a8adcb258 R11: 0000000000000000 R12: 0000000000000001
[ 6.908440] R13: 0000000000000001 R14: ffff9a0a8738be00 R15: ffff9a0a874e20c8
[ 6.908443] FS: 0000000000000000(0000) GS:ffff9a0ded000000(0000) knlGS:0000000000000000
[ 6.908448] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 6.908451] CR2: ffff9a11fffff000 CR3: 00000003cd410001 CR4: 0000000000770ef0
[ 6.908455] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 6.908457] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7: 0000000000000400
[ 6.908460] PKRU: 55555554
[ 6.908462] Call Trace:
[ 6.908465] <TASK>
[ 6.908470] ? show_trace_log_lvl+0x1c4/0x2df
[ 6.908484] ? show_trace_log_lvl+0x1c4/0x2df
[ 6.908492] ? msi_capability_init+0x193/0x280
[ 6.908501] ? pci_msi_setup_msi_irqs+0x27/0x40
[ 6.908509] ? __warn+0x7e/0xd0
[ 6.908519] ? pci_msi_setup_msi_irqs+0x27/0x40
[ 6.908527] ? report_bug+0x100/0x140
[ 6.908537] ? handle_bug+0x3c/0x70
[ 6.908545] ? exc_invalid_op+0x14/0x70
[ 6.908551] ? asm_exc_invalid_op+0x16/0x20
[ 6.908561] ? pci_msi_setup_msi_irqs+0x27/0x40
[ 6.908569] msi_capability_init+0x193/0x280
[ 6.908577] __pci_enable_msi_range+0x1a3/0x230
[ 6.908586] pci_alloc_irq_vectors_affinity+0xc3/0x110
[ 6.908594] pcie_port_enable_irq_vec+0x3f/0x250
[ 6.908604] ? __pci_set_master+0x31/0xd0
[ 6.908614] pcie_portdrv_probe+0xdf/0x300
[ 6.908620] local_pci_probe+0x4c/0xa0
[ 6.908627] work_for_cpu_fn+0x13/0x20
[ 6.908635] process_one_work+0x194/0x380
[ 6.908643] worker_thread+0x2fe/0x410
[ 6.908649] ? __pfx_worker_thread+0x10/0x10
[ 6.908655] kthread+0xdd/0x100
[ 6.908665] ? __pfx_kthread+0x10/0x10
[ 6.908673] ret_from_fork+0x29/0x50
[ 6.908686] </TASK>
[ 6.908688] ---[ end trace 0000000000000000 ]---
Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84315
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Intel platform boot policy setting blob is linked into FIT table
as an FIT4 entry. It is required for server executing CBnT and/or
PFR without a PCH.
Please refer to chapter 4.6 of the document in below link:
https://www.intel.com/content/dam/www/public/us/en/documents/
guides/fit-bios-specification.pdf
Tool usage:
./util/cbfstool/ifittool -f <binary> -a -n <cbfs name> -t 4 \
-r COREBOOT -s <max table size>
Change-Id: I0f9fc61341430b1a35a44d50b108dcfaf31cd11c
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84305
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I79b08630753b3aceb94becc8b9d682a3d3ca8310
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84308
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Id2a2946b7fdfd7fd245835afe6abc9a3f7e1a508
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Xeon-SP simics doesn't provide simulation of writable PAM-F
(Programmable Attribute Map) segment and hence coreboot needs to
enable SHADOW_ROM_TABLE_TO_EBDA to write system table pointers to
EBDA (Extended BIOS Data Area).
Change-Id: I216204987ad646a5d1655323d2725cfd3415a2d7
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Use dev_find_all_devices_on_stack() to find the PCI device on a given stack.
That way open coded duplicated code can be dropped and there's no need to call
socket0_get_ubox_busno(), which allows to drop socket0_get_ubox_busno().
In addition it adds PCI multi segment support.
Change-Id: Ib0ed177ae22112a9f2ed32199409d91cb5851ede
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84790
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The newly added enums and struct members will be used by MT8196.
BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot
Change-Id: I32e758cc4244114073606c418a69e0467cdf1039
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84773
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
MT8196 has different pmif_spmi_arb and pmif_spi_arb configurations. Move
the common pmif data to a separate file in order to reuse common/pmif.c
as much as possible.
BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot
Change-Id: I24643ce58a57b9cc3c5220bc06a85b141b366eee
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
MT8196 has differenet configurations from other platforms. Make
CAL_TOL_RATE and CAL_MAX_VAL as per SoC configuration in order to reuse
common/pmif_clk.c
BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot
Change-Id: Iefc8180e1719d9796df7457b619a8792ceb762b2
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84771
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This enables SOC_INTEL_DEBUG_CONSENT to set PlatformDebugOption
to Trace Ready to have the safe configurations for Panther Lake
ES SoC.
This safe configuration will be removed once the feature is fully
verified and safe to be set to the default value.
BUG=b:373915085
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: I1eaabcb2e2aaff16ee4e64d1c7709b229de18459
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84823
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
|
|
Fix the following error when including device/pciexp.h
src/include/device/pciexp.h: In function 'pciexp_is_downstream_port':
src/include/device/pciexp.h:42:24: error: 'PCI_EXP_TYPE_ROOT_PORT' undeclared (first use in this function)
42 | return type == PCI_EXP_TYPE_ROOT_PORT ||
by including pci_def.h.
Change-Id: Idfd36301a5e766bbe97c93afef88c97507a4c4dc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84791
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adjust the DSM to return 0x00 (unsupported) when no reset gpio
is passed to the driver. Leave the _RST method to comply with
the ACPI specification but omit the BTRT method as it won't do
anything.
Change-Id: I9f8e98fb4f5a22b2f7617b131a3d71cf90f5bc80
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
|
|
If project set configure_ext_fivr = 0 will cause
PchFivrVccstIccMaxControl do not set correctly.
BUG=b:361831628
TEST=Verified on Teliks360 that affected DUTs.
Change-Id: I816de9c0c507aad3b73ab29e9f72048704f4662d
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84812
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
|
|
Alder Lake, Meteor Lake and Panther Lake use the effective way size
when setting up the Enhanced No-Eviction Mode (cf.
`INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE').
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83947
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
|
|
On Alder Lake, Meteor Lake and Panther Lake platforms the way size to
consider for NEM+ computation is the effective way size.
On Alder Lake, the External Design Specification #627270 "3.5.2
No-Eviction Mode (NEM) Sizes" provides a way to compute the effective
way size by reading the number of CBO. Unfortunately, reading the
number of CBO is not possible on Meteor Lake and Panther
Lake. Therefore, we instead compute the effective way size as the
biggest of power of two of the way size which works across all three
platforms.
The Kconfig `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE' is introduced to
control this behavior.
The issue addressed by this commit can be observed with the following
experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to
0x400000 (4 MB).
The number of ways that used to be computed is round(0x400000 /
0x180000) = round(2.66) = 3. 3 ways were mapped to cover the 0x400000
NEM+ region. When the bootblock code accesses memory between 3 MB and
4 MB, the core would raise a page fault exception.
The right computation is: 0x400000 / eff_way_size(0x180000) = 4. 4
ways needs to be mapped to cover the entire 0x400000 NEM+ region.
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This disables C1 state auto-demotion to run the coreboot with
Panther Lake ES SoC without an issue.
This configuration will be remove later once the related features
are fully verified.
BUG=b:373915085
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: I384dba2918cfd04deb90284513c204fa8c21094b
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84767
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
|
|
There is no ACPI power resource for LTE module Rolling RW101R-GL,
therefore implement the power sequence of power-on, power-off, and
reset timing from GPIO init, bootstate init callbacks, and smihandler
function.
BUG=b:368450447
BRANCH=None
TEST= Build firmware and verify on jubilant with LTE:RW101R-GL.
Measure the power on, power off, and reset timing.
Run warm boot, cold boot and suspend/resume to make sure
WWAN devcie is workable.
Change-Id: I4a205e3db777c7c225d31b6cc802883fd7167089
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update jubilant CPU PL4 from 9 watt to 14 watt for critical battery
boot. The maximum peak power is set at 14 watt which is 45W multiplied
by 32% efficiency.
Overriding power limits for AC power without battery:
PL1 (15000, 18000)
PL2 (41000, 41000)
PL4 (14)
BUG=b:364441688
BRANCH=None
TEST=Able to successfully boot on jubilant SKU1 and SKU2 with AC only.
Test on AC 65W and 45W w/o battery, and check PL4 values from log.
Change-Id: Id1e58797206a61d241f48b057b304e05c9c323d9
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84784
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi PCIe hosts M.2 E-key WLAN to fulfill
drawman_jsl_schematic_20200528.
BUG=None
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: If414ff1941d2d70c5f0444ac58b228ed5c95303a
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c5477bbc248a21e21f3a640bdb81304a1bce38c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Add a new Rauru follower 'Navi'.
BUG=b:341210522
TEST=emerge-cherry coreboot
Change-Id: Ia2a6c1c09b3cedc0ef7f51ec93fdabf2c07c8885
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84694
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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NAU8318 supports beep function via GPIO control. Configure the
GPIO pins and pass them to the payload.
BUG=b:343143718
TEST=Verify beep function through CLI in depthcharge successfully.
We can test with:
firmware-shell: badusbbeep
firmware-shell: devbeep
Change-Id: I79277bc1947dab517dea5aba583c5b4e0ac81bc4
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84693
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no powering-on control in the fingerprint kernel driver. The
fingerprint team of ChromeOS suggests powering-on FP MCU in the FW.
Follow trogdor to pull down FP_RST_1V8_S3_L, AP_FP_FW_UP_STRAP,
EN_PWR_FP and pull up EN_PWR_FP in ramstage for power rail to be stable.
BUG=b:340401582
TEST=measure waveform and the fingerprint works on ChromeOS
Change-Id: I05600d90fdf922faeb778a36d8a08f68c1bb4125
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84692
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Configure GPIO EINT28 (XHCI_INIT_DONE) as output, so that payloads
(for example depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:317009620
TEST=emerge-rauru coreboot
Change-Id: I5950974435b56997626886b16d371cd8e6472e3c
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84691
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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N-1 IBL (Integrated Boot Logic) codes are initially forked from
EBG (Emmitsburg PCH) codes (src/soc/intel/xeon_sp/ebg). N-1 IBL
codes are a set of stub codes to fulfill build sanity check for GNR
SoC and CRB codes before the formal codes are published.
Change-Id: I6bd5a2ed973ff91750c5ed1f9a57d30e41d8b97e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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FW_CONFIG ids
Based on Gallida360 design, we add two new options for WIFI_SAR_ID:
- WIFI_SAR_ID_INTEL_CONVERTIBLE 2
- WIFI_SAR_ID_INTEL_CLAMSHELL 3
BUG=b:372354703
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I1b58c4f572d4dbcb269d38485664ddc51e378e5e
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84779
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Create the francka variant of the fatcat reference board.
BUG=b:370666276
TEST=util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_FRANCKA
Change-Id: I372f445f7007d0d33020545a8febbce27c260e41
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84769
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the GPIO pad configuration to be performed before memory is set up
along with the relevant devices definition.
This patch includes:
- FW config for pre-mem GPIO PAD configuration
- Add overridetree changes used by pre-mem FW config
BUG=b:348678529
TEST=Boot on Google Fatcat board. Note this cannot be tested by itself
directly. Test with CL:84408, set the proper CBI fw_config bit(s) and
check that the corresponding GPIO PADs are configured as expected value
accordingly.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iac1f637c21a9818512b224dc4cbe4a75dbc516ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84718
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Create the telith variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=372506691
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TELITH
Change-Id: I4971b9691d3dd293ca640795967c36472afef9c9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84759
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add support for Arm Neoverse N2 Reference design.
Based on Arm Neoverse N2 reference design
Revision: Release D
TEST=Build Arm Neoverse N2 & make sure there is no error.
Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add the BMC and all PCIe slots that the board implements.
There are 32 RSSDs and 2 M.2 slots.
Change-Id: Id7d72990d6997d1e8b9ce75477ce3dc571c99839
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add slot types found in SMBIOS spec 3.8.0.
Change-Id: I705529efcbf2add420fb6f4a720ec33444d46efa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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TEST=Build & boot in IBM SBP1 system. Verified the settings are effective in FSP logs.
Change-Id: I4341ead89a2683f64c834a6981ba316fcfef4f9a
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84741
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The current panel brightness is only 360 nits. Adjust the power and
gamma to optimize the panel brightness. The brightness after adjustment
is 390 nits.
BUG=b:320892589
TEST=boot ciri with IVO_T109NW41 panel and see firmware screen
BRANCH=geralt
Change-Id: I760c37bf915bb40ad2efa7c947034cb168938f2a
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84758
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The spec tells us to clear the busy bit manually after a timeout. Do
that and wait immediately, to detect further issues early. Also fix
some related comments and prints: Failures shouldn't be debug messa-
ges. And we are talking to the PIO interface of the controller, not
the codec. So this was never about the codec being ready.
Change-Id: I4b737f8259157c01bfcd9e6631cc15d39c653d06
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83592
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Add STYLUS fw_config setting.
2. Enable stylus device settings.
3. Disable the stylus GPIO pins based on fw_config.
BUG=b:364798563
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot
2. Confirm command evtest for stylus PRP0001:00 and workable.
Change-Id: Ifa8555eed1c31e9342a50a735fc618106f26d41a
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84713
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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