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2022-02-21mb/google/volteer/var/drobit: update default codec HID to 10EC5682FrankChu
Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:204517112 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ic37e7e6757476f1d30bea31fcde4deebebd488a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21mb/google/volteer/var/delbin: update default codec HID to 10EC5682FrankChu
Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:204523176 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I36e35522aba2463124b7e6e7046b1a56758b534d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21mb/google/volteer/var/copano: update default codec HID to 10EC5682FrankChu
Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:218245715 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I30a1fe2ef8d750616f6907f86a5329f035920504 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21soc/amd/sabrina/fw.cfg: Change the instance of PMUI/D to 2Zheng Bao
Change-Id: Ie9dbed7d6dd1e5f0c97d4a6cedea3d6bd7b000a2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-21soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUDZheng Bao
Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21mb/google/brya: Enable eMMC HS400 mode for nissaReka Norman
Based on the nivviks and nereid schematics, nissa is using eMMC HS400 mode, so enable this in devicetree. BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21mb/amd/chausie/chromeos.fmd: resize EC size in FMAP to 4kByteFelix Held
Only the info about the location of the EC firmware will be stored right at the beginning of the flash, so the size can be reduced to 4kByte which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE file itself is smaller than this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21soc/intel/alderlake: Make clang static assert happyArthur Heymans
Change-Id: Ia3cd66f6b735f7430abcdba8a9323d5ee1320fd4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21drivers/intel/pmc_mux: Fix printing typeArthur Heymans
Change-Id: I1cb517323e7d609ae6624363e116e9814fc631cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21soc/intel/alderlake: Fix function pointer typeArthur Heymans
const void is not a proper return type for a function. It's the function pointer themselves that need to be const. This fixes building with clang. Change-Id: I99888ab9d9d80f1d6edb33b9f4a3f556f211a6e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21drivers/intel/fsp2_0/hob: Remove unused variableArthur Heymans
Change-Id: Ie9f4562be9b019d8dd65d4e9040fefbb6834fa03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-21soc/intel/adl/bootblock/report_platform.c: Use the correct formatArthur Heymans
Change-Id: I54c40434f44621c4ea6564ac9c87c5b2fa083b5d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21ec/google/chromeec/ec_acpi.c: Cast compatible enum typesArthur Heymans
Clang complains about this. Change-Id: If7af9d5a81c1c381490c9634e3da68ff7f5edda8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21[acpi]{include,soc/amd,southbridge/amd}: Clarify ARM_boot_arch in commentsElyes Haouas
Change-Id: I8b209da90b5a591f62e760961c64c4c63e6ef65b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21include/device/dram/ddr3.h: Don't redefine 'printram(x, ...)'Elyes HAOUAS
'printram(x, ...)' is already defined in 'include/device/dram/common.h' file Change-Id: I75e19065b9e713df3190202b7ca9e9cd8f3f44a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-21soc/intel/denverton_ns: Add `pmc_mmio_regs` as public functionSubrata Banik
This patch adds `pmc_mmio_regs` a public function for other IA common code may need to get access to this function. BUG=none TEST=none Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I67a0f7fdcd0827172426bc938569a5022eff16f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-21soc/intel/denverton_ns: Select PMC PCI discoverable configSubrata Banik
This patch selects SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE config to reflect the SoC actual behaviour where PMC PCI device is still visible over bus even after FSP-S exit. Additionally, add DNV PMC PCI ID into PMC IA-common code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iaaea20e54c909800e4d75b58c29507fc1944cfba Reviewed-on: https://review.coreboot.org/c/coreboot/+/62135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-02-21mb/google/brya/variants/felwinter: Adjust I2Cs CLK to be around 400 kHzJohn Su
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for audio, TPM, touchscreen, and touchpad. Audio CLK: 385 kHz TPM CLK: 380.5 kHz Touch Screen CLK: 373.3 kHz Touch Pad CLK: 372.7 kHz BUG=b:218577918 BRANCH=master TEST=emerge-brya coreboot chromeos-bootimage measure by scope with felwinter. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I3e5cc10d6605f9cc41fa6b31da07a81364b72fe0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-21mb/amd/chausie/Kconfig: Move EC firmware image in CBFSFred Reitberger
Move the EC to a location that does not conflict with where the main CBFS is in the chromeos FMAP Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21src/acpi/acpigen.c: Reformat codeElyes Haouas
Change-Id: I58851c8a26cad61975f8ba2910eedef3029aab6f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2022-02-21mb/intel/adlrvp_n: Update devicetreeKrishna Prasad Bhat
Update devicetree according to schematics. TEST=Build and boot Alder Lake N RVP. Change-Id: I9faee1cb3539a0246fc6a87e15b3150533de1ee5 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21soc/intel/alderlake: Enable eMMC based on dev enabledKrishna Prasad Bhat
1. Add eMMC device function in pci_devs.h. 2. Enable eMMC device and configuration based on dev enabled. 3. Add SOC acpi name for eMMC. Change-Id: I44f17420f7a2a1ca0fbb6cfb1886b1617c5a5064 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake NKrishna Prasad Bhat
Alder Lake N SOC has eMMC device. Add ACPI ASL methods for it. Change-Id: I53f04e81584493049d37b46e078d394d3c8a2f09 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21src/acpi: Add macro for FADT Minor Version and use itElyes Haouas
Change-Id: I6a0e9b33c6a1045a3a4a6717487525b82d41e558 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2022-02-19mb/amd/chausie: increase RW_MRC_CACHE size in FMAPFelix Held
On Sabrina SoCs the size of the APOB has increased, so the size of the RW_MRC_CACHE FMAP sections needs to be increased in order for the data to still fit in the corresponding FMAP partition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya: remove the delay from for WWAN _ON method.Cliff Huang
Remove unecessary delay in RTD3 _ON Method after PERST# dessartion. TEST: 2022-02-10T18:22:53.204391Z INFO kernel: [ 0.190287] ACPI: Power Resource [RTD3] (on) 2022-02-10T18:22:53.204395Z INFO kernel: [ 0.194252] ACPI: Power Resource [RTD3] (off) Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I9bc36af6e6c944fcd3de23b7d49640ad9d25642d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-02-18nb/amd/pi/00730F01/northbridge.c: Use 'pci_{and,or}_config'Elyes Haouas
Change-Id: Ifd77c90fe82e20df91562fccea8b5d89dd4a193d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-18soc/intel/apollolake: Create alias for GEN_PMCON1 as GEN_PMCON_ASubrata Banik
This patch creates alias for GEN_PMCON_A to maintain parity with other IA SoC PMC register definitions. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id9a23c58a325cb544c50cbda432fe3117eea22fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18soc/intel/denverton_ns: Add function to clear PMCON status bitsSubrata Banik
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. Added `MS4V` macro for GEN_PMCON_A bit 18 as per EDS doc:558579. Additionally, removed `PMC_` prefix from PMC configuration register macros GEN_PMCON_A/B and ETR3. Moved PMC PCI device macro from pmc.h to pci_devs.h and name PCH_PMC_DEV to PCH_DEV_PMC. Also, adjust PCI macros under B0:D31:Fx based on function numbers. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2690ccd387b40c0d89cf133117fd91914e1b71a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18soc/intel/alderlake: Skip FSP Notify APIsSubrata Banik
Alder Lake SoC deselects Kconfigs as below: - USE_FSP_NOTIFY_PHASE_READY_TO_BOOT - USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE to skip FSP notify APIs (Ready to boot and End of Firmware) and make use of native coreboot driver to perform SoC recommended operations prior booting to payload/OS. Additionally, created a helper function `heci_finalize()` to keep HECI related operations separated for easy guarding again config. TODO: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects required configs. BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot HECI: CSE device 16.1 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0198c9568de0e74053775682a44324405746389a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18soc/intel/common/cse: Add `finalize` operation for CSESubrata Banik
This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects all required configs: BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot HECI: CSE device 16.1 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-18drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik
This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-18mb/google/brya/redrix{4es}: Disable unused USB2/TCSS portsWisley Chen
Disable unused USB2/TCSS Ports. BUG=b:217238553 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I1cdee5b6dc56accb52ba1bf636bdf753a7bfd199 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-18arch/x86/acpi: Add code for KEY_MENUBoris Mittelberg
Support of MENU key (aka hamburger) for Chromebooks with Vivaldi keyboard BUG=b:215038215 TEST=manually tested on Anahera device: pressing T13 key opens menu Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I07873dd9385c743a6512408688ec44a5e97219f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61835 Reviewed-by: Rajat Jain <rajatja@google.com> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18ec/google/chromeec: Update ec_commands.hBoris Mittelberg
This change copies ec_commands.h directly from the Chromium OS EC repo, with the exception of changing the copyright header to SPDX format. Update to commit hash af9a119 Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I1f2a140257d6127fb19bb514bc345466247b7499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-18soc/amd/common/block/psp/Makefile: add fmap_config.h dependencyFelix Held
Compiling efs_fmap_check.c depends on fmap_config.h already being generated, so add this dependency. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85e0900574f928d1594f8d1831ba58f959b75d27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18soc/amd/common/block/apob/apob_cache: use APOB cache size from FMAPFelix Held
Also add the Makefile dependency on the fmap_config.h file to make sure that this file already exists when it's included. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I540ea2c14fd187845efd3c0c8c1e4b8f82c8cac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18include/acpi/acpi.h: Drop non-existing update_ssdt()Elyes Haouas
Change-Id: Ie8535d97e883d3fed9414fb5ba65a0797b989c0d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18include/acpi/acpi.h: Drop non-existing update_ssdtx()Elyes Haouas
Change-Id: I2fd8470ed2b8e8f00de4ba64258aac1db52744c1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18mb/google/brya/var/{redrix, redrix4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I61f8f39ce7651d499756f4975840f32f89b04ca7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-18mb/google/brya/var/felwinter: Update DPTF parameters for FelwinterJohn Su
Follow thermal team design to remove TSR3 sensor and update thermal table for next build. The DPTF parameters were verified by thermal team. BUG=b:219690502 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I0e34fabe546b6eabb3d3adad583668a15a1d908b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18mb/google/brya/var/vell: Correct MIPI camera infoShon Wang
The CIO2 port was incorrectly set to 2, while the correct port is 1 BUG=b:210801553 TEST=Build and boot on vell, camera works correctly now Change-Id: I53d8448ed0e12777456af9b0bc65a04595b47e37 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61946 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/volmar: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1e0b51ee4db73bdff79365d4954a3245a430f140 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62051 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/vell: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e4837489d90c2edd7deaa2af0533085f1ff5ae6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62049 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/taniks: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id44213c7dd4d0df97a6c57d7f1b9d950baaf0e1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62047 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{taeko, taeko4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie304b08b0b1bbad5547a0169ea8056d703141391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61830 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{primus, primus4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1a4bc1aae8e815b882a607432e40caf1066453b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61828 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/kano: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I07cef3b619991afb6337c38a631ee159677d30a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61826 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{gimble, gimble4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0274f03926d97fc543b98f3fb961580283202806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61825 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/felwinter: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I33e4501fd689d642682891c7f5bc9cb7ca5e331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61824 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{brya0, brya4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1940246fd88db29054f85c43672adc97dc90fa04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61823 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{anahera, anahera4es}: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3d8a8a7e2b1e490726986139014cdfcf1271c64b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61805 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/agah: Use ACPI _PLD macroSubrata Banik
This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Idb8f30b2d1069aea1d5ce7c5dda7f99de33a7c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61803 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18acpi: Use ACPI macros to configure USB port _PLD objectSubrata Banik
This patch adds two ACPI macros for USB port A and C _PLD object configuration as: 1. ACPI_PLD_TYPE_A 2. ACPI_PLD_TYPE_C The configurable parameters are - Panel, Port is exposed on which face of a panel. - Horizontal, Horizontal position on the panel where the device connection point resides. - Group - Token, Unique numerical value identifying a group. - Position, Identifies this device connection point’s position in the group (i.e. 1st, 2nd). BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I245b17019b6d3c5e380c16cb3c9f4edc4dd10cc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18mb/google/brya/var/volmar: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iddf0727a538f2063cfabbec1f900c488331f33c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/vell: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib0d1be34775c5eacf6cd9b0ec400bd42a93c59e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/taniks: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia9bc235c257abce2a3cd63cfd1b17ac356267d8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/taeko4es: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic3fbf307bfa42bd377c8f23c1837a6d15cb378e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/{redrix, redrix4es}: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I80d9038d1f41d65201d6bfdb808708f997d71faf Reviewed-on: https://review.coreboot.org/c/coreboot/+/62031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/{primus, primus4es}: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic97d48633ef1f246c181046ec32ab81614ba5ceb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18mb/google/brya/var/kano: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I78734f685672347b06783f834643347a35c59e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18mb/google/brya/var/{gimble, gimble4es}: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4e051b21ca55d25c6fc6cfb529078b18adaab2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62028 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18mb/google/brya/var/{anahera, anahera4es}: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0c72a5c5306d63c5fce24bf727704d212d0ad0f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18mb/google/brya/var/agah: Fix PLD group orderSubrata Banik
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9cef57bbaf3e3519b7f6a7e3d86979722b598ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17mb/google/guybrush: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSPJan Dabros
Guybrush platforms have I2C3 controller which is shared between PSP and X86. In order to enable cooperation, PSP acts as an arbitrator. Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is binded on the OS side. With this change in place it is important to use correct kernel version which has I2C-amdpsp driver [1] enabled. Otherwise, we won't have I2C3 available and thus TPM device available in OS, what may end up as a serious error - guybrush refuses to boot without access to TPM. BUG=b:204508404 BRANCH=guybrush TEST=Build proper kernel and firmware. Run on guybrush and verify TPM functionality. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I9dd94e47e1a02e790427b67adff84de3eb3ee387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61965 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17soc/amd/common/block/i2c: Add support for shared TPM_I2C controllerJan Dabros
There are platforms equipped with AMD SoC where I2C3 controller connected to TPM device is shared between X86 and PSP. In order to handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends acquire and release requests to be accepted by PSP. An example of implementation within Linux kernel is available [1]. There is a need to introduce new ACPI_ID ("AMDI0019") so that dedicated driver on OS side can bind to it and handle this special setup. Since PSP takes care of I2C controller power management, we need to remove PowerResource object from DSDT. BUG=b:204508404 BRANCH=guybrush [1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: Iccfc09d8c580d7ab2acb69d26b9c293cf625fb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61863 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17mb/amd/chausie: Add EC blob into CBFSFred Reitberger
Add chausie EC blob into CBFS at specified location Change-Id: I48de08a18054efbda655e1563a539ff2ba7a38a6 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-17mb/google/herobrine: Disable fingerprint sensor on CRD devicesRavi Kumar Bokka
Qualcomm CRD devices do not have a fingerprint sensor so removing the QUP configuration for it. This QUP also coincidentally is the same as the one used for the TPM, so this initially was also causing TPM communication issues during bootup as the QUP was being reconfigured during the later stages after QcLib execution. BUG=b:206581077 BRANCH=None TEST=Boot to kernel without any CR50 communication errors Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I8d13b67796b70b0b7e9a4721cca0b8a54b2b27c1 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61716 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17mb/google/brya/var/vell: Add Wifi SAR for vellRobert Chen
Add wifi sar for vell BUG=b:218992598 TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I74fddd1dbcb7019fd5fe394da291f125f0d4960f Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-17mb/google/brya/var/vell: Correct the DQ mappingGaggery Tsai
This patch corrects the DQ mapping and enable ECT. In Vell design, the DQS is swapped in Mc0.ch1, Mc0.ch3, Mc1.ch0, Mc1.ch1 and Mc1.ch2 but the DQ mappings are not swapped and that causes ECT training failure. BUT=b:208719081 TEST=emerge-brya coreboot chromeos-bootimage && ensure the system passes ECT training and all the way booting to the OS. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Idd2ad16151f0b2b93b00295b75a66ba65cba23cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-17src/soc: Remove space before tabElyes Haouas
Spaces before tabs are not allowed. Change-Id: I0d2c55c2e0108e59facd92b2e2c0f6c418ef6db0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62055 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17drivers/intel/usb4/retimer/retimer.c: Remove space before tabElyes Haouas
Spaces before tabs are not allowed. Change-Id: I1aa8490cb81a77f48d69c16c175eb4fec70dc0db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62054 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17soc/intel/alderlake: Add CNVi common driver KconfigVarshit B Pandya
Alder Lake has CNVI device. Select SOC_INTEL_COMMON_BLOCK_CNVI for Alder Lake. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6bf2292e870c990deb63fbf6e841ae7c5c63b3a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-17soc/mediatek/mt8195/include/soc/addressmap.h: Remove space before tabElyes Haouas
Spaces before tabs are not allowed. Change-Id: I2732c01fd87c56227d47a4c0104de8e227b0cc34 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62018 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17amd/common/block/gpio/gpio: don't use -1 as bitmask in gpio_or32Felix Held
The and-mask passed to the gpio_update32 call needs all 32 bits to be set to ones. When building as 32 bit binary the -1UL will result in the needed bit mask, but for a 64 bit build the constant would have 64 bits set to ones which then gets truncated to 32 bits causing a compiler error. Use 0xffffffff as bit mask instead which behaves correctly in both cases and also clarifies what this is doing. TEST=Timeless build for Chausie results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0b6a50bd914fdbb7a78885efb6c610715e2d26c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62053 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aamir Bohra <aamirbohra@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17amd/common/block/spi/fch_spi_ctrl: use uintptr_t for addressesFelix Held
This fixes a build failure when trying to build the code in 64 bit mode. TEST=Timeless build for Chausie results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If8fe7b626d9d72c0b8ed07ced93e46f795e36848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamirbohra@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-16mb/google/herobrine: Add Gigadevice SPI PartShelley Chen
BUG=b:182963902 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I73dc695afb7aa2b32aa966070eb057c828073d47 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16mb/google/herobrine: Alphabetize SPI_FLASH configsShelley Chen
BUG=b:182963902 BRANCH=None TEST=None Change-Id: Ia73460d335e859644511b7e9ca80111a919baf2c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16soc/amd/cezanne/psp_verstage/uart: Fix off by 1 errorRaul E Rangel
We only allow index = {0, 1}. Fix the check. BUG=b:215599230 TEST=Build guybrush BRANCH=guybrush Found-by: Coverity CID 1469611 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I59615ab39faeded43b3803b4450c84ab8a8b81ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/61988 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-16Use the fallthrough statement in switch loopsArthur Heymans
Clang does not seem to work with 'fall through' in comments. Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16compiler.h: Define a __fallthrough statementArthur Heymans
Change-Id: I0487698290992162fac6bb74b5082901415e917e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16mb/google/brya/var/agah: Select PCIEXP_SUPPORT_RESIZABLE_BARSTim Wawrzynczak
The google/agah variant will use a peripheral that will require the use of the PCIe Resizable BAR feature from the PCIe spec. Thus, select the new Kconfig option to enable it. The appropriate Resizable BAR size will be updated later. BUG=b:214443809 TEST=build Change-Id: I9cf86ba3160ae5018655b5d366e89f4273b30b94 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-16device: Add support for PCIe Resizable BARsTim Wawrzynczak
Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can indicates support for "Resizable BARs" via a PCIe extended capability. When support this capability is indicated by the device, the size of each BAR is determined in a different way than the normal "moving bits" method. Instead, a pair of capability and control registers is allocated in config space for each BAR, which can be used to both indicate the different sizes the device is capable of supporting for the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and to also inform the device of the size that the allocator actually reserved for the MMIO range. This patch adds a Kconfig for a mainboard to select if it knows that it will have a device that requires this support during PCI enumeration. If so, there is a corresponding Kconfig to indicate the maximum number of bits of address space to hand out to devices this way (again, limited by what devices can support and each individual system may want to support, but just like above, this number can range from 20 to 63) If the device can support more bits than this Kconfig, the resource request is truncated to the number indicated by this Kconfig. BUG=b:214443809 TEST=compile (device with this capability not available yet), also verify that no changes are seen in resource allocation for google/brya0 before and after this change. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/61215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-16vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v2503_00Ronak Kanabar
The headers added are generated as per Alder Lake N FSP v2503_00. Previous FSP version was v2503_00. Change include: Add following Emmc UPDs in Fsps.h - ScsEmmcEnabled - ScsEmmcHs400Enabled - EmmcUseCustomDlls - EmmcTxCmdDelayRegValue - EmmcTxDataDelay1RegValue - EmmcTxDataDelay2RegValue - EmmcRxCmdDataDelay1RegValue - EmmcRxCmdDataDelay2RegValue - EmmcRxStrobeDelayRegValue BUG=b:213828776 BRANCH=None Change-Id: I617673a0cb12e7165f2f63cce73fff38bc7bf827 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-16mb/google/brya/var/agah: Change ELAN touchpad driver for eKT3744Tony Huang
Change to use i2c/generic to match ELAN FW update script. BUG=b:210970640 TEST=emerge-draco coreboot chromeos-bootimage Change-Id: Ib416da6000d9e99f9c37cf497fb1c43e3fca0220 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16soc/amd/common/block/psp: add PSP commandJason Glenesk
Add PSP command to send SPL fuse command if PSP indicates SPL fusing is required. Also add Kconfig option to enable sending message. BUG=b:180701885 TEST=On a platform that supports SPL fusing. Build an image with an SPL table indicating fusing is required, confirm that PSP indicates fusing required and coreboot sends the appropriate command. A message indicating PSP requested fusing will appear in the log: "PSP: Fuse SPL requested" Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-02-16payloads/external: add skiboot (for QEMU/Power9)Sergii Dmytruk
Add an option to build skiboot as a payload. This makes QEMU Power9 board simpler to use as skiboot is necessary anyway. Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-16soc/intel/alderlake: Correct Alder Lake M/N ESPI device IDKrishna Prasad Bhat
Alder Lake M/N ESPI ID 18 was incorrectly assigned to be 0x5482. Assign it to the correct value. Reference documents: 619501, 645548. Change-Id: I08bd218fd128497825b96aa5b9496826afa620d2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61947 Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-16mb/google/brya: Update memory DQ mapEric Lai
Follow latest schematic to update the DQ map. BUG=b:218939997 TEST=boot into OS without issue. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If29cc22b1749fb5d602d3ce64bcc1182593d673f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-16drivers/intel/fsp: Set FSP_LOG_LEVEL_ERR_WARN_INFO for DEBUG_RAM_SETUPKane Chen
To get verbose MRC log includes RMT log, we need to set FSP_LOG_LEVEL_ERR_WARN_INFO instead. TEST=tested on gimble, see MRC verbose and RMT log are printed Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Change-Id: I3896f0482dfde090b4e087490b7937683b5de091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-15mb/starlabs/labtop: Disconnect unused GPIO'sSean Rhodes
Disconnect all GPIO's that aren't connected to anything. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2050da62f73c0f99fbfef013c22e35225cc480c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-15mb/starlabs/labtop: Add comments for GPIOsSean Rhodes
Add comment for each GPIO details its endpoint based on the schematic. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia3678274dcd52285019fb3cf8ccd22617268ce1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-15ec/starlabs/merlin: Adjust Keyboard Backlight configurationSean Rhodes
* Change TGL Q Event for Keyboard Backlight to Q4A * Change enabled value to 0xdd Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibae95e458f14b9d03ff50cb6222b336fd015d0e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15ec/starlabs/merlin: Apply EC settings when suspendingSean Rhodes
Currently, the settings from CMOS were written to the EC, which was pointless. Now, when suspending, the EC values are stored in CMOS when suspending and subsequently restored when waking. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I998d5509cd5e95736468f88663a1423217cf6ddf Reviewed-on: https://review.coreboot.org/c/coreboot/+/60165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15nb/intel/ironlake/raminit_heci.c: Move to southbridge scopeAngel Pons
HECI stuff is in the southbridge, so put the code in there. Rename the file to match the name of the function it provides. Change-Id: I71de1234547dbd46a9b4959c619d2ae194da620a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake: Decouple `setup_heci_uma()` from northbridgeAngel Pons
Remove all northbridge dependencies in the `setup_heci_uma()` function. Update its signature to not pull in raminit internals and drop a dummy read that doesn't have any side-effects (it's probably a leftover from a replay of vendor firmware). This code will be moved into southbridge scope in a follow-up. Change-Id: Ie5b5c5f374e19512c5568ee8a292a82e146e67ad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake/raminit_heci.c: Turn into compilation unitAngel Pons
Remove the temporary `raminit_heci.c` include and make it a proper compilation unit. Export the `setup_heci_uma()` function. Change-Id: Ia6782a0cb5e731d58764d0fa4ee256bfc8cef98a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake: Split out HECI code out of raminitAngel Pons
Move HECI code out of raminit.c into a separate raminit_heci.c file. To preserve reproducibility, use a temporary .c include. This will be gone in a follow-up. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I240552c9628f613fcfa8d2dd09b8e59c87df6019 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-15arch/x86/id.S: Fix building with clangAngel Pons
Commit 0e688b113d7fd98dfdb69cd0a407c8efcd968456 (arch/x86/id.S: Fix building with clang) broke building with GCC 8.3 so this approach should work for both GCC 8.3 and clang. The clang error is: CC bootblock/arch/x86/id.o /tmp/id-35b17a.s:35:7: error: expected relocatable expression .long - ver ^ /tmp/id-35b17a.s:36:7: error: expected relocatable expression .long - vendor ^ /tmp/id-35b17a.s:37:7: error: expected relocatable expression .long - part ^ Change-Id: Ide3d313800641d4d9b5f79127f84d9fdb4ec2b96 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15Revert "arch/x86/id.S: Fix building with clang"Angel Pons
This reverts commit 0e688b113d7fd98dfdb69cd0a407c8efcd968456. Reason for revert: Breaks building with GCC 8.3 which is currently needed to build bootable coreboot images for Ironlake boards: src/arch/x86/id.S: Assembler messages: src/arch/x86/id.S:14: Error: value of 4294967344 too large for field of 4 bytes at 48 src/arch/x86/id.S:15: Error: value of 4294967327 too large for field of 4 bytes at 52 src/arch/x86/id.S:16: Error: value of 4294967318 too large for field of 4 bytes at 56 Change-Id: I9e13b15c062bc6598717382b1fedfa120c6d7209 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-21 10:58:37 +0000