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2024-03-17mb/google/nissa/var/anraggar: Add pen insert/remove for wakeupJianeng Ceng
Currently, inserting the pen does not wake the system, only removing the pen does. This is caused by the wake event configuration being DEASSERTED, so change it to ANY. BUG=b:328351027 TEST=insert and remove pen can wakes system up. Change-Id: Icdea995c2be04ea459e985f79269e49faf88248d Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-03-17mb/google/brya: Create bujia variantShon Wang
Create the bujia variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:327549688 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_BUJIA Change-Id: I453a50f1aa64f8d4119bf0f860d928aa3e00a144 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81198 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2024-03-17src/Kconfig: Make it possible to override CCACHE in site-localArthur Heymans
The value for CCACHE in site-local/Kconfig gets overridden by the default in src/Kconfig. Remove the default to make overrides possible. Change-Id: I6b9dbbb31caa3ef09afd7ecb355c01bd53807b39 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-17vc/amd/opensil: don't use source path when using stubMarshall Dawson
Add a 'depends on' statement so that path/to/opensil/source is only active when the stub is not built. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic050ff0fa3f428e6adff3357f476fcd8a88cdf7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/81189 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17soc/amd/phoenix: make openSIL stub optionalMarshall Dawson
Convert the 'select SOC_AMD_OPENSIL_STUB' statement to a config option and give it a prompt. This allows for internal development of openSIL and corresponding coreboot source, and controllable using a defconfig. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I2b48e2bbf71cd94ac7ecec13834ba36aa6c241ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/81188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-17soc/intel/mtl: Enable RAMTOP caching at SoC level for MTL devicesSubrata Banik
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration at the SoC level for all MTL devices. This change streamlines the configuration process, avoiding redundant selections on individual mainboards. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot functionality on google/ovis and google/rex. Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-17mb/google/rex: Reland RAMTOP caching for OvisSubrata Banik
This patch ensures Ovis baseboard can select RAMTOP caching to improve the boot time w/o any runtime hang. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis with ~30ms savings in boot time. Change-Id: Ic0b73eb8fb9cd6ca70d3d7168b79dfd0fbc550e3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-17soc/intel/cmn/ramtop: Refactor MTRR handling for RAMTOP rangeSubrata Banik
This patch refactors RAMTOP MTRR type selection to address a critical NEM logic bug on SoCs with non-power-of-two cache sets. This bug can cause runtime hangs when Write Back (WB) caching is enabled. Workaround: Force MTRR type to WC (Write Combining) on affected SoCs when the cache set count is not a power of two. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis and google/rex (including Ovis with non-power-of-two cache configuration). Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17arch/x86: Add API to check if cache sets are power-of-twoSubrata Banik
Introduce a function to determine whether the number of cache sets is a power of two. This aligns with common cache design practices that favor power-of-two counts for efficient indexing and addressing. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified functionality on google/ovis and google/rex (including a non-power-of-two Ovis configuration). Change-Id: I819e0d1aeb4c1dbe1cdf3115b2e172588a6e8da5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81268 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-16ec/hp/kbc1126/acpi: Drop unnecessary _STA methodsNicholas Sudsgaard
_STA unconditionally returning 0xF is pretty much the default[1] and should be removed to reduce some noise. [1] https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Device_Configuration.html#sta-device-status Change-Id: I0390767aa866e322c762038c12116a15b280af1a Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-16ec/hp/kbc1126/acpi: Drop unnecessary method argumentsNicholas Sudsgaard
Method(..., 0, NotSerialized) is the default[1] and can be reduced to Method(...) which reduces some noise. TEST=Timeless build produces the same binary [1] https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/19_ASL_Reference/ACPI_Source_Language_Reference.html#method-declare-control-method Change-Id: Ic24e004500a7fa2a5a5b38a3f6f0e13e4ce7dfac Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81205 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2024-03-15mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMeSeunghwan Kim
NVMe using clk_src[0] and clk_req[1] mapping to hardware design, Due to inconsistency between PMC firmware and FSP, we need to set clk_src to clk_req number, not same as hardware mapping in coreboot. Then swap correct setting to clk_src=0,clk_req=1 in mFIT. BUG=b:328318578 TEST=build firmware and veirfy suspend function on NVMe SKU DUT. Cq-Depend: chrome-internal:7063434 Change-Id: I1777310782a0f4417bd1bb21287bec5852be966e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81230 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-15brox: ish: Add Kconfigs for ISHYuval Peress
Modeled after the Rex Kconfigs for ISH. Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed Signed-off-by: Yuval Peress <peress@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81050 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-15treewide: Move stdlib.h to commonlibMaximilian Brune
This patch moves commonlib/stdlib.h -> commonlib/bsd/stdlib.h, since all code is BSD licensed anyway. It also moves some code from libpayloads stdlib.h to commonlib/bsd/stdlib.h so that it can be shared with coreboot. This is useful for a subsequent commit that adds devicetree.c into commonlib. Also we don't support DMA on arm platforms in coreboot (only libpayload) therefore `dma_malloc()` has been removed and `dma_coherent()` has been moved to architecture specific functions. Any architecture that tries to use `dma_coherent()` now will get a compile time error. In order to not break current platforms like mb/google/herobrine which make use of the commonlib/storage/sdhci.c controller which in turn uses `dma_coherent` a stub has been added to arch/arm64/dma.c. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I3a7ab0d1ddcc7ce9af121a61b4d4eafc9e563a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-14soc/intel/xeon_sp: Rewrite acpi_fill_dmarShuo Liu
Rewrite the function by iterating IOMMU (Input/Output Memory Management Unit) devices instead of iterating socket and stacks, which is more aligned to coreboot infrastructure. TEST=intel/archercity CRB coreboot DRHD generation is compared, the order of sections are changed as expected but the content is kept equvalient. Change-Id: I700513e05181303cf3f4effc793a872eb23340cb Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81228 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14soc/intel/xeon_sp: Rewrite acpi_create_drhdShuo Liu
Obtain IOMMU (Input/Output Memory Management Unit) info and enumerate devices using device utils instead of FSP HOB interface, which might change across SoC generations and no ambiguity across multiple PCIe segments. TEST=intel/archercity CRB coreboot DRHD generation log no changes before and after Change-Id: Ic5c404899172a0e4fba2721b8e8ca6c1f0856698 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81227 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14intelblocks/pmc: Assign initial values to pmc_gpe_init variablesGang Chen
pmc_gpe_init uses soc_get_gpi_gpe_configs to initialize dw0, dw1 and dw2. dw0, dw1 and dw2 are uninitialized before calling soc_get_gpi_gpe_configs. This is error prone for some soc implementations where soc_get_gpi_gpe_configs does nothing. This patch is simple, just to assign zero values to dw0, dw1 and dw0, to enhance the code robustness. TEST=intel/archercity CRB Signed-off-by: Gang Chen <gang.c.chen@intel.com> Change-Id: I8a710a2ac1482eed8c11977d51b187d834122d26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81210 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14arch/riscv: support physical memory protection (PMP) registersRonald G Minnich
PMP (Physical Memory Protection) is a feature of the RISC-V Privileged Architecture spec, that allows defining region(s) of the address space to be protected in a variety of ways: ranges for M mode can be protected against access from lower privilege levels, and M mode can be locked out of accessig to memory reserved for lower privilege levels. Limits on Read, Write, and Execute are allowed. In coreboot, we protect against Write and Execute of PMP code from lower levels, but allow Reading, so as to ease data structure access. PMP is not a security boundary, it is an accident prevention device. PMP is used here to protect persistent ramstage code that is used to support SBI, e.g. printk and some data structures. It also protects the SBI stacks. Note that there is one stack per hart. There are 512- and 1024-hart SoC's being built today, so the stack should be kept small. PMP is not a general purpose protection mechanism and it is easy to get around it. For example, S mode can stage a DMA that overwrites all the M mode code. PMP is, rather, a way to avoid simple accidents. It is understood that PMP depends on proper OS behavior to implement true SBI security (personal conversation with a RISC-V architect). Think of PMP as "Protection Minus Protection". PMP is also a very limited resource, as defined in the architecture. This language is instructive: "PMP entries are described by an 8-bit configuration register and one XLEN-bit address register. Some PMP settings additionally use the address register associated with the preceding PMP entry. Up to 16 PMP entries are supported. If any PMP entries are implemented, then all PMP CSRs must be implemented, but all PMP CSR fields are WARL and may be hardwired to zero. PMP CSRs are only accessible to M-mode." In other words if you implement PMP even a little, you have to impelement it all; but you can implement it in part by simply returning 0 for a pmpcfg. Also, PMP address registers (pmpaddr) don't have to implement all the bits. On a SiFive FU740, for example, PMP only implements bits 33:0, i.e. a 34 bit address. PMPs are just packed with all kinds of special cases. There are no requirements that you read back what you wrote to the pmpaddr registers. The earlier PMP code would die if the read did not match the write, but, since pmpaddr are WARL, that was not correct. An SoC can just decide it only does 4096-byte granularity, on TOR PMP types, and that is your problem if you wanted finer granulatiry. SoC's don't have to implement all the high order bits either. And, to reiterate, there is no requirement about which of the pmpcfg are implemented. Implementing just pmpcfg15 is allowed. The coreboot SBI code was written before PMP existed. In order for coreboot SBI code to work, this patch is necessary. With this change, a simple S-mode payload that calls SBI putchar works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Getting this to build on RV32 required changes to the API, as it was incorrect. In RV32, PMP entries are 34 bits. Hence, the setup_pmp needed to accept u64. So, uinptr_t can not be used, as on 32 bits they are only 32 bit numbers. The internal API uses uintptr_t, but the exported API uses u64, so external code does not have to think about right shifts on base and size. Errors are detected: an error in base and size will result in a BIOS_EMERG print, but not a panic. Boots not bricks if possible. There are small changes to the internal API to reduce stack pressure: there's no need to have two pmpcfg_t on the stack when one will do. TEST: Linux now boots partly on the SiFive unmatched. There are changes in flight on the coreboot SBI that will allow Linux to boot further, but they are out of scope for this patch. Currently, clk_ignore_unused is required, this requires a separate patch. Change-Id: I6edce139d340783148cbb446cde004ba96e67944 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-14soc/intel/xeon_sp: Add utils to detect domain0 and stack0Shuo Liu
In Xeon-SP, the domain0, which is located at stack0, usually needs special handling due to the compatible devices on it (HEPT, IO-APIC and legacy IOs). This patch adds util function detect whether a give domain or stack is with such a role. TEST=intel/archercity CRB Change-Id: I2f26b4ac54091c24c554f17964502c364288aa40 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-14soc/intel/xeon_sp: Add domain role checking utilsShuo Liu
For Xeon-SP, there are 4 main domain roles (PCIe/CXL/IOAT/UBOX). This patch adds util function to check whether a given domain belongs to one of these roles, or a give device belongs to a domain of the specific role. TEST=intel/archercity CRB Change-Id: I6b31c29564c774c27e86f55749ca9eca057a0cfe Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-14soc/intel/xeon_sp: Use common _CRS code generationPatrick Rudolph
Drop SoC specific code and use generic implementation provided by pci_domain_fill_ssdt. TEST=Booted on IBM/SBP1 to Ubuntu 22.04. TEST=intel/archercity CRB Change-Id: I8b0bc2eb02569b5d74f8521d79e0af8fee880c80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80796 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-14soc/intel/xeon_sp: Drop IIO_UDS argumentPatrick Rudolph
Use CONFIG_MAX_SOCKET instead of the IIO_UDS hob. Allows to drop the argument in Xeon-SP common layer. TEST=intel/archercity CRB Change-Id: I05ec127f2bf84d3c242c3b0bca9709a0a7a4b52b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81181 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-14ec/hp/kbc1126: Use ec/acpi/ec.h instead of its own implementationNicholas Sudsgaard
This also does some light cleaning up: - Place spaces in function names to make it easier to read. - Adds a newline to a console message. TEST=Tested to work on HP ProBook 450 G3 Change-Id: I73e60c5baa9db6874e480ecef41cf1006150e081 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81204 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14vendorcode/edk2-stable202302: Remove wchar_t assertsArthur Heymans
Remove those MSVC compiler defaults checks so that the GCC defaults for wchar_t can be used. The FSP interface does not depend on wchar_t. TEST: the resulting binaries are the same for intel/mtlrvp Change-Id: I0ee1abc7e9ba46665838b63a6cfe0f4aa300114c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-14mb/google/nissa/var/glassway: Add 2nd touchscreen via SSFC configFrank Chu
Define SSFC bit 0-1 in coreboot for add 2nd BOE G7500 touchscreen. BUG=b:329339069 BRANCH=firmware-nissa-15217.B TEST=Check touchscreen can detect and function work. [INFO ] input: GTCH7503:00 2A94:A804 as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-GTCH7503:00/0014 Change-Id: I85688919864e3cac1beb2442ef3e23fe9d5f916c Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-13mb/google/brox: Enable EC SW SyncShelley Chen
Now that EC software sync has been verified to work on Brox, we can enable it by default. BUG=b:326152804 BRANCH=None TEST=Verify that SW sync occurs Change-Id: I3d356c006fc448125605761f7328d1f1e203a7c4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81211 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13cbfs: Remove broken remnants of PAYLOAD_INFO featureJulius Werner
PAYLOAD_INFO is a very old feature that can add a key/value information section to a payload file. It seems to have only ever been generated by coreinfo and never really read by anything. Since CB:1721 in 2012, the feature has been inadvertently broken in practice since the `.note.pinfo` sections that contain the information get discarded from the payload before cbfstool gets to see them. Since CB:28647 in 2018, support for the section in the SELF loader was (inadvertently?) dropped, so if someone actually fed cbfstool a payload ELF that did have a `.note.pinfo` section, modern coreboot would refuse to boot the payload entirely (which is probably not a good state to leave things in). This patch removes the code to generate PAYLOAD_INFO entries entirely, but leaves the support to parse and extract those sections from old payloads in place in cbfstool. Change-Id: I40d8e9b76a171ebcdaa2eae02d54a1ca5e592c85 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-13Revert "soc/intel/xeon_sp: Rewrite acpi_create_drhd"Martin L Roth
This reverts commit 6995efbd1b986d0426ca513fd2e56771dd489f16. Reason for revert: Submitted out of order and broke the coreboot build: src/soc/intel/xeon_sp/uncore_acpi.c:275:6: error: call to undeclared function 'is_dev_on_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 275 | if (is_dev_on_domain0(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:343:35: error: call to undeclared function 'is_dev_on_ioat_domain'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 343 | if (CONFIG(HAVE_IOAT_DOMAINS) && is_dev_on_ioat_domain(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 423 | assert(vtd_mmio_cap != 0xffffffffffffffff); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 455 | assert(ptr); | ^~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:540:7: error: call to undeclared function 'is_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 540 | if (is_domain0(dev_get_pci_domain(dev))) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 546 | assert(iommu0); | ^~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ Change-Id: I8b66177119ea5f55913a16aae06a3dcb807c2c64 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-13Revert "soc/intel/xeon_sp: Rewrite acpi_fill_dmar"Martin L Roth
This reverts commit 6833e8c01afc2827f150135f3805dc71820ddaa4. Reason for revert: Submitted out of order and broke the coreboot build. src/soc/intel/xeon_sp/uncore_acpi.c:275:6: error: call to undeclared function 'is_dev_on_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 275 | if (is_dev_on_domain0(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:343:35: error: call to undeclared function 'is_dev_on_ioat_domain'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 343 | if (CONFIG(HAVE_IOAT_DOMAINS) && is_dev_on_ioat_domain(iommu)) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 423 | assert(vtd_mmio_cap != 0xffffffffffffffff); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:423:4: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 455 | assert(ptr); | ^~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:455:3: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ src/soc/intel/xeon_sp/uncore_acpi.c:540:7: error: call to undeclared function 'is_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 540 | if (is_domain0(dev_get_pci_domain(dev))) { | ^ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference] 546 | assert(iommu0); | ^~~~~~~~~~~~~~ src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^~~~~~~~~~~~~~~~~ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^~~~~~~~~~~~~~~~~~~~~~ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^~~~~~~~~~~~~~~~ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^~~~~~~~~~~~~~~~~~~~~ src/soc/intel/xeon_sp/uncore_acpi.c:546:2: note: consider using __builtin_trap() or qualifying pointer with 'volatile' src/include/assert.h:85:27: note: expanded from macro 'assert' 85 | #define assert(statement) ASSERT(statement) | ^ src/include/assert.h:56:7: note: expanded from macro 'ASSERT' 56 | if (!__build_time_assert(x) && !(x)) { \ | ^ src/include/assert.h:27:40: note: expanded from macro '__build_time_assert' 27 | (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) | ^ src/include/assert.h:105:2: note: expanded from macro 'dead_code_t' 105 | *(type *)(uintptr_t)0; \ | ^ Change-Id: If919d6fa578a82fbb6bc5e1fd2adf4e9f59cab95 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81232 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-13mb/google/brya/var/omniknight: Pull down USI_REPORT_EN in romstageJamie Chen
Pull down USI_REPORT_EN(GPP_C6) in romstage to solve an abnormal peek pull high before BL_EN. Because power sequence no meet spec, pre #comment36, it may have ghost touch. BUG=b:326337003 TEST=FW_NAME=omnigul emerge-brya coreboot, measurement of HW and test touch detection by evtest Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80769 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-03-13soc/intel/xeon_sp: Rewrite acpi_fill_dmarShuo Liu
Rewrite the function by iterating IOMMU (Input/Output Memory Management Unit) devices instead of iterating socket and stacks, which is more aligned to coreboot infrastructure. TEST=intel/archercity CRB coreboot DRHD generation is compared, the order of sections are changed as expected but the content is kept equvalient. Change-Id: I4c1cbf8d8fc93f746640efc3a82c539dcb3fdee2 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-13soc/intel/xeon_sp: Rewrite acpi_create_drhdShuo Liu
Obtain IOMMU (Input/Output Memory Management Unit) info and enumerate devices using device utils instead of FSP HOB interface, which might change across SoC generations and no ambiguity across multiple PCIe segments. TEST=intel/archercity CRB coreboot DRHD generation log no changes before and after Change-Id: Idcfa899c764ffe51db5ed202ead07ad7b6868864 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81048 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13soc/intel/mtl: Improve functions in soc_info.cTyler Wang
Remove debug message since it's static information. Remove additional uint_8 varience and return below settings directly: 1. CONFIG_SOC_INTEL_USB2_DEV_MAX 2. CONFIG_SOC_INTEL_USB3_DEV_MAX 3. MAX_TYPE_C_PORTS 4. CONFIG_MAX_TBT_ROOT_PORTS 5. CONFIG_MAX_ROOT_PORTS 6. CONFIG_MAX_PCIE_CLOCK_SRC 7. CONFIG_SOC_INTEL_UART_DEV_MAX 8. CONFIG_SOC_INTEL_I2C_DEV_MAX 9. CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX BUG=none TEST=Build and test on rex/karis, system can boot to OS Change-Id: I26e882d2d9dcbef84718924aaab3864d89c58f39 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-03-13soc/intel/xeon_sp: Add device find utilsShuo Liu
For Xeon-SP, it's common pattern to find devices under specific socket, stack and domain. This patch adds util function for these operations. TEST=intel/archercity CRB Change-Id: I163eacae363334919fd66d571b7e0415e77bd52d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-12mb/amd/birman_plus: Update glinda DXIO descriptors per schematicsAnand Vaikar
glinda FP8 SOC PCIe lanes are updated per the Birman+ schematics document 105-D99700-00C revision 1.0. Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81036 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-12mb/google/brya/var/xol: Use unified AP FW for UFS/Non-UFS SKUsSeunghwan Kim
Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS to use unified AP FW for UFS/Non-UFS SKUs. BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I85c3c1c7ccaae9d46b66d3e7a2efea6dc9056188 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81107 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-12soc/intel/common/block: Add support for watchdogMarek Maslanka
Implement watchdog for intel based platform by filling ACPI Watchdog Action Table (WDAT) table. The WDAT ACPI table encompasses essential watchdog functions, including: - Setting and retrieving countdown/timeout values - Starting and stopping the watchdog - Pinging the watchdog - Retrieving the cause of the last reboot, whether it was triggered by the watchdog or another reason The general purpose register TCO_MESSAGE1 stores the reason for the most recent reboot rather than the original register TCO2_STS. This is because the firmware must clear TCO2_STS, and it can't be reused for storing this information for the operating system. The watchdog is designed for use by the OS through certain defined actions in the WDAT table. It relies on the ACPI Power Management Timer, which may result in an increase in power consumption. BUG=b:314260167 TEST=Enable CONFIG_ACPI_WDAT_WDT and CONFIG_USE_PM_ACPI_TIMER in the config. Enable CONFIG_WDAT_WDT in the kernel config. Build and deploy both firmware and kernel to the device. Trigger the watchdog by performing the command: “cat > /dev/watchdog”. Wait approximately 30 seconds for the watchdog to reset the device. Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-12soc/intel/xeon_sp: Rewrite acpi_create_satcShuo Liu
SATC is for RCiEPs (Root Complex Integrated EndPoints) but not limited to IOAT domains. Rewrite the func by iterating all domains and its RCiEPs. Currently the codes only support 1 PCIe segment. TEST=intel/archercity CRB coreboot SATC generation logs are unchanged before and after. Change-Id: I1dfc56ccf279b77cfab4ae3457aa8799d2d57a34 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81049 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-12soc/intel/xeon_sp: Create CXL domainsShuo Liu
SPR CXL IIO stack is divided into 2 PCI domains. The 1st domain is a PCI domain with single bus number and PCIe RCiEPs (Root Complex Integrated End Points) on it. The 2nd domain is a CXL domain with remaining buses for CXL 1.0/1.1 end points and possible SR-IOV (Single Root IO Virtualizaton) VFs (Virtual Function) if any. TEST=intel/archercity CRB P.S. The SUT is not with CXL cards however we hope this refactor could be integrated first as an improvement of the design. Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81099 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-11mb/google/brya: Create nova variantDavid Wu
Create the nova variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:328711879 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_NOVA Change-Id: Ie1cee43f0e2545288130bcc5152075603695c395 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
2024-03-11vc/amd/opensil/stub: add stub MPIO driverFelix Held
Add a stub MPIO chip driver to the openSIL stub code, so that the devicetree entries needed for the MPIO chip can already be added to the mainboard's devicetree files. This driver won't do anything, but still allows the register settings in the devicetree to be set to make switching over to the actual openSIL code and the corresponding glue code easier. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4f5c232859b9abcd10bfa5c21e2f2c3a70b4b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/81100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-09drivers/intel/fsp2_0: Perform MP init post FSP-MultiPhase SI InitJeremy Compostella
FSP can also make use of Multi-Processor services during its multi-phase stages. If `USE_INTEL_FSP_MP_INIT' is set and `USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI' unset coreboot cannot take MP ownership as FSP-S may still use EDK2 MP services concurrently. TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec92 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80691 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09arch/riscv: Remove typedefsMaximilian Brune
typedefs violate our coding-style Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81124 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-09soc/intel/common/mp_init: Fix USE_INTEL_FSP_MP_INIT use-caseJeremy Compostella
Commit 829e8e65b939 ("soc/intel: Use common codeflow for MP init") brokes `USE_INTEL_FSP_MP_INIT' by making `init_cpus' function static. This function needs to be accessible from src/drivers/intel/fsp2_0/fsp_mpinit.c. TEST=Verified on Meteor Lake rex board Change-Id: Idb8cdfef7b4279da2c7dff344c95fe446a605934 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09soc/intel/alderlake: Add Raptor Lake System Agent Device IDsLean Sheng Tan
Add System Agent IDs for Raptor Lake SKUs based on RPL Datasheet (Doc ID: 743844) & EDS Vol 1 (Doc ID: 640555). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/81115 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09soc/intel/xeon_sp: Further share domain creation logics in Xeon-SPShuo Liu
With this patch, all domain creation logics are moved into the scope of attach_iio_stack/chip_common.c for the ease of maintenance and future SoC integration where the domain creation process for specific stack types might be overridden. TEST=intel/archercity CRB 1. Boot to CentOS 9 Stream Cloud. 2. Compare PCIe enumeration and ACPI table generation logs before and and after this patch, no changes. Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81098 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09drivers/spi: Add GD25LR256E supportMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id405ed990101a1ceda5e09c6db835f8302047f5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/81125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09mb/google/brya/var/xol: Disable unused controllersSeunghwan Kim
Disable unused controllers in overridetree.cb by referring to xol proto2 schematics. Enabling unused controllers blocks entering s0ix. - I2C3 - SATA - PCIE RP8 - PCIE RP9 - GSPI1 BUG=b:328318578 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I1be7caf8234c32406aa2cff8fc7fe9fa39b16d89 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81105 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09mb/google/brya/var/xol: Update psys_pmax value to 122WSeunghwan Kim
Update psys_pmax value to 122 from 145. This value is from internal power team. BUG=None BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I8bc58343d5736e2457db006972dc229e16d3fe59 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81104 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09mb/google/brya/var/xol: Configure Acoustic noise mitigationSeunghwan Kim
Enable Acoustic noise mitigation for xol. The setting values are from internal power team. - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=None TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I6165ae6ca73d1467a1d2cc7bd545298bd4c2f54f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-09arch/riscv: Add SMP support for exception handlerXiang Wang
Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618 Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68841 Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-09mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine typeFelix Held
Explicitly assign the 'PCIE' value to the 'type' field of the corresponding MPIO chips in the devicetree. Since the mpio_type enum element 'PCIE' has the value 0, this won't change the behavior, but explicitly assigning this makes this easier to understand. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I84a364cf16c99ba11f67cf033962bbf2c982f6ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/81095 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09soc/intel/alderlake: Remove the guard for CnviWifiCoreSean Rhodes
The CnviWifiCore UPD exists for ADL (version 4263) and RPL (version 4415). Remove the guard so it is set correctly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9943ee43a442a43d75e78d1551e46dcea39db357 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81079 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09mb/google/brox: Enable Wake on WLAN for SKU1Ashish Kumar Mishra
For SKU1, wake pin is WLAN_PCIE_WAKE_ODL. Update gpio config and corresponding ACPI for WoWLAN. BUG=b:327379404 BRANCH=None TEST=Boot image on SKU1 and check Wake on WLAN from S0ix. Change-Id: I04c35da2c9ac57cafdf7f7a35d83ab2e7a05fe4a Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-09cpu/x86/smm: Set up page tables in safe SMRAMArthur Heymans
Relying on page tables being in RO flash is not safe in every setup, therefore set up some page tables in SMRAM that the permanent smihandler can use. Tested on QEMU. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Icb3086abd577b9abb9966dd910a264a873ace4ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/80336 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-08drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 supportJeremy Compostella
Intel Firmware Support Package 2.4 specification (document 736809) brings some significant changes compared to version 2.3 (document 644852): 1. It supports FSP-M multi-phase init. Some fields have been added to the FSP header data structure for this purpose. 2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively. 3. It support 64-bits FSP but 64-bits support will be provided by subsequent patch. Note that similarly to what is done for silicon initialization, timestamps and post-codes are used during the memory initialization multi-phase. [736809] https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf [644852] https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-External-Architecture-Specification.pdf TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-03-08drivers/intel/fsp2_0: Add "silicon" to the multiphase callback nameJeremy Compostella
The `platform_fsp_multi_phase_init_cb' callback is specific to FSP-S, let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid any confusion. Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-08vc/intel/fsp/mtl: Update header files from 3471_85 to 3471_91Ronak Kanabar
Update header files for FSP for Meteor Lake platform to version 3471_91, previous version being 3471_85. FSPM: 1. Address offset changes BUG=b:327688959 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I5a71232018dfefec63b0a83d1e87717e238a4a0a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80782 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07soc/intel/xeon_sp/spr: Fix IOAT resourcesPatrick Rudolph
Do not generate empty mem32 resources for CPMx or HQMx stacks. Switch existing arguments to make sure that base is bigger than limit to indicate that the resource is invalid. Change-Id: I679563e97c33c7ee35d402674972e55f521eafa8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80793 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07soc/intel/xeon_sp: Share numa.c among Xeon-SP platformsShuo Liu
NUMA will be supported by SPR and future generations. TEST=intel/archercity CRB Change-Id: I0d494f8e560059d9c8d5338cef9a6ffe34e59e26 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-07soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platformsJincheng Li
TEST=intel/archercity CRB Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04 Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81041 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07soc/intel/xeon_sp: Add memory type check utilsShuo Liu
FSP memory type representations change across Xeon-SP SoCs. This patch adds type check utils to abstract the differences. TEST=intel/archercity CRB Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-06arch/riscv: Makefile.mk: Fix incorrect config variableRonald G Minnich
ARCH_RISCV_PMP should be CONFIG_ARCH_RISCV_PMP. Rename it. Change-Id: I2a22acae5cd9f30e01c491653bf7fc7b7765d815 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81086 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-06vc/amd/opensil/genoa_poc/memmap: use GiB defineFelix Held
Use the GiB define to make the 4 GiB boundary used in some places in the code a bit easier to read. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81877a5d293c883d2e31bdb18ae3b22b8a44e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-06vc/amd/opensil/genoa_poc/memmap: use get_top_of_mem_below_4gbFelix Held
Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5885e9ad89ed9f0aa657c56804e98c352267267f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-06soc/intel/xeon_sp: Add ACPI namesPatrick Rudolph
Set the unused 'name' property of the domain device and store the ACPI name. Every IIO stack can have multiple domain devices, each owning a subset of the available bus range within the stack. The name will be used in future changes to generate ACPI names in SSDT code generation. It can also be used to identify the domain type by looking at the first two characters of the name. Change-Id: Ic4cc81d198fb88300394055682a3954bf22db570 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80792 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-06mb/google/nissa/var/glassway: Tune eMMC DLL valuesDaniel Peng
Update eMMC DLL values to improve initialization reliability. BUG=b:327123701 TEST=Improve reboot on MB with eMMC smoothly. Change-Id: Ice9ee217acf7dc6e3e704bc82529e0b9a8faf184 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80779 Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Yang <simon1.yang@intel.com>
2024-03-06mb/sifive/sifive-unmatched: add support for spi1 x4 modeRonald G Minnich
Tested on an unmatched, both SPI1 x1 and x4 work now. Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05soc/intel: Add definition of D0 stepping for TigerLake HaloAlicja Michalska
Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E portsAlicja Michalska
ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in OS complaining about interrupt routing. 'pcieport 0000:00:06.0: can't derive routing for PCI INT A' 'nvme 0000:04:00.0: PCI INT A: not connected' 'Interrupt: pin A routed to IRQ -2147483648' TEST=Boot Linux and Windows 10 on TGL-H platform with PEG0/PEG1 populated with PCI-E devices - Radeon RX 7800XT and Kingston KC3000 NVME SSD. Check logs and stability while running 3D application and disk benchmark at the same time. Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80848 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SPShuo Liu
Move MEM_ADDR_64MB_SHIFT_BITS from FSP headers to Xeon-SP common layer to reduce the dependency. TEST=intel/archercity CRB Change-Id: I4e1a652ad58233f7514cb9b23813d75144b8d435 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-05mb/google/oak: Don't build the ChromeEC codebase by defaultMartin Roth
Currently, the oak boards are the only boards that build the ChromeEC by default as a part of the coreboot build. As a part of replacing the chromeec submodule with a different build mechanism, disable this default. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Idd4fe45e52dbdd1c8dccf0d2c09d5cf6d61aa839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81023 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-03-05drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bugArthur Heymans
Starting with Intel CPX there is a bug in the reference code during the Pipe init. This code synchronises the CAR between sockets in FSP-M. This code implicitly assumes that the FSP heap is right above the RC heap, where both of them are located at the bottom part of CAR. Work around this issue by making that implicit assumption done in FSP explicit in the coreboot linker script and allocation. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80579 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-05lib/program.ld: Make (NOLOAD) and to_load more explicitArthur Heymans
(NOLOAD) indicates that the section occupies no space in the file, but does take up space in memory during process execution. It's typically used for bss sections which contain uninitialized global/static variables. to_load makes sure the section is part of the program headers. This is needed for instance with relocatable stages to know how much memory the program will use. Although the BFD linker makes some good guesses making this a NOOP, other linkers like LLD need to mark these sections more explicitly. Change-Id: Ic14543ba580abe7a34c69bba714eae8cce504977 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80803 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-03-05mb/emulation/qemu-riscv: Change to -bios optionMaximilian Brune
This changes the virt target so that it can be run with the -bios option and a pflash backend for the flash. QEMU can now be run as follows: qemu -M virt -m 1G -nographic -bios build/coreboot.rom \ -drive if=pflash,file=./build/coreboot.rom,format=raw coreboot will start in DRAM, but still have a flash to put CBFS onto and to load subsequent stages and payload from. Tested bootflow: coreboot -> OpenSBI -> Linux -> u-root Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-05mb/asus/p8x7x-series: Revert to native max_mem_clock_mhz of 800Keith Hui
The setting was reduced to 666 for native raminit in commit 7039edd2da30 (SNB+MRC boards: Migrate MRC settings to devicetree) based on boot test results at the time. With more changes merged, additional native raminit tests were done on p8z77-m. It is now possible for previously failing memory configurations to operate at full speed. This, combined with multiple reports on gerrit that this family does work at 800, warrants returning the setting to what it was. Change-Id: I1fbe9c8d076fcd633f71424d60585681c40677c4 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79726 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-05Revert "vc/intel/edk2: Remove edk2-stable202111 support"Ronak Kanabar
This reverts commit b5f6320c694766d10023fe8f5183c9c143441b2b. ADL-N FSP uses 202111 Edk2. There are structure definition changes between 202005 and 202111. One of change is in FSP_INFO_HEADER structure. This patch is to bring back support of edk2-stable202111. BUG=b:296433836 TEST=Able to build google/crassk. Change-Id: Id1d3e2c5b368a479e637f3ab3d18e242607849ed Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-05ec/google/chromeec: Enclose Kconfig in 'if/endif' blockMartin Roth
Instead of having things depend on EC_GOOGLE_CHROMEEC, just put an if/ endif block around the configs. The 'source' line stays outside of the if block because the source always happens, even if it's inside an if/endif block. Each of the sub-Kconfigs here already has an if/endif block surrounding the contents. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If88ba7d36ae04d879332037292c5cf9a3c8c3cab Reviewed-on: https://review.coreboot.org/c/coreboot/+/81025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-03-05mb/google/brya/var/xol: Add VGPIO configurations for PEG60Seunghwan Kim
Add VGPIO configurations for NVMe on PEG60. BUG=b:326481458, b:372086400 BRANCH=firmware-brya-14505.B TEST=Verified DUT could detect NVMe. Install ChromeOS into NVMe and boot from it. Change-Id: I5520dc2a4bf6e788701a774674d223b7e8ad5b44 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-05mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanelYunlong Jia
Add FW_CONFIG probe to separate touch panel settings. TOUCH_PANEL_ENABLE/TOUCH_PANEL_DISABLE Use different gpio tables based on the value of TOUCH_PANEL. BUG=b:325987249 TEST=emerge-nissa coreboot and run in DUT Change-Id: I23c62406a932815ff1cfafe05b70468b1f9cca54 Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kyle Lin <kylelinck@google.com>
2024-03-05soc/intel/xeon_sp: Drop unused helper functionsPatrick Rudolph
Change-Id: Ib319643f6b0b91d8c5854da531e035d333f04d75 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80143 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-05soc/intel/xeon_sp: Drop code to locate the UBOX busPatrick Rudolph
Drop the code to retrieve the UBOX bus numbers. Only keep a minial function that works when called from socket0 to retrieve the bus for UBOX(1). Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80102 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-05soc/intel/xeon_sp/util: Enhance lock_pam0123Patrick Rudolph
- Only compile code in ramstage - Lock PAM on all sockets - Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID. This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree. Change-Id: Ic8b3bfee8f0d02790620280b30a9dc9a05da1be8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-05soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSIONSubrata Banik
This patch marks CONFIG_SOC_INTEL_CSE_RW_VERSION as deprecated, as future platforms will automatically determine the CSE RW version using CSE RW partition. BUG=b:327842062 TEST=CSE RW update successful on Screebo. Change-Id: I8c3e5c759e4d9a43c3bce3a0c032086f17592a67 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80924 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2024-03-05vc/google/chromeos: Implement dynamic ChromeOS boot logo selectionSubrata Banik
* Introduces logic to display context-specific boot splash logos. * Logo selection considers: * Chromebook-Plus hardware compliance (using factory_config). * VPD-based product segmentation (soft-branded vs. regular chromebook). * Default Chromebook logo as fallback for regular Chromebook. This patch fixes the problem where existing logic was unable to pick correct ChromeOS boot splash logo based on the product segmentation. Relation between product segment and boot splash screen: 1. Chromebook-Plus Hard-branded device: Renders "cb_plus_logo.bmp" logo 2. Chromebook-Plus Soft-branded device: Renders "cb_plus_logo.bmp" logo 3. Regular Chromebook device: Renders "cb_logo.bmp" BUG=b:324107408 TEST=Verified logo selection based on compliance and product requirements. Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-05drivers/vpd: Add vpd_get_feature_level() APISubrata Banik
This patch introduces the vpd_get_feature_level() API to specifically extract the "feature_level" field from the "feature_device_info" VPD key. This is used to distinguish between Chromebook-Plus and regular Chromebook devices. The previous vpd_get_feature_device_info() API is removed as vpd_get_feature_level() is enough to find VPD and extract the data. Note: The new API decodes the base64-encoded "feature_device_info" VPD data. BUG=b:324107408 TEST=Able to build and boot google/rex0. Change-Id: I76fc220ed792abdfefb0b1a37873b5b828bfdda8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80805 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-05mb/google/brya/var/dochi: Add wifi sar tableMorris Hsu
Add wifi sar table for dochi BUG=b:326137130 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Iaf90756eb318bef1ffcda9368a976c0ca209a100 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-04riscv/mb/qemu: fix DRAM probingPhilipp Hug
Current version of qemu raise an exception when accessing invalid memory. Modify the probing code to temporary redirect the exception handler like on ARM platform. Also move saving of the stack frame out to trap_util.S to have all at the same place for a future rewrite. TEST=boots to ramstage Change-Id: I25860f688c7546714f6fdbce8c8f96da6400813c Signed-off-by: Philipp Hug <philipp@hug.cx> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36486 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/google/guybrush: turn off SD ASPM L1.1/L1.2JasonNien
Turn off SD ASPM L1.1/L1.2 as w/a for wlan DMA resume failure We completed 4 runs for each of the 2 tests - power_idle and power_VideoCall. Here are the averages for both the tests: L1ss disabled SD plugged power idle test: 735.3875 L1ss enabled SD plugged power idle test: 737.2335 L1ss disabled SD plugged power video test: 333.29325 L1ss enabled SD plugged power video test: 333.442 BUG=b:254382832 TEST=test pass over 10k cycles Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I4d903f0f6333ffa18069e42be3c932aeae8013d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80237 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04lib/ramdetect: Limit probe size to function argumentArthur Heymans
This avoids probing above the function argument where other things than DRAM could be mapped. Change-Id: Ie7f915c6e150629eff235ee94719172467a54db2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-03-04arch/x86/Kconfig: Deduplicate ARCH_SUPPORTS_CLANG selectionElyes Haouas
Change-Id: Iced69e0bce345748a43eb1c14bf17a683e26ba60 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81020 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-04mb/dell: Add OptiPlex 7020/9020 portMate Kukri
The OptiPlex 7020 and 9020 use physically identical motherboards. WARNING: PWM fan control doesn't work via the EC and the fan runs at a fixed speed. There is likely more EC init to reverse engineer. Each model comes in the following form factors: - 7020: SFF, MT - 9020: USFF (not currently supported), SFF, MT (7020 SFF) Boots Linux and Windows 10: - Tested with an i3-4160 and i5-4460 - DRAM init works using the MRC (4G, 4G+4G) - iGPU init works using libgfxinit (VGA, 2x DP) - PCIe 16x: tested, ok - PCIe 4x: tested, ok - All USB2 and USB3 ports work - SMSC SCH5555 Super I/O: serial works, PS/2 untested - Audio: back and front output works, internal speaker works, mic inputs untested - Ethernet: tested, works (9020 MT) - Tested by Michael Büchler (thanks for the overridetree) Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55232 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-03-04nb/haswell: Disable iGPU when dGPU is usedLeah Rowe
This is usually is handled by Haswell mrc.bin, disabling VGA decode on the iGPU when a dGPU is installed. However, Broadwell mrc.bin does not, so the iGPU and dGPU are both enabled. This patch disables legacy VGA cycles for iGPU, under such conditions. It has been tested on Broadwell mrc.bin when using a graphics card on Dell OptiPlex 9020 SFF (currently under review at this time of writing, submitted by Mate Kukri). This patch has also been tested when Haswell mrc.bin is used, and there are seemingly no breaking changes caused by it. Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b Signed-off-by: Leah Rowe <info@minifree.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-04mb/google/brya: Enable CSE telemetry for ADL-NKapil Porwal
BUG=none TEST=Verify CSE telemetry data in boot time data on Yahiko. Before: ``` yahiko-rev9 ~ # cbmem -t 71 entries total: 0:1st timestamp 197,583 (0) ``` After: ``` yahiko-rev9 ~ # cbmem -t 76 entries total: 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 49,000 945:CSE started to handle ICC configuration 49,000 (0) 946:CSE sent 'Host BIOS Prep Done' to PMC 51,000 (2,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 168,000 (117,000) 0:1st timestamp 195,861 (27,861) ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3f90d0462cb766655bf8e59a90bc550ceefb2256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79768 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/system76/adl,rpl: Add 50ms timeout for PCIe 3.0 RPsTim Crawford
The FSP may fail to detect PCIe 4.0 devices in PCIe 3.0 slots on S3 resume. This issue has only been experienced on lemp12, and only with Samsung drives, but implies it could happen on other systems or with other drives as well. A timeout of 50ms is arbitrarily chosen. Tested on lemp12 with Samsung 980 PRO (FW: 3B2QGXA7, 5B2QGXA7) and 990 PRO (FW: 4B2QJXD7) drives. Change-Id: I4f44fc429c52e407b7566d6bb6dd31b2cf85c48d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80756 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/system76/adl: Remove duplicate PchHdaAudioLinkHdaEnableTim Crawford
This UPD is hooked up in devicetree since commit 854bd492fcfa ("mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetree"). As these boards were in development when the change happened, they still had the UPD set via romstage. Remove them now so they are only set in devicetree. Change-Id: I393e2c7b0134a31feae20f8992d7fd447ff7ee59 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80755 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-03-04mb/system76/adl,rpl: Enable PchHdaSdiEnableTim Crawford
Commit 4a58d14506ef ("soc/intel/alderlake: Hook up UPD PchHdaSdiEnable") and commit 2d482386182e ("soc/intel/alderlake: Set PchHdaSdiEnable for Alder Lake") hooked up this UPD in devicetree, causing the FSP default to be overridden (now disabled by default). Enable SDI to fix the following error: [DEBUG] PCI: 00:00:1f.3 init [DEBUG] azalia_audio: base = 0xbfbcc000 [DEBUG] azalia_audio: No codec! [DEBUG] PCI: 00:00:1f.3 init finished in 5 msecs Tested on gaze17-3050: Speaker output works again. Change-Id: Iceac1faec939ce9eea68c335929f96ec5f2bd132 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-03-04mb/system76/rpl: Add TCSS ACPI for all boardsDan Campbell
Fixes ACPI errors about missing methods: ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TDM0], AE_NOT_FOUND (20230628/dswload2-162) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220) ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x0010) ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TRP0], AE_NOT_FOUND (20230628/dswload2-162) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220) Tested on lemp12: ACPI errors in dmesg are gone. Change-Id: I9b79cb04f57a27af2a6c8f3118e573f7ac0041e5 Signed-off-by: Dan Campbell <dan@compiledworks.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80791 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/google/brox: Update Verbtable for beep functionalitypoornima tom
For boot beep functionality, relevant register values are required to be updated. BUG=b:324528901 BRANCH=None TEST=Build & verified Boot Beep functionality on Brox Change-Id: If236c8ac173a279db676af412377fa4e4122c1cd Signed-off-by: poornima tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80416 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entrySubrata Banik
This patch automates the process of determining the CSE RW version used for the CBFS entry, eliminating the need for manual configuration in CONFIG_SOC_INTEL_CSE_RW_VERSION. How to get CSE RW Version: 1. Open CSE RW file as per CONFIG_SOC_INTEL_CSE_RW_FILE 2. Read offset 16 (0x10) to know the CSE version 3. Format: - CSE_VERSION_MAJOR : offset 16-17 - CSE_VERSION_MINOR : offset 18-19 - CSE_VERSION_HOTFIX: offset 20-21 - CSE_VERSION_HOTFIX: offset 22-23 Benefits: - Removes error-prone manual version updates. - Prevents boot loops due to mismatched CSE RW versions (actual vs config) - Eliminates the need for SKU-specific CSE version limitations. BUG=b:327842062 TEST=CSE RW update successful on Screebo with this patch. Example Debug Output: [DEBUG] cse_lite: RO version = 18.0.5.2066 [DEBUG] cse_lite: RW version = 18.0.5.2107 Change-Id: I0165d81b0e4b38e0e097956f250bb7484d774145 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80923 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>