soc/intel/xeon_sp: Drop IIO_UDS argument

Use CONFIG_MAX_SOCKET instead of the IIO_UDS hob.
Allows to drop the argument in Xeon-SP common layer.

TEST=intel/archercity CRB

Change-Id: I05ec127f2bf84d3c242c3b0bca9709a0a7a4b52b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81181
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

3 files changed, 7 insertions, 7 deletions

diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c
index 0cc0931e7d..11913d354c 100644
--- a/src/soc/intel/xeon_sp/acpi.c
+++ b/src/soc/intel/xeon_sp/acpi.c
@@ -99,10 +99,9 @@ size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[])
 
 	*ioapic_bases = xeonsp_ioapic_bases;
 
-	for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; socket++) {
+	for (int socket = 0; socket < CONFIG_MAX_SOCKET; socket++) {
 		if (!soc_cpu_is_enabled(socket))
 			continue;
-		iio++;
 		for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
 			const STACK_RES *ri =
 				&hob->PlatformData.IIO_resource[socket].StackRes[stack];
diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c
index da97d1af40..853b6bf918 100644
--- a/src/soc/intel/xeon_sp/chip_common.c
+++ b/src/soc/intel/xeon_sp/chip_common.c
@@ -373,7 +373,9 @@ void attach_iio_stacks(void)
 		return;
 
 	struct bus *root_bus = dev_root.downstream;
-	for (int s = 0; s < hob->PlatformData.numofIIO; ++s) {
+	for (int s = 0; s < CONFIG_MAX_SOCKET; ++s) {
+		if (!soc_cpu_is_enabled(s))
+			continue;
 		for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) {
 			const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
 			if (ri->BusBase > ri->BusLimit)
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index bee6a3b41d..96a2b3f75a 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -379,7 +379,7 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket,
 	return current;
 }
 
-static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob)
+static unsigned long acpi_create_atsr(unsigned long current)
 {
 	struct device *child, *dev;
 	struct resource *resource;
@@ -391,10 +391,9 @@ static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob)
 	 * This is easier than to sort the host bridges by PCI segment group first
 	 * and then generate one ATSR header for every new segment.
 	 */
-	for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) {
+	for (int socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) {
 		if (!soc_cpu_is_enabled(socket))
 			continue;
-		iio++;
 		unsigned long tmp = current;
 		bool first = true;
 
@@ -542,7 +541,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
 	current = acpi_create_rmrr(current);
 
 	// Root Port ATS Capability
-	current = acpi_create_atsr(current, hob);
+	current = acpi_create_atsr(current);
 
 	// RHSA
 	current = acpi_create_rhsa(current);